m29w128f
November 2006 Rev 61/78
M29W128FH M29W128FL
128 Mbit (8Mb x 16 or 16Mb x 8, Page, Uniform Block)
3V Supply Flash Memory
Feature summary
■
Supply voltage
–V CC = 2.7 to 3.6V for Program, Erase and Read
–V PP =12V for Fast Program (optional)■
Asynchronous Random/Page Read –Page Width: 8 Words/16 Bytes –Page Access: 25, 30ns –Random Access: 60, 70ns ■
Programming time
–10μs per Byte/Word (typical)– 4 Words / 8 Bytes Program
–32-Word (64-Bytes) Write Buffer ■64 KByte (32 KWord) Uniform Blocks
■
Program/ Erase Suspend and Resume Modes –Read from any Block during Program Suspend
–Read and Program another Block during Erase Suspend ■
Unlock Bypass Program
–Faster Production/Batch Programming ■
Common Flash Interface –64 bit Security Code
■100,000 Program/Erase cycles per block ■
Low power consumption
–Standby and Automatic Standby ■
Hardware Block Protection
–V PP protect of the highest (M29W128FH) or lowest block (M29W128FL) ■
Extended Memory Block:
Extra block used as security block or to store additional information
■
Electronic Signature
–Manufacturer Code: 0020h –Device Code:
M29W128FH: 227Eh + 2212h + 228Ah M29W128FL: 227Eh + 2212h + 228Bh ■
ECOPACK ? packages
https://www.wendangku.net/doc/4b2119103.html,
Contents M29W128FH, M29W128FL
Contents
1Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 12
2.5Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8V PP/Write Protect (V PP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12V CC supply voltage (2.7V to
3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.13V ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6Special Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.1Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.2Verify Extended Memory Block Protection Indicator . . . . . . . . . . . . . . . 17
3.6.3Verify Block Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.4Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.5Temporary Unprotect of high voltage Protected Blocks . . . . . . . . . . . . . 18
4Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/78
M29W128FH, M29W128FL Contents
4.2Temporary Block Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.3Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.4Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.6Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.8Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.9Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.10Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.1Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.2Write to Buffer and Program Confirm command . . . . . . . . . . . . . . . . . . 29
5.2.3Write to Buffer and Program Abort and Reset command . . . . . . . . . . . 29
5.2.4Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.5Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.6Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.7Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.8Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.9Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.10Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.11Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3Extended Memory Block Protection commands . . . . . . . . . . . . . . . . . . . 34
5.3.1Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.2Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0.1Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0.2Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0.3Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.0.4Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.0.5Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.0.6Write to Buffer and Program Abort Bit (DQ1) . . . . . . . . . . . . . . . . . . . . 38
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Contents M29W128FH, M29W128FL 7Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Appendix A Block addresses and Read/Modify Protection Groups . . . . . . . . . 54 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Appendix C Extended Memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
C.1Factory Locked Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . 67
C.2Customer Lockable Extended Memory Block. . . . . . . . . . . . . . . . . . . . . . 68
Appendix D High Voltage Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
D.1Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
D.2In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Appendix E Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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M29W128FH, M29W128FL List of tables List of tables
Table 1.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.Bus operations, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3.Read Electronic Signature, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4.Block Protection, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5.Bus operations, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6.Read Electronic Signature, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7.Block Protection, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8.Hardware Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 9.Standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10.Standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11.Fast Program commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 12.Fast Program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13.Extended Block Protection commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 14.Block Protection commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 15.Program, Erase Times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . 36 Table 16.Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 17.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 18.Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 19.Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 20.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 21.Read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 22.Write AC characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23.Write AC characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 24.Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 25.TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data . . . 51 Table 26.TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data. . . . . . . 52 Table 27.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 28.Block Addresses and Protection Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 29.Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 30.CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 31.CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 32.Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 33.Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 34.Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 35.Extended Memory Block Address and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 36.Programmer technique Bus operations, 8-bit or 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . 70 Table 37.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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List of figures M29W128FH, M29W128FL List of figures
Figure 1.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2.TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3.TBGA connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4.Block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5.Data Polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 6.Toggle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 7.AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 8.AC measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 9.Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 10.Page Read AC waveforms (Word mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 11.Write AC waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 12.Write AC waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 13.Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing) . . . . . . . 49 Figure 14.Reset/Block Temporary Unprotect during Program/Erase operation AC waveforms. . . . . 49 Figure 15.Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 16.TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package outline. . . . . . . . . . . 51 Figure 17.TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline . . . . . . . . . . . . . . 52 Figure 18.Programmer equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 19.Programmer equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 20.In-System equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 21.In-System equipment Chip Unprotect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 22.Write to Buffer and Program flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . 75 6/78
M29W128FH, M29W128FL Summary description
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1 Summary description
The M29W128FH and M29W128FL are 128 Mbit (16Mb x8 or 8Mb x16) non-volatile
memories that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. At Power-up the memories default to Read mode. The M29W128FH and M29W128FL are divided into 256 thirty-two KWord (sixty-four KByte) uniform blocks.
Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the
memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
The Chip Enable, Output Enable and Write Enable signals control the bus operations of the memory. They allow simple connection to most microprocessors, often without additional logic.
The devices support Asynchronous Random Read and Page Read from all blocks of the memory array.
The M29W128FH and M29W128FL have an extra 128 Word (256 Byte) Extended Memory Block that can be accessed using a dedicated command. The Extended Memory Block can be protected and so is useful for storing security information. However the protection is irreversible, once protected the protection cannot be undone.
Each block can be erased independently, so it is possible to preserve valid data while old data is erased.
The devices feature two different levels of hardware block protection to avoid unwanted program or erase (modify):
●The V PP on the M29W128FL.
●
The RP pin temporarily unprotects all the blocks previously protected using a High Voltage Block Protection technique (see Appendix D: High Voltage Block Protection ).
The memories are offered in TSOP56 (14 x 20mm) and TBGA64 (10 x 13mm, 1mm pitch) packages.
In order to meet environmental requirements, ST offers the M29W128FH and the
M29W128FL in ECOPACK ? packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: https://www.wendangku.net/doc/4b2119103.html,.The memories are supplied with all the bits erased (set to ’1’).
The M29W128FH and the M29W128FL will be referred to as M29W128F throughout the document.
Summary description M29W128FH, M29W128FL
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1.Also see Appendix A and Table28 for a full listing of the Block Addresses. Table 1.Signal names
A0-A22Address Inputs
DQ0-DQ7Data Inputs/Outputs
DQ8-DQ14Data Inputs/Outputs
DQ15A?1Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block T emporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
V CC Supply voltage
V PP/WP V PP/Write Protect
V SS Ground
NC Not Connected Internally
M29W128FH, M29W128FL Summary description
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Summary description M29W128FH, M29W128FL
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M29W128FH, M29W128FL Summary description
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Signal descriptions M29W128FH, M29W128FL
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2 Signal descriptions
See Figure 1: Logic diagram , and T able 1: Signal names , for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.
2.2 Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.
2.3 Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation IH IL , these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.
2.4 Data Input/Output or Address Input (DQ15A ?1)
When the device is in x16 Bus mode, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When the device is in x8 Bus mode, this pin behaves as an address pin; DQ15A ?1 Low will select the LSB of the addressed Word, DQ15A ?1 High will select the MSB.
Throughout the text consider references to the Data Input/Output to include this pin when the device operates in x16 bus mode and references to the Address Inputs to include this pin when the device operates in x8 bus mode except when stated explicitly otherwise.
2.5 Chip Enable (E)
to be performed. When Chip Enable is High, V IH , all other pins are ignored.
2.6 The Output Enable pin, G, controls the Bus Read operation of the memory.
M29W128FH, M29W128FL Signal descriptions 2.7
Interface.
2.8 V PP/Write Protect (V PP/WP)
The V PP/Write Protect pin provides two functions. The V PP function allows the memory to
use an external high voltage power supply to reduce the time required for Program
operations. This is achieved by bypassing the unlock cycles and/or using the multiple Word
(2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands.
The Write Protect function provides a hardware method of protecting the highest or lowest
block. When V PP/Write Protect is Low, V IL, the highest or lowest block is protected; Program
and Erase operations on this block are ignored while V PP/Write Protect is Low, even when
RP is at V ID.
When V PP/Write Protect is High, V IH, the memory reverts to the previous protection status
of the highest or lowest block. Program and Erase operations can now modify the data in
this block unless the block is protected using Block Protection.
Applying V PPH to the V PP/WP pin will temporarily unprotect any block previously protected
(including the highest or lowest block) using a High Voltage Block Protection technique (In-
System or Programmer technique). See Table8: Hardware Protection for details.
When V PP/Write Protect is raised to V PP the memory automatically enters the Unlock
Bypass mode. When V PP/Write Protect returns to V IH or V IL normal operation resumes.
During Unlock Bypass Program operations the memory draws I PP from the pin to supply the
programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from V IH to V PP and from V PP to V IH must be slower than
t VHVPP (see Figure15: Accelerated Program Timing waveforms).
Never raise V PP/Write Protect to V PP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
The V PP/Write Protect pin must not be left floating or unconnected or the device may
become unreliable. A 0.1μF capacitor should be connected between the V PP/Write Protect
pin and the V SS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during Unlock Bypass Program,
I PP.
13/78
Signal descriptions M29W128FH, M29W128FL
14/78
2.9 The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique (In-System or Programmer technique). Note that if V PP V IL ID .
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V IL , for at least t PLPX . After Reset/Block Temporary Unprotect goes High, V IH , the memory will be ready for Bus Read and Bus Write operations after t PHEL or t RHEL , whichever occurs last. See Section 2.10: Ready/Busy Output (RB), Table 24: Reset/Block Temporary Unprotect AC characteristics and Figure 13 and Figure 14 for more details.
ID will temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique. Program and erase operations on all blocks will be possible. The transition from V IH to V ID must be slower than t PHPHH .
2.10 The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or erase operation. During Program or erase operations Ready/Busy is Low, V OL . Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 24: Reset/Block Temporary Unprotect AC characteristics and Figure 13 and Figure 14.
The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.
2.11 Byte/Word Organization Select (BYTE)
It is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, V IL , the memory is in x8 mode, when it is High, V IH , the memory is in x16 mode.
2.12 V CC supply voltage (2.7V to
3.6V)
V CC provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, V LKO . This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1μF capacitor should be connected between the V CC Supply Voltage pin and the V SS Ground pin to decouple the current surges from the power supply. The PC
B track widths must be sufficient to carry the currents required during program and erase operations, I cc2.
M29W128FH, M29W128FL Signal descriptions
2.13 V ss ground
V SS is the reference for all voltage measurements. The device features two V SS pins both of
which must be connected to the system ground.
15/78
Bus operations M29W128FH, M29W128FL
16/78
3 Bus operations
There are five standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby. See T able 2 and T able 5, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the memory and do not affect bus operations.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The Page has a size of 8 Words (or 16 Bytes) and is addressed by the address inputs A2-A0 in x16 mode and A2-DQ15A ?1 in Byte mode.
A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL , to Chip Enable and Output Enable and keeping Write Enable High, V IH . The Data Inputs/Outputs will output the value, see Figure 9: Random Read AC waveforms , Figure 10: Page Read AC waveforms (Word mode), and Table 21: Read AC characteristics , for details of when the output becomes valid.
3.2 Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V IH , during the whole Bus Write operation. See Figure 11 and Figure 12, Write AC Waveforms, and Table 22 and Table 23, Write AC Characteristics, for details of the timing requirements.
3.3 Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH .
3.4 Standby
When Chip Enable is High, V IH , the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, I CC2, Chip Enable should be held within V CC ± 0.3V . For the Standby current level see Table 20: DC characteristics .
During program or erase operations the memory will continue to use the Program/Erase Supply Current, I CC3, for Program or Erase operations until the operation completes.
M29W128FH, M29W128FL Bus operations
17/78
3.5 Automatic Standby
If CMOS levels (V CC ± 0.3V) are used to drive the bus and the bus is inactive for t AVQV +
30ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, I CC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.
3.6 Special Bus operations
Additional bus operations can be performed to read the Electronic Signature, verify the Protection Status of the Extended Memory Block, and apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require V ID to be applied to some pins.
3.6.1 Read Electronic Signature
The memory has two codes, the Manufacturer code and the Device code used to identify the memory. These codes can accessed by performing read operations with control signals and addresses set as shown in T able 3 and Table 5.
These codes can also be accessed by issuing an Auto Select command (see Section 5.1.2: Auto Select command ).
3.6.2 Verify Extended Memory Block Protection Indicator
The Extended Memory Block is either Factory Locked or Customer Lockable.
The Protection Status of the Extended Memory Block (Factory Locked or Customer
Lockable) can be accessed by reading the Extended Memory Block Protection Indicator. This is performed by applying the signals as shown in Table 4 and Table 7. The Protection Status of the Extended Memory Block is then output on bit DQ7 of the Data Input/Outputs. (see Table 2 and Table 5, Bus Operations).
The Protection Status of the Extended Memory Block can also be accessed by issuing an Auto Select command (see Section 5.1.2: Auto Select command ).
3.6.3 Verify Block Protection Status
The Protection Status of a Block can be directly accessed by performing a read operation with control signals and addresses set as shown in Table 4 and Table 7.
If the Block is protected, then 01h (in x8 mode) is output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output.
3.6.4 Hardware Block Protect
The V PP /WP pin can be used to protect the highest or lowest block. When V PP /WP is at V IL the highest or lowest block is protected and remains protected regardless of the Block Protection Status or the Reset/Block T emporary Unprotect pin state.
Bus operations M29W128FH, M29W128FL
18/78
3.6.5 Temporary Unprotect of high voltage Protected Blocks
or the Programmer protection technique (High Voltage techniques).Refer to Section 2.9: Reset/Block Temporary Unprotect (RP).
Table 2.
Bus operations, 8-bit mode
Operation (1)
E G W RP V PP /WP Address Inputs
Data Inputs/Outputs A22-A0, DQ15A-1DQ14-DQ8
DQ7-DQ0Bus Read V IL V IL V IH V IH V IH Cell Address Hi-Z Data Output Bus Write
V IL V IH V IL V IH V IH Command Address
Hi-Z Data Input Output Disable X V IH V IH V IH V IH X Hi-Z Hi-Z Standby
V IH
X
X
V IH
V IH
X
Hi-Z
Hi-Z
1.X = V IL or V IH .
Table 3.
Read Electronic Signature, 8-bit mode
Read Cycle (1)E G W
Address Inputs
Data Inputs/Outputs A22-A10A9A8-A7A6A5-A4A3A2A1A0DQ15A-1
DQ14-DQ8DQ7-DQ0Manufacturer Code V IL V IL V IH
X
V ID
X
V IL
X
V IL V IL V IL V IL X Hi-Z
20h
Device Code (Cycle 1)V IL V IL V IL V IH
X
Hi-Z 7Eh (Both Devices)
Device Code (Cycle 2)V IH V IH V IH V IL X Hi-Z 12h (Both Devices)Device Code (Cycle 3)
V IH V IH V IH V IH
X
Hi-Z
8Ah (M29W128FH)8Bh (M29W128FL)
1.X = V IL or V IH .
M29W128FH, M29W128FL Bus operations
19/78
Table 4.
Block Protection, 8-bit mode
Operation
(1)
E
G
W RP
V PP /
WP Address Inputs
Data Inputs/Outputs
A22-A12A11-A10A9A8-A7A6A5-A4A3-A2A1A0
DQ15A-1DQ14-DQ8
DQ7-DQ0Verify
Extended Memory Block
Protection Indicator (bit DQ7)
V IL V IL V IH V IH V IH
BA
X
V ID
X
V IL
X
V IL V IH
V IH
X
Hi-Z
M29W128FH 88h (factory locked)08h (customer lockable)M29W128FL 98h (factory locked) 18h (customer lockable)Verify Block Protection Status V IL
01h (protected)
00h (unprotected)
Temporary Block Unprotect
(2)
X X
X V ID
X Valid Data Input
1.X = V IL or V IH . BA any Address in the Block.
2.The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.
Table 5.Bus operations, 16-bit mode
Operation (1)
E G W RP
V PP /WP Address Inputs
Data Inputs/Outputs A22-A0DQ15A-1, DQ14-DQ0
Bus Read V IL V IL V IH V IH V IH Cell Address Data Output Bus Write V IL V IH
V IL
V IH V IH Command Address
Data Input Output Disable X V IH V IH V IH V IH X Hi-Z Standby
V IH
X
X
V IH
V IH
X
Hi-Z
1.X = V IL or V IH .
Bus operations M29W128FH, M29W128FL
20/78
Table 6.
Read Electronic Signature, 16-bit mode
Read Cycle (1)
E
G
W
Address Inputs
Data Inputs/Outputs A22-A10A9A8-A7
A6
A5-A4
A3A2A1A0DQ15A-1, DQ14-DQ0
Manufacturer Code V IL V IL V IH
X
V ID
X
V IL
X
V IL V IL V IL V IL 0020h Device Code (Cycle 1)V IL
V IL
V IL
V IH
227Eh
(Both Devices)Device Code (Cycle 2)V IH V IH V IH V IL 2212h (Both Devices)Device Code (Cycle 3)
V IH
V IH
V IH
V IH
228Ah (M29W128FH)228Bh (M29W128FL)
1.X = V IL or V IH .
Table 7.Block Protection, 16-bit mode
Operation (1)
E G W RP
V PP /
WP Address Inputs
Data Inputs/Outputs
A22-A12A11-A10A9A8-A7A6A5-A4A3-A2
A1A0
DQ15A-1, DQ14-DQ0Verify
Extended
Memory Block Indicator
(bit DQ7)
V IL V IL V IH V IH V IH BA
X
V ID
X
V IL
X
V IL V IH
V IH
M29W128FH
0088h
(factory locked)
0008h
(customer lockable)M29W128FL 0098h
(factory locked)
0018h
(customer lockable)Verify Block
Protection Status V IL
0001h (protected)0000h (unprotected)
T emporary Block
Unprotect (2)
X
X
X
V ID
X
Valid
Data Input
1.X = V IL or V IH . BA Any Address in the Block.
2.The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.