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EM6617中文资料

EM6617

Ultra Low Power Microcontroller with ADC AND EEPROM

Features

? Low Power - 3.2 μA active mode, ADC off

- 9.0 μA active mode, ADC on - 0.6 μA standby mode - 0.1μA sleep mode @ 3.0V, 32kHz, 25°C

? Voltage range logic incl. EEPROM 2.0 to 5.5 V

? System operating clock : 32 or 128KHz (metal option) ? Voltage range for the ADC is 2.6 to 5.5 V ? 2 clocks per instruction cycle ? 72 basic instructions ? ROM 3k × 16 bit ? RAM 128 × 4 bit ? E 2PROM 64 × 8 bit

? Voltage Level Detector, 3 levels software selectable :2.2, 2.5, 3.0 V

? 2 channel ADC, successive approximation method; conversion time at 32 kHz : 305μs

? Max. 12 inputs (3 ports); port A, port B, port C ? Max. 8 outputs (2 ports); port B, port C ? Serial Write Buffer, 256 bit wide , 4 bit rates ? Oscillation supervisor and timer watchdog ? Universal 10-bit counter, PWM, event counter

? 8 internal interrupt sources (2 × timer , 2 × prescaler, ADC, VLD, FIFO, EEPROM)

? 4 external interrupt sources (input port A ) ?

Frequency output; 32kHz, 2kHz, 1kHz, PWM

Description

The EM6617 is an advanced single chip CMOS 4-bit microcontroller. It contains ROM, RAM, power on reset, watchdog timer, oscillation detection circuit, combined timer , event counter, prescaler, E 2PROM, 2 channel ADC, serial write buffer, voltage level detector and several clock functions. The low voltage feature and low power consumption make it the most suitable controller for battery, stand alone and mobile equipment. The EM6617 is manufactured using EM Microelectronic’s advanced low power (ALP) CMOS Process.

Typical Applications

? Sensor & detector interface ? Heat meter interface ? Security systems

? Household equipment controls ? Automotive controls ? Measurement equipment ? R/F and IR. control ? Voltage control

EM MICROELECTRONIC - MARIN SA

EM6617 EM6617 at a glance

? Power Supply

- Low voltage low power architecture

including internal voltage regulator

- 2.0 ... 5.5 V battery voltage for all logic functions

- 2.6 ... 5.5 V battery voltage for the ADC (0.2LSB)

- 3.2 μA in active mode, ADC off

- 9.0 μA active mode, ADC on

- 0.6μA in standby mode

- 0.1μA in sleep mode

- 32 KHz crystal oscillator

? RAM

- 64 x 4 bit, direct addressable

- 64 x 4 bit, indirect addressable

? ROM

- 3072 x 16 bit metal mask programmable

? E2PROM

- 64 x 8 bit, indirect addressable

- Interrupt request at the end of a write operation ? CPU

- 4 bit RISC architecture

- 2 clock cycles per instruction

- 72 basic instructions

? Main Operating Modes and Resets

- Active Mode (CPU is running)

- Standby Mode (CPU in halt)

- Sleep Mode (No clock, reset state)

- Initial reset on power on (POR)

- Watchdog resets (logic and oscillation watchdogs)

- Reset terminal

- Reset with input combination on port A register

selectable, ¨AND¨ or ¨OR¨ type by metal mask

? 4-Bit Input Port A

- Direct input read on the port terminals

- Debouncer function available on all inputs

- Interrupt request on positive or negative edge

- Pull-up or pull-down or none selectable by register - Test variables (software) for conditional jumps

- PA[0] and PA[3] are inputs for the event counter

- Reset with input combination (register selectable) ? Serial Write Buffer (output)

- Max 256 bits long bit rates of 16kHz,8kHz,2kHz,1kHz - Automatic or interactive send mode

- Interrupt request when buffer is empty ? 2 Channel 8-bit ADC

- Conversion time is 305μs @32kHz

- 2 operating modes (continuous, single)

- Interrupt request at the end of conversion

? Prescaler

- 15 stage system clock divider down to 1 Hz

- 2 Interrupt requests; 1 Hz, 32 Hz or 8 Hz

- Prescaler reset (4 KHz to 1Hz)

? 4-Bit Bi-directional Port B

- All different functions bit-wise selectable

- Direct input read on the port terminals

- Data output latches

- CMOS or Nch. open drain outputs

- Pull-down or pull-up selectable

- Weak pull-up in Nch. open drain mode

- Selectable PWM, 1kHz, 32kHz and 2kHz output ? 4Bit Bi-directional Port C

- Input or output mode as whole port

- Direct input read on port terminal

- Data output latches

- CMOS or Nch. open drain outputs

- Pull-down or pull-up selectable

- Weak pull-up in Nch. open drain mode

? Voltage Level Detector

- 3 levels software selectable (2.0, 2.5, 3.0 V)

- Busy flag during measure

- Interrupt request at end of measure

? 10-Bit Universal Counter

- 10, 8, 6 or 4bit up/down counting

- Parallel load

- 8 different input clocks

- Event counting (PA[0] or PA[3] )

- Full 10 bit or limited (8, 6, 4 bit) compare function

- 2 interrupt requests (on compare and on 0)

- Hi-frequency input on PA[3] and PA[0]

- Pulse-width modulation (PWM) output

? Interrupt Controller

- 4 external and 8 internal interrupt request sources - Each interrupt can individually be maskable

- Each interrupt can individually be reset

- Automatic reset of each interrupt request after read - General interrupt request to CPU can be disabled - Automatic enabling of general interrupt request flag when going into HALT mode

EM6617 Table of Contents

F EATURES 1

D ESCRIPTION _______________________________1 TYPICAL APPLICATIONS _______________________1 EM6617 AT A GLANC

E ________________________2

1. Pin Description for EM6617________________4

2. Typical configurations____________________5

3. Operating Modes________________________6 3.1 Active

Mode________________________6 3.2 Standby

Mode_______________________6 3.3 Sleep

Mode_________________________6

4. Power Supply___________________________7

5. Reset_________________________________8 5.1 Oscillation Detection Circuit____________9 5.2 Reset

Terminal______________________9 5.3 Input Port A Reset Function____________9

5.3.1 AND-Type Reset function__________9

5.3.2 OR -Type Reset function__________10 5.4 Digital Watchdog Timer Reset_________10

5.5 CPU State after Reset_______________11

6. Oscillator and Prescaler__________________12 6.1 Oscillator__________________________12

6.2 Prescaler__________________________12

7. Input and Output ports___________________13 7.1 Ports

overview_____________________13 7.2 Port

A____________________________14

7.2.1 IRQ on Port A__________________14

7.2.2 Pull-up or Pull-down______________15

7.2.3 Software Test Variables___________15

7.2.4 Port A for 10-Bit Counter__________15 7.3 Port A registers_____________________15 7.4 Port

B____________________________17

7.4.1 Input / Output Mode______________17

7.4.2 Pull-up or Pull-down______________18

7.4.3 CMOS or Nch. Output____________18

7.4.4 PWM and Frequency Output_______19 7.5 Port B registers_____________________19 7.6 Port

C____________________________20

7.6.1 Pull-up or Pull-down______________20

7.6.2 CMOS or Nch. Output____________21

7.7 Port C Registers____________________22

8. 10-bit Counter_________________________23 8.1 Full and Limited Bit Counting__________23 8.2 Frequency Select and Up/Down Counting24 8.3 Event

Counting_____________________25 8.4 Compare

Function__________________25 8.5 Pulse Width Modulation (PWM)________25

8.5.1 How the PWM Generator works.____26

8.5.2 PWM

Characteristics_____________26 8.6 Counter

Setup______________________27

8.7 10-bit Counter Registers______________27

9. Serial (Output) Write Buffer - SWB_________29 9.1 SWB Automatic send mode____________29 9.2 SWB Interactive send mode___________31 9.3 SWB

registers______________________32

10. 2-Channel ADC (8-bit digital converter)_____33 10.1 Continuous mode____________________34 10.2 Single mode________________________34

10.3 2-Channel ADC registers______________35

11. EEPROM ( 64 × 8 Bit )_________________36

11.1 EEPROM registers___________________37

12. Supply Voltage Level Detector___________38

12.1 SVLD Register______________________38

13. Interrupt

Controller_____________________39

13.1 Interrupt control registers______________40

14. RAM________________________________41

15. Strobe

Output________________________42

15.1 Strobe register______________________42

16. PERIPHERAL MEMORY MAP___________43

17. Option Register Memory Map____________46

18. Active Supply Current Test______________47

19. Mask

Options_________________________48 19.1 Input / Output Ports__________________48

19.1.1 Port A Metal Options______________48

19.1.2 Port B Metal Options______________49

19.1.3 Port C Metal Options_____________50

19.1.4 SWB high impedance state________51

19.1.5 Debouncer Frequency Option_______51

19.1.6 System Frequency_______________51

19.1.7 Additional mask options___________51

20. Temp. and Voltage Behavior_____________52 20.1 I(VDD) Current______________________52 20.2 IOL, IOH___________________________53 20.3 Pull-up, Pull-down___________________54 20.4 Vreg, EEPROM_____________________54

20.5 ADC8_____________________________55

21. Electrical

Specification__________________57 21.1 Absolute Maximum Ratings____________57 21.2 Handling Procedures_________________57 21.3 Standard Operating Conditions_________57 21.4 DC Characteristics - Power Supply______58 21.5 Oscillator__________________________58 21.6 DC characteristics - I/O Pins___________59 21.7 Supply Voltage Level Detector__________60 21.8 ADC 8 Bit__________________________60

21.9 EEPROM__________________________60

22. Pad Location Diagram__________________61

23. Package & Ordering information__________62 23.1 Ordering Information_________________65 23.2 Package Marking____________________65 23.3 Customer Marking___________________65

EM6617 1. Pin Description for EM6617

PDIP24 SO24

PDIP28

SO28

TSSOP28

Signal Name Function Remarks

17 20 V BAT=V DD Positive power supply Main power pin

MFP programming connection 21 24 V SS Negative power supply Reference terminal, substrate

MFP programming connection 18 21 Vreg Internal voltage regulator connect to minimum 100nF

MFP programming connection

15 18 Test Input test terminal,

internal pull-down 15k

for EM tests only, ground 0 ! Except for MFP programming

14 17 Reset Reset

terminal

internal pull-down 15k

16 19 Strobe Strobe / reset status μC reset state + port B write 19 22 Qin Crystal terminal 1 32kHz crystal

MFP programming connection 20 23 Qout Crystal terminal 2 32kHz crystal

MFP programming connection 10 13 PB[0] Input or output, CMOS or Nch.

open drain; port B terminal 0

Ck[12] output (2 KHz)

11 14 PB[1] Input or output, CMOS or Nch.

open drain; port B terminal 1

Ck[16] output (32 KHz)

12 15 PB[2] Input or output, CMOS or Nch.

open drain; port B terminal 2

Ck[11] output (1 KHz)

13 16 PB[3] Input or output, CMOS or Nch.

open drain; port B terminal 3

PWM output

6 7 PA[0] Input port A terminal 0 TestVar 1,

event counter

7 8 PA[1] Input port A terminal 1 TestVar 2

5 6 PA[2] Input port A terminal 2

8 9 PA[3] Input port A terminal 3 Event counter

4 5 PC[0] Input or output, CMOS or Nch.

open drain; port C terminal 0

9 10 PC[1] Input or output, CMOS or Nch.

open drain; port C terminal 1

- 4 PC[2] Input or output, CMOS or Nch.

open drain; port C terminal 2

Bonded only in 28 pin package

- 12 PC[3] Input or output, CMOS or Nch.

open drain; port C terminal 3

Bonded only in 28 pin package

22 25 Ain channel A for A/D converter

23 26 Bin channel B for A/D converter

24 27 Vref external voltage reference input

FOR the A/D converter Only used for external Vref i.e. Vref not equal to V DD

1 28 Vgnd Virtual analogue ground for A/D

converter

Virtual Ground, usually V DD/2

2 2 Data Serial write buffer data out

3 3 Clk Serial write buffer clock out

Gray shaded area : MFP programming connections (V DD, Vreg, Qin , Qout, Test, Vss).

EM6617

2. Typical configurations

Full range ADC : Vref = V DD , Vgnd = V DD /2.

For power saving one might connect the Vgnd resistor divider chain onto a port B output. This output should be driving V DD during the conversion and driving V SS or high impedance in the ADC off state.

Limited range ADC : V DD > Vref > Vgnd, Vgnd=V DD /2.

For power saving one might connect the Vgnd and the Vref resistor divider chain onto a port B output to V SS . This output should be driving V DD during the conversion and driving Vss or high impedance in the ADC off state.

other possibility: VREF = VregLogic, VGND = VregLogic/2

For power saving one might connect the Vgnd resistor divider chain from VregLogic onto a port B output. This output should be driving V SS during the conversion and driving ‘high impedance’ in the ADC off state.

EM6617

3. Operating Modes

The EM6617 has two low power dissipation modes, standby and sleep. Figure 5 is a transition diagram for these modes.

3.1 Active Mode

The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by the CPU. Leaving active mode via the halt instruction to go into standby mode, the Sleep bit write to go into Sleep mode or a reset from port A to go into reset mode.

3.2 Standby Mode

Executing a halt instruction puts the EM6617 into standby mode. The voltage regulator, oscillator, watchdog timer, ADC, interrupts, SWB, timers and counters are operating.

However, the CPU stops since the clock

related to instruction execution stops.

Registers, RAM and I/O pins retain their

states prior to standby mode. A reset or an

interrupt request if enabled cancels standby. 3.3 Sleep Mode

Writing to the Sleep bit in the RegSysCntl1 register puts the EM6617 in sleep mode. The oscillator stops and most functions of the

EM6617 are inactive. To be able to write to

the Sleep bit, the SleepEn bit in

RegSysCntl2 must first be set to "1". In sleep

mode only the voltage regulator and the reset input are active. The RAM data integrity is maintained. Sleep mode may be canceled only by a high level of min 10μs at the Reset terminal or by the selected port A input reset combination, if option InpResSleep in register OPTFSelPB is turned on.

Due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to guarantee stable oscillation. During sleep mode and the following start up the EM6617 is in reset state. Waking up from sleep clears the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if the EM6617 was powered up (SleepEn = "0") or woken up from sleep (SleepEn = "1").

Table 3.3.1. Internal State in Standby and Sleep Mode

Function Standby Sleep Oscillator Active Stopped Oscillator Watchdog Active Stopped Instruction Execution Stopped Stopped Interrupt Functions Active Stopped Registers and Flags Retained Reset

RAM Data Retained Retained Option Registers Retained Retained Timer & Counter Active Reset Logic Watchdog Active Reset I/O Port B and Serial Port Active High Impedance,

Pull’s as defined in option register

Input Port A Active No pull-downs and inputs deactivated

except if InpResSleep = "1"

LCD Active Stopped (display off) Strobe Output Active Active Buzzer Output Active High Impedance Voltage Level Detector Finishes ongoing measure, then stop Stopped

Reset Pin Active Active

Figure 5. Mode transition diagram Active

Halt instruction Sleep bit

w rite

IRQ Standby Sleep

Reset=1

Reset=0

Reset=1Reset=1Reset

EM6617 4. Power Supply

The EM6617 is supplied by a single external power supply between V DD (Vbat) and V SS (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the oscillator and the internal logic. The output drivers and the ADC are supplied directly from the external supply VDD. A typical power connection configuration and the internal power connection is shown below.

Figure 7. Internal Power Connection

Ref. Logic Term inal Vreg

Term inal

Vbat

All Pad input & output buffers,

ADC, SVLD, EEPRO M Core Logic, O scillator 1kO hm

EM6617

5. Reset

Figure 8. illustrates the reset structure of the EM6617-1. There are six possible reset sources :

(1) Internal initial reset from the Power On Reset (POR) circuitry. --> POR

(2) External reset from the Reset terminal. --> System Reset, Reset CPU

(3) External reset by simultaneous high/low inputs to port A. --> System Reset, Reset CPU

(Combinations are defined in the registers OptInpRSel1 and OptInpRSel2)

(4) Internal reset from the Digital Watchdog. --> System Reset, Reset CPU

(5) Internal reset from the Oscillation Detection Circuit. --> System Reset, Reset CPU

(6) Internal reset when sleep mode is activated. --> System Reset, Reset CPU

All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the system reset remains active long enough for all system functions to be reset (active for n system clock cycles). The ‘CPU Reset Delay’ ensures that the reset CPU remains active until the oscillator is in stable oscillation.

As well as activating the system reset and the reset CPU, the POR also resets all option registers and the sleep enable (SleepEn) latch. System reset and reset CPU do not reset the option registers nor the SleepEn latch. Reset state can be shown on Strobe terminal by selecting StrobeOutSel1,0 = 0 in OPTCandStr register.

EM6617

5.1 Oscillation Detection Circuit

At power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry, and thus the system reset. The CPU of the EM6617 remains in the reset state for the ‘CPU Reset Delay’, to allow the oscillator to stabilize after power up.

The oscillator is disabled during sleep mode. So when waking up from sleep mode, the CPU of the EM6617 remains in the reset state for the CPU Reset Delay, to allow the oscillator to stabilize. During this time, the Oscillation Detection Circuit is inhibited.

In active or standby modes, the oscillator detection circuit monitors the oscillator. If it stops for any reason, a system reset is generated. After clock restart the CPU waits for the CPU Reset Delay before executing the first instructions.

The oscillation detection circuitry can be inhibited with bit NoOscWD = 1 in register RegSysCntl3. At power up, and after any system reset, the function is activated.

The ‘CPU Reset Delay’ is 32768 system clocks ( Ck[16] ) long.

5.2 Reset Terminal

During active or standby modes the Reset terminal has a debouncer to reject noise. Reset must therefore be active for at least 16 ms (system clock = 32 KHz).

When canceling sleep mode, the debouncer is not active (no clock), however, reset passes through an analogue filter with a time constant of typical. 5μs. In this case Reset pin must be high for at least 10 μs to generate a system reset.

5.3 Input Port A Reset Function

By writing the OptInpRSel1 and OptInpRSel2 registers it is possible to choose any combination of port A input values to execute a system reset. The reset condition must be valid for at least 16ms (system clock = 32kHz) in active and standby mode.

OPTInpRSleep selects the input port A reset function in sleep mode. If set to "1" the occurrence of the selected combination for input port A reset will immediately trigger a system reset (no debouncer) .

Reset combination selection (InpReset) is done with registers OptInpRSel1 and OptInpRSel2.

Either an ‘AND’ or an ‘OR’ type port A combination can be chosen to generate the reset.

5.3.1 AND-Type Reset function

Default setting(metal option). One or a combination of port A inputs will trigger a reset. Following formula is applicable :

InpResPA = InpResPA[0] ? InpResPA[1] ? InpResPA[2] ? InpResPA[3]

InpRes1PA[n] InpRes2PA[n]InpResPA[n]

0 0 V SS

0 1 PA[n]

PA[n]

1 0 not

1 1 V DD

n = 0 to 3

i.e. ; - no reset if InpResPA[n] = V SS.

- Don't care function on a single bit with

its InpResPA[n] = V DD.

- Always Reset if InpResPA[3:0] = 'b1111

EM6617

5.3.2 OR -Type Reset function

If wanted, needs to be chosen with the metal 1 option settings. Any one of the port A inputs can trigger a reset. Following formula is applicable :

InpResPA = InpResPA[0] + InpResPA[1] + InpResPA[2] + InpResPA[3]

InpRes1PA[n] InpRes2PA[n]InpResPA[n]

0 0 V SS

0 1 PA[n]

1 0 not

PA[n]

1 1 V DD

n = 0 to 3

i.e. ; - no reset if all InpResPA[n] = V SS.

- Don't care function on a single bit with

its InpResPA[n] = Vss.

- Always Reset if any InpResPA[3:0] = V DD

5.4 Digital Watchdog Timer Reset

The digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by activating an inhibit digital watchdog bit (NoLogicWD) located in RegSysCntl3. At power up, and after any system reset, the watchdog timer is activated.

If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a system reset signal is generated.

The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode for more than 2.5 seconds.

From a system reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. It is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every second. It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’ {WDVal1WDVal0}. When going into the ‘11’ state, the watchdog reset will be active within ? second. The watchdog reset activates the system reset which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always reads ‘0’.

EM6617 Table 5.4.1 Watchdog Timer Register RegSysCntl2

Description

Bit Name Reset

R/W

3 WDReset 0 R/W Reset the Watchdog

1 -> Resets the Logic Watchdog

0 -> No action

The Read value is always '0'

2 SleepEn 0 R/W See Operating modes (sleep)

1 WDVal1 0 R Watchdog timer data Ck[1] divided by 4

0 WDVal0 0 R Watchdog timer data Ck[1] divided by 2

Table 5.4.2 Watchdog Control Register RegSysCntl3

Description

R/W

Bit Name Reset

3 Vref1/2Sel 0 R/W Reference selection for the ADC

2 -- 0 R/W always reads 0

1 NoOscWD 0 R/W No oscillation supervisor

0 NoLogicWD 0 R/W No logic watchdog

5.5 CPU State after Reset

Reset initializes the CPU as shown in Table 5.5.1 below.

Table 5.5.1 Initial CPU Value after Reset.

Value

Symbol Initial Name Bits

Program counter 0 12 PC0 hex 000 (as a result of Jump 0)

Program counter 1 12 PC1 Undefined

Program counter 2 12 PC2 Undefined

Stack pointer 2 SP PSP[0] selected

Index register 7 IX Undefined

Carry flag 1 CY Undefined

Zero flag 1 Z Undefined

Halt 1

HALT 0 Instruction register 16 IR Jump 0

Periphery registers 4 Reg. See peripheral memory map

EM6617 6. Oscillator and Prescaler

6.1 Oscillator

A built-in crystal oscillator generates the system operating clock for the CPU and peripheral blocks, from an externally connected crystal (typically 32.768kHz or 128KHz depending of the metal opt. on table 19.1.6). The oscillator circuit is supplied by the regulated voltage, Vreg. In sleep mode the oscillator is stopped.

EM’s special design techniques guarantee the low current consumption of this oscillator. The external impedance between the oscillator pads must be greater than 10MOhm. Connection of any other components to the two oscillator pads must be confirmed by EM Microelectronic-Marin SA.

6.2 Prescaler

The prescaler consists of fifteen elements divider chain which delivers clock signals for the peripheral circuits such as timer/counter, buzzer, LCD voltage multiplier, debouncer and edge detectors, as well as generating prescaler interrupts. The input to the prescaler is the system clock signal. Power on initializes to Hex(0001).

Table 6.2.1 Prescaler Clock Name Definition

Function Name 32 KHz Xtal Function Name 32 KHz Xtal

System clock Ck[16] 32768 Hz System clock / 256 Ck[8] 128 Hz

System clock / 2 Ck[15] 16384 Hz System clock / 512 Ck[7] 64 Hz

System clock / 4 Ck[14] 8192 Hz System clock / 1024 Ck[6] 32 Hz

System clock / 8 Ck[13] 4096 Hz System clock / 2048 Ck[5] 16 Hz

System clock/ 16 Ck[12] 2048 Hz System clock / 4096 Ck[4] 8 Hz

System clock / 32 Ck[11] 1024 Hz System clock / 8192 Ck[3] 4 Hz

System clock / 64 Ck[10] 512 Hz System clock / 16384 Ck[2] 2 Hz

System clock / 128 ck [9] 256 Hz System clock / 32768 Ck[1] 1 Hz

Table 6.2.2 Control of Prescaler Register RegPresc

Bit Name Reset R/W Description 3

PWMOn 0 R/W see 10 bit counter

2 ResPresc 0 R/W Write Reset prescaler

1 -> Resets the divider chain

from Ck[14] down to

Ck[2], sets Ck[1].

0 -> No action.

The Read value is always '0'

1 PrIntSel 0 R/W Interrupt

select.

0 -> Interrupt from Ck[4]

1 -> Interrupt from Ck[6]

0 DebSel 0 R/W Debouncer clock select.

0 -> Debouncer with Ck[8]

1 -> Debouncer with Ck[11] or

Ck[14]

With DebSel = 1 one may choose either the Ck[11] or Ck[14] debouncer frequency by selecting the corresponding metal mask option. Relative to 32kHz the corresponding max. debouncer times are then 2 ms or 0.25 ms. For the metal mask selection refer to chapter 19.1.4.

Switching the PrIntSel may generate an interrupt request. Avoid it with MaskIRQ32/8 = 0 selection during the switching operation.

The prescaler contains 2 interrupt sources:

- IRQ32/8 ; this is Ck[6] or Ck[4] positive edge interrupt, the selection is depending on bit PrIntSel.

- IRQHz1 ; this is Ck[1] positive edge interrupt

There is no interrupt generation on reset.

The first IRQHz1 Interrupt occurs 1 sec (32kHz) after reset.

EM6617 7. Input and Output ports

The EM6617 has one input port and two bi-directional ports.

7.1 Ports overview

Table 7.1.1 Input and Output Ports Overview

Port Mode Mask(M:) or Register(R:)

Option

Function Bit-wise Multifunction on Ports

PA [3:0] Input M:

Pull-up

M: Pull-down (default)

R: Pull enabling

R: Debouncer or direct

input for IRQ requests

and Counter

R: + or - for IRQ-edge

and counter

R: Input reset

combination

-Input

-Bit-wise interrupt request

-Software test variable

conditional jump

-PA[3],PA[0] input for the

event counter

-Port A reset inputs

PA[3]

10 bit

event

counter

clock

PA[2]

PA[1]

TestVar2

PA[0]

10 bit

event

counter

clock

TestVar1

PB [3:0] Individual

input or

output

R: CMOS or

Nch. open drain output

R: Pull-down on input

R: Pull-up on input

M: Pull-up

M: Pull-down

-Input or output

-PB[3] for the PWM output

-PB[2:0] for the

Ck[11,16,12]

output

-Tristate output

PB[3]

PWM

output

PB[2]

Ck[11]

output

PB[1]

Ck[16]

output

PB[0]

Ck[12]

output

PC [3:0] Port-wise

input /

output

R: CMOS or

Nch. open drain output

R: Pull-down on input

R: Pull-up on input

M: Pull-up

M: Pull-down

-Input or output

-Tristate output

PC[3]

only in

28 pin

package

PC[2]

only in

28 pin

package

PC[1] PC[0]

EM6617

7.2 Port A

The EM6617 has one four bit general purpose CMOS input port. The port A input can be read at any time, internal pull-up or pull-down resistors can be chosen. All selections concerning port A are bit-wise executable. I.e. Pull-up on PA[2], pull-down on PA[0], positive IRQ edge on PA[0] but negative on PA[1], etc.

In sleep mode the port A pull-up or pull-down resistors are turned off, and the inputs are deactivated except if the InpResSleep bit in the option register OPTFSelPB is set to 1. In this case the port A inputs are continuously monitored to match the input reset condition which will immediately wake the EM6617 from sleep mode (all pull resistors remain).

7.2.1 IRQ on Port A

For interrupt request generation (IRQ) one can choose direct or debouncer input and positive or negative edge IRQ triggering. With the debouncer selected ( OPTDebIntPA ) the input must be stable for two rising edges of the selected debouncer clock (RegPresc). This means a worst case of 16 ms (default) or 2 ms (0.25 ms by metal mask) with a system clock of 32 KHz.

Either a positive or a negative edge on the port A inputs - after debouncer or not - can generate an interrupt request. This selection is done in the option register OPTIntEdgPA.

All four bits of port A can provide an IRQ, each pin with its own interrupt mask bit in the RegIRQMask1 register. When an IRQ occurs, inspection of the RegIRQ1, RegIRQ2 and RegIRQ3 registers allows the interrupt to be identified and treated.

At power on or after any reset the RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt is only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt chapter 13.

It is recommended to mask the port A IRQ’s while one changes the selected IRQ edge. Else one may generate a IRQ (Software IRQ). I.e. PA[0] on ‘0’ then changing from positive to negative edge selection on PA[0] will immediately trigger an IRQPA[0] if the IRQ was not masked.

EM6617

7.2.2 Pull-up or Pull-down

Each of the input port terminals PA[3:0] has a resistor integrated which can be used either as pull-up or pull-down resistor, depending on the selected metal mask options. See the port A metal mask chapter for details. The pull resistor can be inhibited using the NoPullPA[n] bits in the register OptNoPullPA. Table 7.2.1. Pull-up or Pull-down Resistor on Port A Inputs

Option mask pull-up MPAPU[n]

Option mask pull-down MPAPD[n]

NoPullPA[n] value

Action

no no x no pull-up, no pull-down no yes 0 no pull-up, pull-down no yes 1 no pull-up, no pull-down yes no 0 pull-up, no pull-down yes no 1 no pull-up , no pull-down

yes

not allowed*

* only pull-up or pull-down may be chosen on any port A terminal (one choice is excluding the other)

7.2.3 Software Test Variables

The port A terminals PA[2:0] are also used as input conditions for conditional software branches. Independent of the OPTDebIntPA and the OPTIntEdgPA. These CPU inputs always have a debouncer.

- Debounced PA[0] is connected to CPU TestVar1. - Debounced PA[1] is connected to CPU TestVar2.

- SWB signal SWBEmpty is connected to CPU TestVar3

7.2.4 Port A for 10-Bit Counter

The PA[0] and PA[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode. As for the IRQ generation one can choose debouncer or direct input with the register OPTDebIntPA and non-inverted or inverted input with the register OPTIntEdgPA . Debouncer input is always recommended.

7.3 Port A registers

Table 7.3.1 Register RegPA

Bit Name Reset R/W Description 3 PAData[3] - R* PA[3] input status 2 PAData[2] - R* PA[2] input status 1 PAData[1] - R* PA[1] input status 0 PAData[0] - R* PA[0] input status

*Direct read on port A terminal

Table 7.3.2 Register RegIRQMask1

Bit Name Reset R/W Description 3 MaskIRQPA[3] 0 R/W Interrupt mask for PA[3] input 2 MaskIRQPA[2] 0 R/W Interrupt mask for PA[2] input 1 MaskIRQPA[1] 0 R/W Interrupt mask for PA[1] input 0 MaskIRQPA[0] 0 R/W Interrupt mask for PA[0] input

Default "0" is: interrupt request masked, no new request stored

with n=0 (3)

EM6617 Table 7.3.3 Register RegIRQ1

R/W Description Bit Name Reset

3 IRQPA[3] 0 R/W* Interrupt request on PA[3]

2 IRQPA[2] 0 R/W* Interrupt request on PA[2]

1 IRQPA[1] 0 R/W* Interrupt request on PA[1]

0 IRQPA[0] 0 R/W* Interrupt request on PA[0]

W*; Write "1" clears the bit, write "0" has no action, Default "0" is: no interrupt request

Table 7.3.4 Register OPTIntEdgPA

Bit Name

R/W Description

power

value

3 IntEdgPA[3] 0 R/W Interrupt edge select for PA[3]

2 IntEdgPA[2] 0 R/W Interrupt edge select for PA[2]

1 IntEdgPA[1] 0 R/W Interrupt edge select for PA[1]

0 IntEdgPA[0] 0 R/W Interrupt edge select for PA[0]

Default "0" is: Positive edge selection

Table 7.3.5 Register OPTDebIntPA

Bit Name

R/W Description

power

value

3 NoDebIntPA[3] 0 R/W Interrupt debounced for PA[3]

2 NoDebIntPA[2] 0 R/W Interrupt debounced for PA[2]

1 NoDebIntPA[1] 0 R/W Interrupt debounced for PA[1]

0 NoDebIntPA[0] 0 R/W Interrupt debounced for PA[0]

Default "0" is: Debounced inputs for interrupt generation

Table 7.3.6 Register OPTNoPullPA

Bit Name

R/W Description

power

value

3 NoPull[3] 0 R/W Pull-up/down selection on PA[3]

2 NoPull[2] 0 R/W Pull-up/down selection on PA[2]

1 NoPull[1] 0 R/W Pull-up/down selection on PA[1]

0 NoPull[0] 0 R/W Pull-up/down selection on PA[0]

Default "0" is: depending on mask selection

EM6617

7.4 Port B

The EM6617 has one four bit general purpose I/O port. Each bit can be configured individually by software for input/output, pull-up, pull-down and CMOS or Nch. open drain output type. The port outputs either data, frequency or PWM signals.

7.4.1 Input / Output Mode

Each port B terminal is bit-wise bi-directional. The input or output mode on each port B terminal is set by writing the corresponding bit in the RegPBCntl control register. To set for input (default), 0 is written to the corresponding bit of the RegPBCntl register which results in a high impedance state for the output driver. The output mode is set by writing 1 in the control register, and consequently the output terminal follows the status of the bits in the RegPBData register.

The port B terminal status can be read on address RegPBData even in output mode. Be aware that the data read on port B is not necessary of the same value as the data stored on RegPBData register.