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HA5351IB中文资料

File Number

3690.7

HA5351

64ns Sample and Hold Ampli?er

The HA5351 is a fast acquisition, wide bandwidth sample and hold ampli?er, built with the Intersil HBC-10 BiCMOS process.This sample and hold ampli?er offers a combination of desirable features; fast acquisition time (70ns to 0.01%maximum),excellent DC precision and extremely low power dissipation, making it ideal for use in systems that sample multiple signals and require low power.

The HA5351 is in an open loop con?guration with fully differential inputs providing ?exibility for user de?ned feedback. In unity gain the HA5351 is completely self-contained and requires no external components. The on-chip 15pF hold capacitor is completely isolated to minimizing droop rate and reduce sensitivity to pedestal error. The HA5351 is available in 8 lead PDIP and SOIC packages for minimizing board space and ease of layout.

Functional Diagram

Features

?Fast Acquisition to 0.01%. . . . . . . . . . . . . . . . .70ns (Max)?Low Offset Error. . . . . . . . . . . . . . . . . . . . . . .±2mV (Max)?Low Pedestal Error. . . . . . . . . . . . . . . . . . . .±10mV (Max)?Low Droop Rate . . . . . . . . . . . . . . . . . . . . . .2μV/μs (Max)?Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . .40MHz ?Low Power Dissipation . . . . . . . . . . . . . . .220mW (Max)?Total Harmonic Distortion (Hold Mode) . . . . . . . . .-72dBc -(V IN = 5V P-P at 1MHz)?Fully Differential Inputs ?On Chip Hold Capacitor

Applications

?Synchronous Sampling

?Wide Bandwidth A/D Conversion ?Deglitching ?Peak Detection ?High Speed DC Restore

Pinout

HA5351(PDIP , SOIC)TOP VIEW)

Ordering Information

PART NUMBER

(BRAND)TEMP.RANGE (o C)PACKAGE PKG.NO.HA5351IP -40 to 858 Ld PDIP E8.3HA5351IB (H5351)

-40 to 85

8 Ld SOIC

M8.15

HA5351

G M BUFFER

A V

-IN

+IN

S/H

OUT

15pF

V+V-7GND

--+

+IN NC

V-OUT

1234

8765

-IN GND V+S/H CTRL

Data Sheet

May 1999

元器件交易网https://www.wendangku.net/doc/445845112.html,

Absolute Maximum Ratings Thermal Information

Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . .+11V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Voltage Between Sample and Hold Control and Ground. . . . .+5.5V Output Current, Continuous. . . . . . . . . . . . . . . . . . . . . . . . . .±37mA Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40o C to 85o C Thermal Resistance (T ypical, Note 1)θJA (o C/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Maximum Junction T emperature (Plastic Package) . . . . . . . .150o C Maximum Storage Temperature Range. . . . . . . . . . -65o C to 150o C Maximum Lead T emperature (Soldering 10s) . . . . . . . . . . . . 300o C (SOIC - Lead Tips Only)

CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied.

NOTE:

1.θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Speci?cations Test Conditions: V SUPPL Y = ±5V; C H = Internal = 15pF, Digital Input: V IL = fc0V (Sample), V IH = 4.0V (Hold).

Non-Inverting Unity Gain Con?guration (Output Tied to -Input), C L = 5pF,

Unless Otherwise Speci?ed

PARAMETER TEST CONDITIONS TEMP.

(o C)

HA5351I

UNITS MIN TYP MAX

INPUT CHARACTERISTICS

Input Voltage Range Full-2.5-+2.5V Input Resistance (Note 2)25100500-k?Input Capacitance25--5pF Input Offset Voltage25-2-2mV

Full-3.0- 3.0mV Offset Voltage Temperature Coefficient Full-15-μV/o C Bias Current Full- 2.55μA Offset Current Full-1.5-+1.5μA Common Mode Range Full-2.5-+2.5V Common Mode Rejection Ratio±2.5V, Note 3Full6080-dB TRANSFER CHARACTERISTICS

Large Signal Voltage Gain V OUT =±2.5V2595108-dB

Full85--dB Unity Gain -3dB Bandwidth25-40-MHz TRANSIENT RESPONSE

Rise Time200mV Step25-8.5-ns Overshoot200mV Step250-30% Slew Rate5V Step Full88105-V/μs DIGITAL INPUT CHARACTERISTICS

Input Voltage V IH25, 85 2.1- 5.0V

-40 2.4- 5.0V

V IL Full0-0.8V Input Current V IL = 0V Full-1.0- 1.0μA

V IH = 5V Full-1.0- 1.0μA OUTPUT CHARACTERISTICS

Output Voltage R L = 510?Full-3.0-+3.0V Output Current R L = 100?25, 852025-mA

-4015--mA

Full Power Bandwidth 5V P-P , A V = +1, -3dB Full -13-MHz Output Resistance Hold Mode 25-0.02-?Total Output Noise (DC to 10MHz)

Sample Mode 25-325-μV RMS Hold Mode

-325

-μV RMS

DISTORTION CHARACTERISTICS SAMPLE MODE Total Harmonic Distortion

V IN = 4.5V P-P , f IN = 100kHz 25--80-dBc V IN = 5V P-P , f IN = 1MHz 25--74-dBc V IN = 1V P-P , f IN = 10MHz

25--57-dBc Signal to Noise Ratio

(RMS Signal to RMS Noise)V IN = 4.5V P-P , f IN = 100kHz

HOLD MODE (50% Duty Cycle S/H)Total Harmonic Distortion

V IN = 4.5V P-P , f IN = 100kHz,f S ? 100kHz

25--78-dBc V IN = 5V P-P , f IN = 1MHz,f S ? 1MHz

25--72-dBc V IN = 1V P-P , f IN = 10MHz,f S ? 1MHz

25--51-dBc Signal to Noise Ratio

(RMS Signal to RMS Noise)

V IN = 4.5V P-P , f IN = 100kHz,f S ? 100kHz

SAMPLE AND HOLD CHARACTERISTICS Acquisition Time

0V to 2.0V Step to ±1mV 25-53-ns 0V to 2.0V Step to 0.01%(±200μV)

25-6470ns -2.5V to +2.5V Step to 0.01%(±500μV)

25-90100ns Droop Rate

25-0.3-μV/μs Full

-2-2μV/μs Hold Step Error

V IL = 0V, V IH = 4.0V, t R = 5ns Full -10-+10mV Hold Mode Settling Time To ±1mV

25-50-ns Hold Mode Feedthrough

5V P-P , 500kHz, Sine

25-72-dB EADT (Effective Aperture Delay Time)25-+1-ns Aperture Time (Note 2)25-10-ns Aperture Uncertainty

POWER SUPPLY CHARACTERISTICS Positive Supply Current Full -2022mA Negative Supply Current Full

-2022mA PSRR 10% Delta

Full

NOTES:

2.Derived from Computer Simulation only, not tested.

3.+CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V.

Electrical Speci?cations

Test Conditions: V SUPPL Y = ±5V; C H = Internal = 15pF , Digital Input: V IL = fc0V (Sample), V IH = 4.0V (Hold).Non-Inverting Unity Gain Con?guration (Output Tied to -Input), C L = 5pF ,Unless Otherwise Speci?ed (Continued)

PARAMETER

TEST CONDITIONS

TEMP.(o C)HA5351I

UNITS MIN TYP MAX

Typical Performance Curves

FIGURE https://www.wendangku.net/doc/445845112.html,RGE SIGNAL RESPONSE FIGURE 2.SMALL SIGNAL RESPONSE

FIGURE 3.UNITY GAIN FREQUENCY RESPONSE

FIGURE 4.CLOSED LOOP GAIN/PHASE A V = +1000

FIGURE 5.5V P-P FULL POWER FREQUENCY RESPONSE

FIGURE 6.-3dB BANDWIDTH vs SUPPL Y VOLTAGE

20-20

100

200300400

500

TIME (ns)

O U T P U T (V )

0.1

0.0

-0.1

200

400

600

TIME (ns)

O U T P U T (V )

100K

10M

100M

-2

-4

-6

-8FREQUENCY (Hz)G A I N (d B )

40.163156MHz

-3dB

10K

100K

10M

100M

FREQUENCY (Hz)

-20

0-30-60

-90-120-150-180P H A S E (D E G R E E S )G A I N (d B )

0dB AT 21.34MHz

GAIN

PHASE -119.86 DEG 10K

100K 1M

10M 100M

-2

-4

-6

-8FREQUENCY (Hz)

G A I N (d B )

13.241189MHz

-3dB

±3.5

±4

±4.5±5±5.5

±6

010********

SUPPLY VOLTAGE (V)

-3d B B A N D W I D T H (M H z )

4 TYPICAL UNITS

200mV P-P

FIGURE 7.DROOP RATE vs TEMPERATURE FIGURE 8.SLEW RATE vs TEMPERATURE

FIGURE 9.RISE TIME vs TEMPERATURE FIGURE 10.HOLD MODE SETTLING vs TEMPERATURE

FIGURE 11.PEDESTAL vs S/H CONTROL RISE TIME FIGURE 12.ACQUISITION TIME (0.01%, 0V TO 2V STEP)

-50

050

100

00.1

0.2

0.3

0.40.5

TEMPERATURE (o C)

D R O O P R A T

E (μV /μs )

3 TYPICAL UNITS

-50

050

100

8090

100110120130140

150

160

TEMPERATURE (o C)

S L E W R A T E (V /μs )

UNIT #2

UNIT #3

UNIT #1

3 TYPICAL UNITS

-SLEW RATE

+SLEW RATE -50

050100

TEMPERATURE (o C)

R I S E T I M E (n s )

4 TYPICAL UNITS

-50

050100

35404550556065

TEMPERATURE (o C)

H O L D M O D E S E T T L I N G T I M E (n s )

4 TYPICAL UNITS 0

-2

-1

S/H CONTROL RISE TIME (ns)

P E D E S T A L E R R O R (m V )

0V TO 4V S/H CTRL

0.01

0.00

-0.01

3.0E-7

TIME (ns)

O U T P U T (V )

S /H C O N T R O L (V )67.25ns

OUTPUT

S/H

CONTROL

Die Characteristics

DIE DIMENSIONS:

2530μm x 1760μm x 525μm 100 mils x 69 mils x 19 mils METALLIZATION:

Type: Metal 1: AlSiCu/TiW

Thickness: Metal 1: 6k ?±750?Type: Metal 2: AlSiCu

Thickness: Metal 2: 16k ?±1.1k ?

PASSIVATION:

T ype: Sandwich Passivation

Nitride - 4k ?, Undoped Si Glass (USG) - 8k ?,T otal - 12k ?±2k ?SUBSTRATE POTENTIAL:V-TRANSISTOR COUNT:

156

Metallization Mask Layout

HA5351

FIGURE 13.HOLD MODE SETTLING TIME (±200μV)

0.02

0.00

-0.02

-0.04

4060

TIME (ns)

51.4 ns

O U T P U T (V )

S /H C O N T R O L (V )

OUTPUT

+IN

-IN

V-V-V-

V OUT

S/H CONTROL

V+

GND

C L E

e A C e B e C

-B-E1

INDEX 123

N/2

AREA

SEATING BASE PLANE PLANE

-C-D1B1

L A 1

-A-0.010 (0.25)C A M

B S

NOTES:

1.Controlling Dimensions:INCH.In case of conflict between English and Metric dimensions, the inch dimensions control.

2.Dimensioning and tolerancing per ANSI Y14.5M -1982.

3.Symbols are defined in the “MO Series Symbol List”in Section 2.2 of Publication No. 95.

4.Dimensions A,A1and L are measured with the package seated in JEDEC seating plane gauge GS -3.

5.D, D1, and E1 dimensions do not include mold flash or protru-sions.Mold flash or protrusions shall not exceed 0.010inch (0.25mm).

6.E and are measured with the leads constrained to be per-pendicular to datum .

7.e B and e C are measured at the lead tips with the leads uncon-strained. e C must be zero or greater.

8.B1maximum dimensions do not include dambar protrusions.Dambar protrusions shall not exceed 0.010 inch (0.25mm).9.N is the maximum number of terminal positions.

10.Corner leads (1,N,N/2and N/2+1)for E8.3,E16.3,E18.3,

E28.3,E42.6will have a B1dimension of 0.030-0.045inch (0.76 - 1.14mm).

e A -C-E8.3(JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS NOTES MIN MAX MIN MAX A -0.210- 5.334A10.015-0.39-4A20.1150.195 2.93 4.95-B 0.0140.0220.3560.558-B10.0450.070 1.15 1.778, 10C 0.0080.0140.2040.355-D 0.3550.4009.0110.165D10.005-0.13-5E 0.3000.3257.628.256E10.240

0.280

6.10

7.11

5e 0.100 BSC 2.54 BSC -e A 0.300 BSC 7.62 BSC

6e B -0.430-

10.927L 0.115

0.150

2.93

3.814N

Rev. 0 12/93

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certi?cation.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-out notice.Accordingly,the reader is cautioned to verify that data sheets are current before placing https://www.wendangku.net/doc/445845112.html,rmation furnished by Intersil is believed to be accurate and reliable.However,no responsibility is assumed by Intersil or its subsidiaries for its use;nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products,see web site https://www.wendangku.net/doc/445845112.html,

Sales Of?ce Headquarters

NORTH AMERICA Intersil Corporation

P. O. Box 883, Mail Stop 53-204Melbourne, FL 32902TEL:(321) 724-7000FAX: (321) 724-7240

EUROPE Intersil SA

Mercure Center

100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111FAX: (32) 2.724.22.05

ASIA

Intersil (Taiwan) Ltd.

7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China

TEL: (886) 2 2716 9310FAX: (886) 2 2715 3029

INDEX AREA

E D

-B-0.25(0.010)C A M

B S

-A-L

-C-A1

SEATING PLANE

0.10(0.004)

h x 45o

0.25(0.010)B M

NOTES:

1.Symbols are defined in the “MO Series Symbol List”in Section

2.2of Publication Number 95.

2.Dimensioning and tolerancing per ANSI Y14.5M -1982.

3.Dimension “D”does not include mold flash,protrusions or gate burrs.Mold flash,protrusion and gate burrs shall not exceed 0.15mm (0.006inch) per side.

4.Dimension “E” does not include interlead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.25mm (0.010inch)per side.

5.The chamfer on the body is optional.If it is not present,a visual index feature must be located within the crosshatched area.

6.“L” is the length of terminal for soldering to a substrate.

7.“N” is the number of terminal positions.

8.Terminal numbers are shown for reference only.

9.The lead width “B”,as measured 0.36mm (0.014inch)or greater above the seating plane,shall not exceed a maximum value of 0.61mm (0.024 inch).

10.Controlling dimension:MILLIMETER.Converted inch dimensions

are not necessarily exact.

M8.15(JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS NOTES

MIN MAX MIN MAX A

0.05320.0688 1.35 1.75-A10.00400.00980.100.25-B 0.0130.0200.330.519C 0.00750.00980.190.25-D 0.18900.1968 4.80 5.003E 0.14970.1574 3.80 4.004e

0.050 BSC 1.27 BSC

-H 0.22840.2440 5.80 6.20-h 0.00990.01960.250.505L 0.016

0.0500.40

1.276N

887α

-Rev. 0 12/93