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ADA4857-2YCPZ-R7中文资料

Ultralow Distortion, Low Power,

Low Noise, High Speed Op Amp

ADA4857-1/ADA4857-2 Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 https://www.wendangku.net/doc/4d7102139.html, Fax: 781.461.3113 ?2008 Analog Devices, Inc. All rights reserved.

FEATURES

High speed

850 MHz, ?3 dB bandwidth (G = +1, R L = 1 kΩ, LFCSP) 750 MHz, ?3 dB bandwidth (G = +1, R L = 1 kΩ, SOIC) 2800 V/μs slew rate

Low distortion: ?88 dBc @ 10 MHz (G = +1, R L = 1 kΩ)

Low power: 5 mA/amplifier @ 10 V

Low noise: 4.4 nV/√Hz

Wide supply voltage range: 5 V to 10 V

Power-down feature

Available in 3 mm × 3 mm 8-lead LFCSP (single), 8-lead SOIC (single), and 4 mm × 4 mm 16-lead LFCSP (dual)

APPLICATIONS

Instrumentation

IF and baseband amplifiers

Active filters

ADC drivers

DAC buffers CONNECTION DIAGRAMS NC = NO CONNECT

–IN

+IN

7OUT

8+V S

6NC

5–V

ADA4857-1

TOP VIEW

1 Figure 1. 8-Lead LFCSP (CP)

–IN

+IN

–V S

+V S

OUT

NC = NO CONNECT

ADA4857-1

TOP VIEW

Figure 2. 8-Lead SOIC (R)

–IN1

+IN1

–V S2

11NC

12–V S1

10+IN2

9–IN2

ADA4857-2

TOP VIEW

(Not to Scale)

NC = NO CONNECT

3 Figure 3. 16-Lead LFCSP (CP)

GENERAL DESCRIPTION

The ADA4857 is a unity-gain stable, high speed, voltage feedback amplifier with low distortion, low noise, and high slew rate. With a spurious-free dynamic range (SFDR) of ?88 dBc @ 10 MHz, the ADA4857 is an ideal solution for a variety of applications, including ultrasounds, ATE, active filters, and ADC drivers. The Analog Devices, Inc., proprietary next-generation XFCB process and innovative architecture enables such high performance amplifiers. The ADA4857 has 850 MHz bandwidth, 2800 V/μs slew rate, and settles to 0.1% in 15 ns. With a wide supply voltage range (5 V to 10 V), the ADA4857 is an ideal candidate for systems that require high dynamic range, precision, and speed.

The ADA4857-1 amplifier is available in a 3 mm × 3 mm, 8-lead LFCSP and a standard 8-lead SOIC. The ADA4857-2 is available in a 4 mm × 4 mm, 16-lead LFCSP. The LFCSP features an exposed paddle that provides a low thermal resistance path to the printed circuit board (PCB). This path enables more efficient heat transfer and increases reliability. The ADA4857 works over the extended industrial temperature range (?40°C to +125°C).

ADA4857-1/ADA4857-2

Rev. A | Page 2 of 20

TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 Connection Diagrams ...................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 ±5 V Supply ................................................................................... 3 +5 V Supply ................................................................................... 4 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 Maximum Power Dissipation ..................................................... 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 9 Test Circuits ..................................................................................... 15 Applications Information .............................................................. 16 Power-Down Operation ............................................................ 16 Capacitive Load Considerations .............................................. 16 Recommended Values for Various Gains ................................ 16 Active Low-Pass Filter (LPF) .................................................... 17 Noise ............................................................................................ 18 Circuit Considerations .............................................................. 18 PCB Layout ................................................................................. 18 Power Supply Bypassing ............................................................ 18 Grounding ................................................................................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .. (20)

REVISION HISTORY

11/08—Rev. 0 to Rev. A

Changes to Table 5 ............................................................................ 7 Changes to Table 7 ............................................................................ 8 Changes to Figure 32 ...................................................................... 13 Added Figure 44; Renumbered Sequentially .............................. 15 Changes to Layout .......................................................................... 15 Changes to Table 8 .......................................................................... 16 Added Active Low-Pass Filter (LFP) Section .............................. 17 Added Figure 48 and Figure 49; Renumbered Sequentially ..... 17 Changes to Grounding Section ..................................................... 18 Exposed Paddle Notation Added to Outline Dimensions ........ 19 Changes to Ordering Guide . (20)

5/08—Revision 0: Initial Version

ADA4857-1/ADA4857-2

Rev. A | Page 3 of 20

SPECIFICATIONS

±5 V SUPPLY

T A = 25°C, G = +2, R G = R F = 499 Ω, R L = 1 kΩ to ground, PD = no connect, unless otherwise noted. Table 1.

Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth (LFCSP/SOIC) G = +1, V OUT = 0.2 V p-p 650 850/750 MHz G = +1, V OUT = 2 V p-p 600/550 MHz G = +2, V OUT = 0.2 V p-p 400/350 MHz Full Power Bandwidth G = +1, V OUT = 2 V p-p, THD < ?40 dBc 110 MHz Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) G = +2, V OUT = 2 V p-p, R L = 150 Ω 75/90 MHz Slew Rate (10% to 90%) G = +1, V OUT = 4 V step 2800 V/μs Settling Time to 0.1% G = +2, V OUT = 2 V step 15 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion f = 1 MHz, G = +1, V OUT = 2 V p-p (HD2) ?108 dBc f = 1 MHz, G = +1, V OUT = 2 V p-p (HD3) ?108 dBc f = 10 MHz, G = +1, V OUT = 2 V p-p (HD2) ?88 dBc f = 10 MHz, G = +1, V OUT = 2 V p-p (HD3) ?93 dBc f = 50 MHz, G = +1, V OUT = 2 V p-p (HD2) ?65 dBc f = 50 MHz, G = +1, V OUT = 2 V p-p (HD3) ?62 dBc Input Voltage Noise f = 100 kHz 4.4 nV/√Hz Input Current Noise f = 100 kHz 1.5 pA/√Hz DC PERFORMANCE Input Offset Voltage ±2 ±4.5 mV Input Offset Voltage Drift 2.3 μV/°C

Input Bias Current

?2 ?3.3 μA Input Bias Current Drift 24.5 nA/°C Input Bias Offset Current 50 nA Open-Loop Gain V OUT = ?2.5 V to +2.5 V 57 dB PD (POWER-DOWN) PIN PD Input Voltage Chip powered down ≥(V CC ? 2) V Chip enabled ≤(V CC ? 4.2) V Turn-Off Time 50% off PD to <10% of final V OUT , V IN = 1 V, G = +2 55 μs Turn-On Time 50% off PD to <10% of final V OUT , V IN = 1 V, G = +2 33 ns PD Pin Leakage Current Chip enabled 58 μA Chip powered down 80 μA INPUT CHARACTERISTICS Input Resistance Common mode 8 MΩ Differential mode 4 MΩ Input Capacitance Common mode 2 pF Input Common-Mode Voltage Range ±4 V Common-Mode Rejection Ratio V CM = ±1 V ?78 ?86 dB OUTPUT CHARACTERISTICS Output Overdrive Recovery Time V IN = ±2.5 V, G = +2 10 ns Output Voltage Swing R L = 1 kΩ ±4 V R L = 100 Ω ±3.7 V Output Current 50 mA Short-Circuit Current Sinking and sourcing 125 mA Capacitive Load Drive 30% overshoot, G = +2 10 pF

ADA4857-1/ADA4857-2

Rev. A | Page 4 of 20

Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range 4.5 10.5 V Quiescent Current

5 5.5 mA Quiescent Current (Power Down) PD ≥ V CC ? 2 V

350 450 μA Positive Power Supply Rejection +V S = 4.5 V to 5.5 V, ?V S = ?5 V ?59 ?62 dB Negative Power Supply Rejection

+V S = 5 V, ?V S = ?4.5 V to ?5.5 V

?65

?68

+5 V SUPPLY

T A = 25°C, G = +2, R F = R G = 499 Ω, R L = 1 kΩ to midsupply, PD = no connect, unless otherwise noted. Table 2.

Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth (LFCSP/SOIC) G = +1, V OUT = 0.2 V p-p 595 800/750 MHz G = +1, V OUT = 2 V p-p 500/400 MHz G = +2, V OUT = 0.2 V p-p 360/300 MHz Full Power Bandwidth G = +1, V OUT = 2 V p-p, THD < ?40 dBc 95 MHz Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) G = +2, V OUT = 2 V p-p, R L = 150 Ω 50/40 MHz Slew Rate (10% to 90%) G = +1, V OUT = 2 V step 1500 V/μs Settling Time to 0.1% G = +2, V OUT = 2 V step 15 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion f = 1 MHz, G = +1, V OUT = 2 V p-p (HD2) ?92 dBc f = 1 MHz, G = +1, V OUT = 2 V p-p (HD3) ?90 dBc f = 10 MHz, G = +1, V OUT = 2 V p-p (HD2) ?81 dBc f = 10 MHz, G = +1, V OUT = 2 V p-p (HD3) ?71 dBc f = 50 MHz, G = +1, V OUT = 2 V p-p (HD2) ?69 dBc f = 50 MHz, G = +1, V OUT = 2 V p-p (HD3) ?55 dBc Input Voltage Noise f = 100 kHz 4.4 nV/√Hz Input Current Noise f = 100 kHz 1.5 pA/√Hz DC PERFORMANCE Input Offset Voltage ±1 ±4.2 mV Input Offset Voltage Drift 4.6 μV/°C

Input Bias Current

?1.7 ?3.3 μA Input Bias Current Drift 24.5 nA/°C Input Bias Offset Current 50 nA Open-Loop Gain V OUT = 1.25 V to 3.75 V 57 dB PD (POWER-DOWN) PIN PD Input Voltage Chip powered down ≥(V CC ? 2) V Chip enabled ≤(V CC ? 4.2) V Turn-Off Time 50% off PD to <10% of final V OUT , V IN = 1 V, G = +2 38 μs Turn-On Time 50% off PD to <10% of final V OUT , V IN = 1 V, G = +2 30 ns PD Pin Leakage Current Chip enable 8 μA Chip powered down 30 μA INPUT CHARACTERISTICS Input Resistance Common mode 8 MΩ Differential mode 4 MΩ Input Capacitance Common mode 2 pF Input Common-Mode Voltage Range 1 to 4 V Common-Mode Rejection Ratio V CM = 2 V to 3 V ?76 ?84 dB

ADA4857-1/ADA4857-2

Rev. A | Page 5 of 20

Parameter Conditions Min Typ Max Unit

OUTPUT CHARACTERISTICS Overdrive Recovery Time G = +2 15 ns Output Voltage Swing R L = 1 kΩ 1 to 4 V R L = 100 Ω 1.1 to 3.9 V Output Current 50 mA Short-Circuit Current Sinking and sourcing 75 mA Capacitive Load Drive 30% overshoot, G = +2 10 pF POWER SUPPLY Operating Range 4.5 10.5 V Quiescent Current 4.5 5 mA Quiescent Current (Power Down) PD ≥ V CC ? 2 V 250 350 μA Positive Power Supply Rejection +V S = 4.5 V to 5.5 V, ?V S = 0 V ?58 ?62 dB Negative Power Supply Rejection +V S = 5 V, ?V S = ?0.5 V to +0.5 V ?65 ?68 dB

ADA4857-1/ADA4857-2

Rev. A | Page 6 of 20

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 11 V

Power Dissipation See Figure 4

Common-Mode Input Voltage ?V S + 0.7 V to +V S ? 0.7 V Differential Input Voltage ±V S Exposed Paddle Voltage ?V S

Storage Temperature Range ?65°C to +125°C Operating Temperature Range

?40°C to +125°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature

150°C

The power dissipated in the package (P D ) is the sum of the quiescent power dissipation and the power dissipated in the

die due to the ADA4857 drive at the output. The quiescent

power is the voltage between the supply pins (V S ) times the

quiescent current (I S ). P D = Quiescent Power + (Total Drive Power ? Load Power )

()L OUT L OUT

S S S D R V R

V V I V P 2

–2???

?????×+×= RMS output voltages should be considered. If R L is referenced to ?V S , as in single-supply operation, the total drive power is V S × I OUT . If the rms signal levels are indeterminate, consider the worst case, when V OUT = V S /4 for R L to midsupply.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

()()L

S S

S D R V I V P 24/+

×=

In single-supply operation with R L referenced to ?V S , the worst case is V OUT = V S /2.

Airflow increases heat dissipation, effectively reducing θJA . In addition, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduces θJA .

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. Figure 4 shows the maximum power dissipation in the package vs. the ambient temperature for the SOIC and LFCSP packages on a JEDEC standard 4-layer board. θJA values are approximations.

Table 4.

Package Type θJA θJC Unit 8-Lead SOIC 115 15 °C/W 8-Lead LFCSP 94.5 34.8 °C/W 16-Lead LFCSP

68.2

19 °C/W

0.5

1.0

1.5

2.0

2.5

3.0

07040-004

AMBIENT TEMPERATURE (°C)

M A X I M U M P O W E R D I S S I P A T I O N (W )

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation for the ADA4857 is

limited by the associated rise in junction temperature (T J ) on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4857. Exceeding a junction temperature of 175°C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality.

Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

ADA4857-1/ADA4857-2

Rev. A | Page 7 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

1PD 2FB 3–IN 4

+IN 7OUT 8+V S 6NC 5–V S

ADA4857-1

07040-005

TOP VIEW (Not to Scale)

Figure 5. 8-Lead LFCSP Pin Configuration

FB 1

–IN 2

+IN 3–V S 4PD

+V S

7OUT 6NC

5NC = NO CONNECT

ADA4857-1

07040-006

TOP VIEW

(Not to Scale)

Figure 6. 8-Lead SOIC Pin Configuration

Table 5. 8-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic Description

1 PD Power Down.

2 FB Feedback.

3 ?IN Inverting Input.

4 +IN Noninverting Input.

5 ?V S Negative Supply.

6 NC No Connect.

7 OUT Output.

8 +V S Positive Supply. EP GND or V S Exposed Pad. The exposed pad

may be connected to GND or V S .

Table 6. 8-Lead SOIC Pin Function Descriptions

Pin No. Mnemonic Description 1 FB Feedback 2 ?IN Inverting Input 3 +IN Noninverting Input 4 ?V S Negative Supply 5 NC No Connect 6 OUT Output 7 +V S Positive Supply 8 PD Power Down

ADA4857-1/ADA4857-2

Rev. A | Page 8 of 20

1–IN12+IN13NC 4

–V S211NC 12–V S110+IN29–IN2

O U T 26

+V S 27

P D 28

F B 2F B 1

P D 1+V S 1

O U T 1

15161413ADA4857-2

TOP VIEW (Not to Scale)

NC = NO CONNECT

07040-007

Figure 7. 16-Lead LFCSP Pin Configuration

Table 7. 16-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic

Description

1 ?IN1 Inverting Input 1.

2 +IN1 Noninverting Input 1. 3, 11 NC No Connect.

4 ?V S2

Negative Supply 2.

5 OUT2 Output 2.

6 +V S2 Positive Supply 2.

7 PD2

Power Down 2.

8 FB2 Feedback 2. 9 ?IN2 Inverting Input 2. 10 +IN2 Noninverting Input 2. 12 ?V S1

Negative Supply 1.

13 OUT1 Output 1. 14 +V S1 Positive Supply 1. 15 PD1

Power Down 1.

16 FB1 Feedback 1.

EP GND or Vs

Exposed Pad. The exposed pad may be connected to GND or V S .

ADA4857-1/ADA4857-2

Rev. A | Page 9 of 20

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C (G = +1, R F = 0 Ω, and, R G open; G = +2, and R F = R G = 499 Ω), unless otherwise noted.

–10

–9–8–7–6–5–4–3–2–101231

100

1000

07040-008

FREQUENCY (MHz)

N O R M A L I Z E D C L O S E D -L O O P G A I N (d B )

Figure 8. Small Signal Frequency Responses for Various Gains (LFCSP)

–10

–9–8–7–6–5–4–3–2–10123

07040-009

FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

Figure 9. Small Signal Frequency Response for Various Supply Voltages (LFCSP)

–10

–9–8–7

–6–5–4–3–2–101

2307040-010

FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP)

–10

–9–8–7–6–5–4–3–2–10123

07040-011FREQUENCY (MHz)

N O R M A L I Z E D C L O S E D -L O O P G A I N (d B )

Figure 11. Large Signal Frequency Responses for Various Gains (LFCSP)

07040-012

FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

–7–6–5–4–3–2–10123456789Figure 12. Small Signal Frequency Response for Various Capacitive Loads (LFCSP)

–10

–9

–8–7–6–5–4–3–2–101

2307040-013FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

Figure 13. Large Signal Frequency Response vs. V OUT (LFCSP)

ADA4857-1/ADA4857-2

Rev. A | Page 10 of 20

07040-014

FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

–7–6–5–4–3–2–10123456789Figure 14. Small Signal Frequency Response for Various Resistive Loads (LFCSP)

–10

–9–8–7–6–5–4–3–2–10123

07040-015

FREQUENCY (MHz)

N O R M A L I Z E D C L O S E D -L O O P G A I N (d B )

Figure 15. Small Signal Frequency Response for Various Gains (LFCSP)

–120

–110

–100–90–80

–70–60–50–400.2

110

100

07040-016

FREQUENCY (MHz)

D I S T O R T I O N (d B c )

Figure 16. Harmonic Distortion vs. Frequency and Gain (LFCSP)

–10

–9

–8–7–6–5–4–3–2–1012

307040-017

FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

Figure 17. Large Signal Frequency Response for Various Resistive Loads (LFCSP)

–10

–9–8–7–6–5–4–3–2–10123

07040-018FREQUENCY (MHz)N O R M A L I Z E D C L O S E D -L O O P G A I N (d B )

Figure 18. Small Signal Frequency Response for Various Gains (SOIC)

–120

–110

–100–90

–80–70

–60

–50–40

07040-019

FREQUENCY (MHz)

D I S T O R T I O N (d B c )

Figure 19. Harmonic Distortion vs. Frequency and Load (LFCSP)

ADA4857-1/ADA4857-2

Rev. A | Page 11 of 20

12345678

–120

–110

–100–90–80–70–60–50–40

07040-020

OUTPUT VOLTAGE (V p-p)

D I S T O R T I O N (d B c )

Figure 20. Harmonic Distortion vs. Output Voltage

5.75.8

5.9

6.1

6.0

6.26.3

110

100070

40-021

FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

Figure 21. 0.1 dB Flatness vs. Frequency for Various Output Voltages (SOIC)

O U T P U T V

O L T A G E (V )

07040-022

TIME (10ns/DIV)

2.5

–2.5

–2.02.0–1.5

1.5

–1.01.0–0.500.5Figure 22. Large Signal Transient Response for Various Output Voltages (SOIC)

S E

T T L I N G T I M E (%)

07040-023

TIME (5ns/DIV)

0.5–0.5

–0.4

0.4–0.30.3–0.20.2–0.100.1

Figure 23. Short-Term Settling Time (LFCSP)

5.7

5.8

5.9

6.1

6.0

6.2

6.3

110

100

07040

-024

FREQUENCY (MHz)

C L O S E

D -L O O P G A I N (d B )

Figure 24. 0.1 dB Flatness vs. Frequency for Various Output Voltages (LFCSP)

O U T P U T V O L T A G E (V )

07040-025

TIME (10ns/DIV)

2.5–2.5

–2.02.0–1.5

1.5

–1.01.0–0.500.5Figure 25. Large Signal Transient Response for Various Output Voltages (LFCSP)

ADA4857-1/ADA4857-2

Rev. A | Page 12 of 20

O U T P U T V O L T A G E (V )

07040-026

TIME (10ns/DIV)

0.25–0.25

–0.200.20–0.150.15

–0.100.10–0.0500.05

Figure 26. Small Signal Transient Response for Various Capacitive Loads (LFCSP)

O U T P U T V O L T A G E (V )

07040-027

TIME (10ns/DIV)

0.25–0.25

–0.200.20–0.15

0.15

–0.100.10–0.0500.05

Figure 27. Small Signal Transient Response for Various Supply Voltages (LFCSP)

0.11

101001000

07040-028

FREQUENCY (MHz)C L O S E D -L O O P O U T P U T I M P E D A N C E (?)

Figure 28. Closed-Loop Output Impedance vs. Frequency for Various Gains

O U T P U T V O L T A G E (V )

07040-029

TIME (10ns/DIV)

2.0–2.0

–1.61.6–1.21.2–0.80.8–0.400.4Figure 29. Large Signal Transient Response for Various Load Resistances (SOIC)

O U T P U T V O L T A G E (V )

07040-030

TIME (10ns/DIV)

2.0–2.0

–1.61.6–1.2

1.2–0.80.8–0.400.4Figure 30. Large Signal Transient Response for Various Load Resistances (LFCSP)

1101001000

07040-031

FREQUENCY (MHz)

C L O S E

D -L O O P I N P U T I M P

E D A N C E (k ?)

0.01

0.1

100

Figure 31. Closed-Loop Input Impedance vs. Frequency

ADA4857-1/ADA4857-2

Rev. A | Page 13 of 20

–100102030405060

8070–180–160

–140–120–100–80–60–40–20O P E N -L O O P P H A S E (D e g r e e s )

07040-032

FREQUENCY (MHz)

O P E N -L O O P G A I N (d B )

Figure 32. Open-Loop Gain and Phase vs. Frequency

07040-03

O U T P U T V O L T A G E (V )

TIME (40ns/DIV)

8–8

6–6

–4

4–202

Figure 33. Input Overdrive Recovery for Various Resistive Loads

–30–20–10010–80–70

–60

–50–400.1

110

1001000

07040-034

FREQUENCY (MHz)

P S R R (d B )

Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency

–30–20–10

0–100

–70–80–90

–60–50

–400.1

100

1000

07040-035

FREQUENCY (MHz)

P D I S O L A T I O N (d B )

Figure 35. PD Isolation vs. Frequency

07040-03

O U T P U T V O L T A G E (V )

TIME (200ns/DIV)

8–8

6–6–44

–202

Figure 36. Output Overdrive Recovery for Various Resistive Loads

–30

–90–80

–70

–60

–50

–40

07040-037

FREQUENCY (MHz)

C M R R (d B )

Figure 37. Common-Mode Rejection Ratio (CMRR) vs. Frequency

ADA4857-1/ADA4857-2

Rev. A | Page 14 of 20

07040-050

FREQUENCY (Hz)

C U R R E N T N O I S E (p A /√H z

)

110

100

1001k 10k 100k 1M

Figure 38. Input Current Noise vs. Frequency

5040

4.954.904.85

5.00007040-042

SUPPLY CURRENT (mA)

C O U N T

5.15

5.10

5.05

Figure 39. Supply Current

07040-041FREQUENCY (Hz)

V O L T A G E N O I S E (n V /√H z )

1000

100

1101001k 10k 100k

Figure 40. Input Voltage Noise vs. Frequency

07040-043

V O L T A G E (V )

TIME (20μs/DIV)

3.5–0.5

3.00

0.5

2.51.01.5

2.0

Figure 41. Disable/Enable Switching Speed

ADA4857-1/ADA4857-2

Rev. A | Page 15 of 20

TEST CIRCUITS

V IN

V OUT

07040-047

Figure 42. Noninverting Load Configuration

OUT 07040-045

Figure 43. Positive Power Supply Rejection

OUT

+V 07040-051

Figure 44. Typical Capacitive Load Configuration (LFCSP)

OUT 07040-046

Figure 45. Common-Mode Rejection

OUT +V S

07040-048

Figure 46. Negative Power Supply Rejection

OUT

07040-049

Figure 47. Typical Capacitive Load Configuration (SOIC)

ADA4857-1/ADA4857-2

Rev. A | Page 16 of 20

APPLICATIONS INFORMATION

POWER-DOWN OPERATION

The PD pin is used to power down the chip, which reduces the quiescent current and the overall power consumption. It is low enabled, which means that the chip is on with full power when the PD pin input voltage is low (see Table 8). Note that PD does not put the output in a high-Z state, which means that the ADA4857 should not be used as a multiplexer.

Table 8. PD Operation Table Guide Supply Voltage Condition ±5 V ±2.5 V +5 V Enabled

≤+0.8 V ≤?1.7 V ≤+0.8 V Powered down

≥+3 V

≥+0.5 V

≥+3 V

CAPACITIVE LOAD CONSIDERATIONS

When driving a capacitive load using the SOIC package, R SNUB is used to reduce the peaking (see Figure 47). An optimum resistor value of 40 Ω is found to maintain the peaking within 1 dB for any capacitive load up to 40 pF.

RECOMMENDED VALUES FOR VARIOUS GAINS

Table 9 provides a useful reference for determining various gains

and associated performance. R F and R G are kept low to minimize their contribution to the overall noise performance of the amplifier.

Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; V S = ±5 V, T A = 25°C, R L = 1 kΩ, R T = 49.9 Ω

Gain R F (Ω) R G (Ω)

?3 dB SS BW (MHz), V OUT = 200 mV p-p Slew Rate (V/μs),

V OUT = 2 V Step ADA4857 Voltage Noise (nV/√Hz), RTO Total System

Noise (nV/√Hz), RTO +1 0 N/A 850 2350 4.4 4.49 +2 499 499 360 1680 8.8 9.89 +5 499 124 90 516 22.11 23.49 +10 499 56.2 43

213

43.47

45.31

ADA4857-1/ADA4857-2

Rev. A | Page 17 of 20

ACTIVE LOW-PASS FILTER (LPF)

Active filters are used in many applications such as antialiasing filters and high frequency communication IF strips. With a 410 MHz gain bandwidth product and high slew rate, the ADA4857-2 is an ideal candidate for active filters. Figure 48 shows the frequency response of 90 MHz and 45 MHz LPFs. In addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. In this case, a 90 MHz bandwidth with a 2 V p-p output swing requires at least 2800 V/μs.

The circuit shown in Figure 49 is a 4-pole, Sallen-Key LPF. The filter comprises two identical cascaded Sallen-Key LPF sections, each with a fixed gain of G = 2. The net gain of the filter is equal to G = 4 or 12 dB. The actual gain shown in Figure 48 is 12 dB. This does not take into account the output voltage being divided in half by the series matching termination resistor, R T , and the load resistor.

Setting the resistors equal to each other greatly simplifies the design equations for the Sallen-Key filter. To achieve 90 MHz, the value of R should be set to 182 Ω. However, if the value of R is doubled, the corner frequency is cut in half to 45 MHz. This would be an easy way to tune the filter by simply multiplying the value of R (182 Ω) by the ratio of 90 MHz and the new corner frequency in megahertz.

Figure 48 shows the output of each stage is of the filter and the two different filters corresponding to R = 182 Ω and R = 365 Ω. Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. Due to the low capacitance values used in the filter circuit, the PCB layout and minimization of parasitics is critical. A few picofarads can detune the corner frequency, f c of the filter. The capacitor values shown in Figure 49 actually incorporate some stray PCB capacitance. Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors and silver mica, are good choices for filter elements.

–42–39–36–33

–30–27–24–21–18–15–12–9–6–3036912150.1

100

500

07040-074

FREQUENCY (MHz)

M A G N I T U D E (d B )

Figure 48. Low-Pass Filter Response

C1+IN107040-075

Figure 49. 4-Pole, Sallen-Key Low-Pass Filter (ADA4857-2)

ADA4857-1/ADA4857-2

Rev. A | Page 18 of 20

NOISE

T o analyze the noise performance of an amplifier circuit, identify the noise sources and determine if the source has a significant contribution to the overall noise performance of the amplifier. T o simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the

expressions (noise spectral density, which is generally expressed in nV/√Hz, is equivalent to the noise in a 1 Hz bandwidth). The noise model shown in Figure 50 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally referred to input (RTI), but it is often easier to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise.

= –R2

NG = 1 +

V OUT

07040-073

Figure 50. Op Amp Noise Analysis Model

All resistors have Johnson noise that is calculated by

)(4kBTR

where:

k is Boltzmann’s Constant (1.38 × 10–23 J/K). B is the bandwidth in Hertz.

T is the absolute temperature in Kelvin. R is the resistance in ohms.

A simple relationship that is easy to remember is that a 50 Ω resistor generates a Johnson noise of 1 nV/√Hz at 25°C. In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table 9. CIRCUIT CONSIDERATIONS

Careful and deliberate attention to detail when laying out the ADA4857 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier.

PCB LAYOUT

Because the ADA4857 can operate up to 850 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4857 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on the SOIC footprint can add as much as 0.2 pF of capacitance to ground if the ground plane is not cleared from under the mounting pads. The low distortion pinout of the ADA4857 increases the separation distance between the inputs and the supply pins, which improves the second harmonics. In addition, the feedback pin reduces the distance between the output and the inverting input of the amplifier, which helps minimize the parasitic inductance and capacitance of the feedback path, reducing ringing and peaking.

POWER SUPPLY BYPASSING

Power supply bypassing for the ADA4857 was optimized for frequency response and distortion performance. Figure 42 shows the recommended values and location of the bypass capacitors. The 0.1 μF bypassing capacitors should be placed as close as possible to the supply pins. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The capacitor between the two supplies helps improve PSR and distortion performance. The 10 μF electrolytic capacitors should be close to the 0.1 μF capacitors; however, it is not as critical. In some cases, additional paralleled capacitors can help improve frequency and transient response.

GROUNDING

Ground and power planes should be used where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input, output terminations, bypass capacitors, and R G should all be kept as close to the ADA4857 as possible. The output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. The ADA4857 LFSCP packages feature an exposed paddle. For optimum electrical and thermal performance, solder this paddle to the ground plane or the power plane. For more information on high speed circuit design, see A Practical Guide to High-Speed Printed-Circuit-Board Layout at https://www.wendangku.net/doc/4d7102139.html,.

ADA4857-1/ADA4857-2

Rev. A | Page 19 of 20

OUTLINE DIMENSIONS

072408-B

0.90 MAX 0.05 MAX 0.01 NOM

1.60

1.451.300.18

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 51. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2)

Dimensions shown in millimeters

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

012407-A

0.17 (0.0067)

0.40 (0.0157)

0.25 (0.0098)0.10 (0.0040)COPLANARITY

0.10

Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]

(R-8)

Dimensions shown in millimeters and (inches)

ADA4857-1/ADA4857-2

Rev. A | Page 20 of 20

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

COPLANARITY

0.08

PLANE

072808-A

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity

Branding ADA4857-1YCPZ-R21 –40°C to +125°C 8-Lead LFCSP_VD CP-8-2

250 H15 ADA4857-1YCPZ-RL 1

–40°C to +125°C 8-Lead LFCSP_VD CP-8-2 5,000 H15 ADA4857-1YCPZ-R71 –40°C to +125°C 8-Lead LFCSP_VD CP-8-2

1,500 H15 ADA4857-1YRZ 1

–40°C to +125°C 8-L ead SOIC_N R-8 1 ADA4857-1YRZ-R71 –40°C to +125°C 8-L ead SOIC_N R-8

2,500 ADA4857-1YRZ-RL 1

–40°C to +125°C 8-L ead SOIC_N R-8

1,000 ADA4857-2YCPZ-R21

–40°C to +125°C 16-Lead LFC S P_VQ CP-16-4 250 ADA4857-2YCPZ-RL 1 –40°C to +125°C 16-Lead LFC S P_VQ CP-16-4

5,000 ADA4857-2YCPZ-R71

–40°C to +125°C 16-Lead LFC S P_VQ CP-16-4

1,500

Z = RoHS Compliant Part.