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5962F9670601VXC中文资料

Ordering Information

PART NUMBER TEMPERATURE RANGE

SCREENING LEVEL

PACKAGE

5962F9670601VEC -55o C to +125o C MIL-PRF-38535 Class V 16 Lead SBDIP

5962F9670601VXC -55o C to +125o C

MIL-PRF-38535 Class V 16 Lead Ceramic Flatpack ACS161D/Sample 25o C Sample 16 Lead SBDIP

ACS161K/Sample 25o C Sample 16 Lead Ceramic Flatpack ACS161HMSR

25o C

Die

ACS161MS

Radiation Hardened

4-Bit Synchronous Counter

January 1996

Pinouts

16 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835, DESIGNATOR CDIP2-T16,

LEAD FINISH C TOP VIEW

16 PIN CERAMIC FLATPACK

MIL-STD-1835, DESIGNATOR CDFP4-F16,

LEAD FINISH C TOP VIEW

14151691312111012345768

CP P0P1P2P3GND PE VCC Q0Q1Q2Q3TE SPE

TC MR 2345678

1161514131211109

MR CP P0P1P2P3PE GND

VCC TC Q0Q1Q2Q3TE SPE

Features

?Devices QML Quali?ed in Accordance with MIL-PRF-38535?Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96706 and Intersil’ QM Plan ? 1.25 Micron Radiation Hardened SOS CMOS

?Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300K RAD (Si)?Single Event Upset (SEU) Immunity:<1 x 10-10 Errors/Bit/Day (Typ)

?SEU LET Threshold. . . . . . . . . . . . . . . . . . . . . . .>100 MEV-cm 2/mg ?Dose Rate Upset . . . . . . . . . . . . . . . .>1011 RAD (Si)/s, 20ns Pulse ?Dose Rate Survivability. . . . . . . . . . .>1012 RAD (Si)/s, 20ns Pulse ?Latch-Up Free Under Any Conditions

?Military Temperature Range . . . . . . . . . . . . . . . . . .-55o C to +125o C ?Signi?cant Power Reduction Compared to ALSTTL Logic ?DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V ?Input Logic Levels

-VIL = 30% of VCC Max -VIH = 70% of VCC Min ?Input Current ≤ 1μA at VOL, VOH

?Fast Propagation Delay. . . . . . . . . . . . . . . .21ns (Max), 14ns (Typ)

Description

The Intersil ACS161MS is a Radiation Hardened 4-Bit Binary Synchronous Counter. The MR is an active low master reset.SPE is an active low Synchronous Parallel Enable which disables counting and allows data at the preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is the terminal count or carry output. Both TE and PE must be high for counting to occur, but are irrelevant to loading. TE low will keep TC low.

The ACS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened,high-speed, CMOS/SOS Logic family.

The ACS161MS is supplied in a 16 lead Ceramic Flatpack (K suf?x) or a Ceramic Dual-In-Line Package (D suf?x).

Functional Diagram

TRUTH TABLE

OPERATING MODE INPUTS

OUTPUTS MR CP PE TE SPE P N Q N

TC Reset (Clear)L X

X X X X L L Parallel Load H X X I I L L H X X I h H

(Note 1)Count H h h h (Note 3)X count (Note 1)Inhibit

H X I (Note 2)

X h (Note 3)X q N (Note 1)

X X

I (Note 2)

h (Note 3)

q N

H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low volt-age level one setup time prior to the Low-to-High clock transition, X = Don’t Care,q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition, = Low-to-High Transition.NOTES:

1.The TC output is High when TE is High and the counter is at Terminal Count (HHHH).

2.The High-to-Low transition of PE or TE should only occur while ZCP is High for conventional operation.

3.The Low-to-High transition of SPE should only occur while CP is High for conventional operation.

4.The TC output is High when TE is High and the counter is at Terminal Count (HHHH).

CP J Q QN CD

K CP

J Q

QN CD

J Q QN CD

J Q QN SPE

Die Characteristics

DIE DIMENSIONS:88 mils x 88 mils 2240mm x 2240mm

METALLIZATION:T ype: AlSi

Metal 1 Thickness: 7.125k ?±1.125k ?Metal 2 Thickness: 9k ?±1k ?GLASSIVATION:T ype: SiO 2

Thickness: 8k ?±1k ?

WORST CASE CURRENT DENSITY:< 2.0 x 105A/cm 2BOND PAD SIZE:110μm x 110μm 4.3 mils x 4.3 mils

Metallization Mask Layout

ACS161MS

MR VCC TC (1)

(16)

(15)

CP (2)

P0 (3)P1 (4)P2 (5)

P3 (6)

(8)(7)(9)PE GND SPE (10)TE

(14) Q0

(13) Q1

(12) Q2

(11) Q3

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certi?cation. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speci?cations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site https://www.wendangku.net/doc/457808744.html,

Sales Of?ce Headquarters

NORTH AMERICA

Intersil Corporation

P. O. Box 883, Mail Stop 53-204 Melbourne, FL32902

TEL:(407) 724-7000

FAX: (407) 724-7240EUROPE

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

ASIA

Intersil (Taiwan) Ltd.

Taiwan Limited

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029