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CYM9273中文资料

CYM9271B CYM9272A CYM9273

64K x 36 SRAM Module

128K x 36 SRAM Module 256K x 36 SRAM Module 512K x 36 SRAM Module

Features

?Operates at 50 MHz

?Uses 64K x 18 / 128K x 18 or 256K x 18 high-performance synchronous SRAMs

?144-Position Angled DIMM from Berg p/n 61178?3.3V inputs/data outputs

Functional Description

The CYM9270, CYM9271B, CYM9272A, and the CYM9273are high-performance synchronous memory modules orga-nized as 64K(9270), 128K(9271B), 256K(9272A), 512K(9273)by 36 bits. These modules are constructed using either 128K x 18 SRAMs (9270, 9271B, 9272A) or 256K x 18 SRAMs

(9273) in plastic surface mount packages on an epoxy lami-nate board with pins. The modules are designed to be incor-porated into large memory arrays.

The modules are configured as single banks or multiple banks depending on the SRAM used to make the module. Separate clock are provided for each of the banks. Separate clocks are provided for each of the SRAMs.

Multiple ground pins and on-board decoupling capacitors en-sure high performance with maximum noise immunity.All components on the cache modules are surface mounted on a multi-layer epoxy laminate (FR-4) substrate. The contact pins are plated with 150 micro-inches of nickel covered by 30micro-inches of gold flash.

Logic Block Diagram -CYM9270

D[0:31]DQ[0:3]

A[15:0]

CS BW[0:3]PD 1

PD 0GND

9270

D[0:15]DQ[0:1]

CLK OE WE 64Kx36

(2) 128K x 18 SRAMs CLK[0:1]WEH WEL ADSC

A 15:0

SGW OE CS CLK[0:1]

BWE Bank 0

Bank0

ADSP CS

Logic Block Diagram-CYM9271B/CYM9272A

D[0:31]DQ[0:3]

A[16:0]

CS[0:1]BW[0:3]PD 1PD 0NC GND 9271B/72A

D[0:15]DQ[0:1]

CLK ADSC

A 16:0

SGW OE CS D[0:15]DQ[0:1]

CLK OE[0:1]WE 128Kx36256KX36

GND

(2) 128K x 18 SRAMs (2) 128K x 18 SRAMs CLK[0:1]CLK[2:3]

WEH WEL ADSC

A 16:0

SGW OE CS WEH WEL CLK[0:3]

BWE BWE Bank0

Bank1

Bank0

Bank0 and Bank1

ADSP CS1

CS0

OE1OE0

Logic Block Diagram-CYM9273

D[0:31]DQ[0:3]

A[17:0]

CS[0:1]BW[0:3]PD 1

PD 09273

D[0:15]DQ[0:1]

CLK

OE[0:1]WE (2) 256K x 18 SRAMs CLK[0:1]

WEH WEL ADSC

A 17:0

SGW OE

CLK[0:3]

BWE Bank1

D[0:15]DQ[0:1]

CLK (2) 256K x 18 SRAMs WEH WEL ADSC

A 17:0

SGW OE CS BWE ADSP Bank0

CLK[2:3]

512KX36

Bank0 and 1

CS[0]CS[1]

OE1OE0

PinConfiguration

Top View

Dual Read-Out SIMM (DIMM)

1095678412GND GND V CC339089858687888481828320191516171814111213302925262728242122D 30D 28D 24D 22D 26233935363738343132D 20D 14D 12DQ 1D 1833404142525147484950464344D 8D 6D 4D 0A 3D 24557585960565354A 5GND

A 2556965666768646162GND 637079757677787471727380GND D 21100999596979894919293D 29D 23D 27D 25110109105106107108104101102103D 19D 17D 15D 13120119115116117118114111112113D 11121122D 9D 7D 5D 3D 1127128129130126123124125GND A 6140139135136137138134131132133PD 0A 4144

141142143

A 9A 16A 12A 13D 16GND CS[0]A 8A 10A 14A 15PD 1V CC3V CC3A 1A 0A 7A 11V CC3GND CLK0CLK1V CC3D 10CLK3CLK2V CC3GND

GND D 31GND GND DQ 0DQ 2DQ 3GND GND A 17NC NC GND BW[2]CS[1]OE[1]ADSP NC NC NC V CC3V CC3V CC3BW[3]WE GND GND GND NC NC NC GND GND GND GND GND V CC3V CC3V CC3V CC3OE[0]BW[0]GND BW[1]GND V CC3NC NC NC NC NC NC NC NC NC NC NC NC GND GND V CC3NC GND NC NC NC NC V CC3NC NC NC NC NC

Pin Definitions

Signal Description

V CC33V Supply

GND Ground

A[17:0]Addresses from processor

ADSP Address strobe from the processor

OE[1:0]Output Enables for each of the banks

BW[0:3]Byte writes

WE Global Write

CS[1:0]Chip Select for the two banks

PD0–PD1Presence Detect output pins

D[31:0]Data lines from processor

DQ[3:0]Data Parity lines from processor

CLK[0:3]Clock lines to the module.

NC Signal not connected on module

RSVD Reserved

Presence Detect Pins

PD1PD0 CYM9270 – 64K x 36GND NC CYM9271B – 128K x 36NC GND CYM9272A – 256K x 36GND GND

CYM9273 – 512K x 36NC NC

Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage T emperature.................................–55°C to +125°C Ambient T emperature

with Power Applied.........................................–0°C to +70°C 3.3V Supply Voltage to Ground Potential......–0.5V to +4.5V DC Voltage Applied to Outputs

in High Z State..............................................–0.5V to +4.6V DC Input Voltage........................................... –0.5V to +4.6V Output Current into Outputs (LOW).............................20 mA

Operating Range

Range AmbientTemperature V CC Commercial 0°C to +70°C 3.3V ± 5%

Electrical Characteristics Over the Operating Range

Parameter Description Test Condition Min.Max.Unit V IH Input HIGH Voltage 2.2V CC + 0.3V V IL Input LOW Voltage–0.30.8V V OH Output HIGH Voltage V CC=Min. I OH = ?4 mA 2.4V V OL Output LOW Voltage V CC=Min. I OL = 8 mA0.4V I CC (9270)V CC Operating Supply Current V CC=Max., I OUT=0 mA, f=f MAX=1/t RC350mA

I CC (9271B)V CC Operating Supply Current V CC=Max., I OUT=0 mA, f=f MAX=1/t RC500 mA

I CC (9272A)V CC Operating Supply Current V CC=Max., I OUT=0 mA, f=f MAX=1/t RC1000 mA I CC (9273)V CC Operating Supply Current V CC=Max., I OUT=0 mA, f=f MAX=1/t RC1200 mA

Capacitance[1]

Parameter Description Test Conditions Max.Max.Unit

C A Address Input Capacitance T A = 25°C, f = 1 MHz,

V CC = 5.0V

927012pF 9271B7

9272A14

927320

C I Control Input Capacitance T A = 25°C, f = 1 MHz,

V CC = 5.0V

927012 9271B8 9272A16 927320

C O Input / Output Capacitance T A = 25°C, f = 1 MHz,

V CC = 5.0V

92709 9271B 5 9272A10 927316

C CLK Clock Capacitance T A = 25°C, f = 1 MHz,

V CC = 5.0V

92706 9271B 3 9272A 3 9273 5

Note:

1.T ested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms [3]

3.3V GND

90%

10%

90%10%

≤3ns

≤

3ns

OUTPUT

5pF

INCLUDING JIGAND SCOPE (a)

(b)

ALL INPUT PULSES

OUTPUT

R L =50 ?

V L = 1.5V

V CCQ [2]

Switching Characteristics Over the Operating Range

Parameter Description

CYM9270

CYM9271B CYM9272A CYM9273Min.Max.

Min.Max.

Unit t CYC Clock Cycle Time

12121212ns t CH Clock HIGH 4444ns t CL Clock LOW

4444ns t AS Address Set-Up Before CLK Rise 3333ns t AH Address Hold After CLK Rise 0.5

0.5

ns t CD V Data Output Valid After CLK Rise 10.3

10.3

10.3ns t DOH Data Output Hold After CLK Rise 3333ns t WES WH, WL Set-Up Before CLK Rise 3.1 3.1 3.1 3.1ns t WEH WH, WL Hold After CLK Rise 0.50.50.50.5ns t DS Data Input Set-Up Before CLK Rise 3.3 3.3

3.3 3.3ns t DH Data Input Hold After CLK Rise 0.50.50.5ns t CSS Chip Select Set-Up

3.1 3.1 3.1 3.1ns t CSH Chip Select Hold After CLK Rise 0.5

0.5

ns t EOZ [4]OE HIGH to Output High

Z 7

ns t EOV

OE LOW to Output Valid

777

Notes:

2.Resistor values for V CCQ =

3.3V are R1=317? and R2=351?.

3.Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output

loading of the specified I OL /I OH and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are at room temperature.4.t EOZ is specified with a load capacitance of 5 pF as in part (b) of AC T est Loads. T ransition is measured ± 500 mV from steady-state voltage.

Switching Waveforms

Single Read [5]

Single Write Timing

Notes:

5.OE is LOW throughout this operation.

6.ADSP has no effect on AD V , WL, and WH if CS is HIGH.

t CL t AS

t AH

t ADS

t ADSH

t CH

t CSS

t CSH

t WES

t WEH

t CDV

t DOH

t CYC

CLK

ADDRESS

ADSP

WH,WL

DA TA OUT

[6]

t CL

t AS

t AH t ADS

t ADSH t CH

t CSS

t CSH

t WES

t WEH t DS

t DH t EOZ

CLK

ADDRESS

ADSP WH,WL

DA TA IN

DAT A OUT

Document #: 38-M-00083-A

Output (Controlled by OE)

Output Timing (Controlled by CS)

Output Timing (Controlled by WH/ WL)

Switching Waveforms (continued)

t EOV

DA TA OUT

t EOZ

t CSS

t CSH t CSS

t CSH

t CDV

t CSOZ

CLK

DAT A OUT

t ADS

t ADSH

t ADS

t ADSH

ADSP

t ADS

CLK

t WEOZ

t WEOV

WH,WL

DAT A OUT

t WES

t WEH t ADSH

t ADSH

ADSP

Ordering Information

Speed(MHz)Ordering Code Package Name Package Type

Description Operating Range 50

CYM9270PM-50C PM45144-Pin Dual-Readout SIMM Sync 64K x 36Commercial

CYM9271BPM-50C PM45144-Pin Dual-Readout SIMM Sync 128K x 36CYM9272APM-50C PM46144-Pin Dual-Readout SIMM Sync 256K x 36CYM9273PM-50C

PM46

144-Pin Dual-Readout SIMM

Sync 512K x 36

? Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Package Diagrams

144-Pin Single-Sided DIMM PM45

144-Pin Dual-Sided DIMM PM46