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end behave;
当前编译的程序文件没有放在指定文件夹内,所以系统找不到WORK工作库。
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五、VHDL 程序设计:(15分)
设计一数据选择器MUX,其系统模块图和功能表如下图所示。试采用下面三种方式中的两种来描述该数据选择器MUX 的结构体。
MUX
SEL(1:0)
AIN(1:0)BIN(1:0)
COUT(1:0)
SEL COUT 00
011011OTHERS
A or
B A xor B
A nor
B A and B “XX ”
(a) 用if 语句。 (b) 用case 语句。 (c) 用when else 语句。
Library ieee; Use mymux is Port ( s el : in std_logic_vector(1 downto 0);
-- 选择信号输入 Ain, Bin : in std_logic_vector(1 downto 0); -- 数据输入
Cout : out std_logic_vector(1 downto 0) );
End mymux;
Architecture one of mymux is Begin Process (sel, ain, bin) Begin If sel = “00” then cout <= ain or bin; Elsif sel = “01” then cout <= ain xor bin; Elsif sel = “10” then cout <= ain and bin; Else cout <= ain nor bin;
End if;
End process;
End one;
Architecture two of mymux is Begin Process (sel, ain, bin) Begin Case sel is
when “00” => cout <= ain or bin;
六、根据原理图写出相应的VHDL 程序:(15分)
Library ieee; Use mycir is Port ( din, clk : in std_logic;
Qout : out std_logic);
End mycir;
Architecture behave of mycir is
Signal a, b, c;
Begin Qout <= c nand (a xor b); Process (clk) Begin If clk ’event and clk = ‘1’ then A <= din; B <= A;
C <= B;
End if;
End process;
End behave;
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七、综合题:(20分)
(一)已知状态机状态图如图a 所示;完成下列各题:
st0
st1
st2
st3
in_a = “00”
in_a /= “00”
in_a = “01”
in_a /= “01”
in_a = “11”
in_a /= “11”
in_a = “11”
in_a /= “11”
out_a <= “0101”;
out_a <= “1000”;
out_a <= “1100”;
out_a <= “1101”;
图a 状态图
REG
COM
clk reset
in_a
out_a
c_state
n_state
图b 状态机结构图
1. 试判断该状态机类型,并说明理由。
该状态机为moore 型状态机,输出数据outa 和输入ina 没有直接逻辑关系,outa 是时钟clk 的同步时序
逻辑。
2. 根据状态图,写出对应于结构图b ,分别由主控组合进程和主控时序进程组成的VHDL 有限状态机描述。
Library ieee; Use mooreb is Port (clk, reset : in std_logic; Ina : in std_logic_vector (1 downto 0);
Outa : out std_logic_vector (3 downto 0) );
End mooreb;
End if;
End process; Process (c_st) Begin Case c_st is
When st0 => if ina = “00” then n_st <= st0;
Else n_st <= st1; End if;
Outa <= “0101”;
When st1 => if ina = “00” then n_st <= st1; Else n_st <= st2;
End if;
Outa <= “1000”;
When st2 => if ina = “11” then n_st <= st0;
Else n_st <= st3;
End if;
Outa <= “1100”;
When st3 => if ina = “11” then n_st <= st3; Else n_st <= st0;
End if;
Outa <= “1101”;
When others => n_st <= st0;
End case;
End process;
End one;
3. 若已知输入信号如下图所示,分析状态机的工作时序,画出该状态机的状态转换值(c_state )和输出控
制信号(out_a);
Architecture one of mooreb is
Type ms_state is (st0, st1, st2, st3);
Signal c_st, n_st : ms_state; Begin
Process (clk, reset)
Begin
If reset = ‘1’ then c_st <= st0;
Elsif clk’event and clk = ‘1’ then c_st <= n_st;4.若状态机仿真过程中出现毛刺现象,应如何消除;试指出两种方法,并简单说明其原理。方法1,添加辅助进程对输出数据进行锁存
方法2,将双进程状态机改写为单进程状态机,其输出也是锁存过了,故能消除毛刺
方法3,使用状态位直接输出型状态机编码方式,其输出直接由当前状态输出,也没有毛刺
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(二)已知一个简单的波形发生器的数字部分系统框图如下图所示
图中lcnt、lrom都是在MAX+PlusII中使用MegaWizard调用的LPM模块,其VHDL描述中Entity部分分别如下:
ENTITY lcnt IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lcnt;
ENTITY lrom IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lrom;
试用VHDL描述该系统的顶层设计(使用例化语句)。Library ieee;
Use mysg is
Port (clk : in std_logic;
To_da : out std_logic_vector (9 downto 0) );
End mysq;
Architecture one of mysq is
Signal addr : std_logic_vector (9 downto 0);
Component lcnt
Port (clock : in std_logic;
Q : out std_logic_vector (9 downto 0) );
End component;
Component lrom
Port (address : in std_logic_vector (9 downto 0);
Q : out std_logic_vector (9 downto 0) );
End component;
Begin
U1 : lcnt port map (clock => clk, q => addr);
U2 : lrom port map (address => addr, q => to_da);
End one;
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