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PPC440GX-3CF667C中文资料

Part Number 440GX

Revision 1.15 – August 30, 2007 440GX

Power PC 440GX Embedded Processor

Data Sheet Features

?PowerPC? 440 processor core operating up to 800MHz with 32KB I- and D-caches (with parity checking)

?On-chip 256KB SRAM configurable as L2 Code store or Ethernet Packet store memory ?Selectable processor:bus clock ratios (Refer to the Clocking chapter in the PPC440GX

Embedded Processor User’s Manual for details)?Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 166MHz

(200MHz for 800MHz Rev F parts)

?External Peripheral Bus (32 bits) for up to eight devices with external mastering

?DMA support for external peripherals, internal UART and memory

?PCI-X V1.0a interface (32 or 64 bits, up to 133MHz) with support for conventional PCI V2.3?Two Ethernet 10/100/1000Mbps half- or full-duplex interfaces. Operational modes supported are SMII, GMII, RGMII, TBI and RTBI.?TCP/IP Acceleration Hardware (TAH) provided for 10/100/1000 Mbps ports that performs checksum processing, TCP segmentation, and includes

support for jumbo frames

?Programmable Interrupt Controller supports interrupts from a variety of sources.

?I2O Messaging unit for message transfer between the CPU and PCI-X

?Programmable General Purpose Timers (GPT)?Two serial ports (16750 compatible UART)

?Two IIC interfaces

?General Purpose I/O (GPIO) interface available ?JTAG interface for board level testing ?Processor can boot from PCI memory ?Available in ceramic (RoHs and non-RoHS compliant versions) and plastic packages (RoHS and non-RoHS compliant versions).

Description

Designed specifically to address high-end embedded applications, the PowerPC 440GX (PPC440GX) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation.

This chip contains a high-performance RISC processor core, DDR SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, PCI-X bus interface, Gigabit Ethernet interfaces, TCP/IP acceleration hardware, I2O messaging unit, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.Technology: CMOS Cu-11, 0.13μm

Packages: 25mm, 552-ball Ceramic Ball Grid Array (CBGA) or Plastic Ball Grid Array (PBGA) in standard or RoHS compliant versions

Power (estimated): Less than:

4W typical @533MHz

5W typical @667MHz

6W typical @800MHz (estimated)

Supply voltages required: 3.3V, 2.5V, 1.5V

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

Contents

Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLB Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

I2O Messaging Unit (IMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Heat Sink Mounting Information (Ceramic Package Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

Figures

PPC440GX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

25mm, 552-Ball Ceramic (CBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

25mm, 552-Ball Plastic (FC-PBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Heat Sink Attached With Spring Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Heat Sink Attached With Adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DDR SDRAM MemClkOut0 and Read Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DDR SDRAM Read Cycle Timing—Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DDR SDRAM Read Cycle Timing—Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DDR SDRAM Read Cycle Timing—Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Tables

Order Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

I/O Specifications—500MHz–800MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

I/O Timing—DDR SDRAM T DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

I/O Timing—DDR SDRAM T SK, T SA, and T HA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

I/O Timing—DDR SDRAM T SD and T HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

I/O Timing—DDR SDRAM T SIN and T DIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet Ordering and PVR Information

For information on the availability of the following parts, contact your local AMCC sales office.

Order Part Numbers

Product Name

Order Part Number

(See Notes and Key drawing)

Processor

Frequency

Package

Rev

Level

PVR Value JTAG ID

PPC440GX PPC440GX-3CC533S533MHz25mm, 552 CBGA C0x51B218920x32054049 PPC440GX PPC440GX-3CC667S667MHz25mm, 552 CBGA C0x51B218920x32054049 PPC440GX PPC440GX-3CF400C 400MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3CF533C533MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3CF533CZ533MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3CF533E533MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3CF667C667MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3CF667CZ667MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3CF800C800MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3CF800CZ800MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3FF533C533MHz25mm, 552 PBGA F0x51B218940x52054049 PPC440GX PPC440GX-3FF533E533MHz25mm, 552 PBGA F0x51B218940x52054049 PPC440GX PPC440GX-3FF667C667MHz25mm, 552 PBGA F0x51B218940x52054049 PPC440GX PPC440GX-3FF667E667MHz25mm, 552 PBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF400C400MHz25mm, 552 PBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF533C533MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF533CZ533MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF533E533MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF667C667MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF667CZ667MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF800C800MHz25mm, 552 CBGA F0x51B218940x52054049 PPC440GX PPC440GX-3RF800CZ800MHz25mm, 552 CBGA F0x51B218940x52054049

440GX – Power PC 440GX Embedded Processor

Revision 1.15 – August 30, 2007

Data Sheet

Each part number contains a revision code. This is the die mask revision number and is included in the part number for identification purposes only.

The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PPC440GX User’s Manual for details on accessing these registers.

Order Part Number Key

PPC440GX PPC440GX-3NF533C 533MHz 25mm, 552 PBGA F 0x51B218940x52054049PPC440GX PPC440GX-3NF533E 533MHz 25mm, 552 PBGA F 0x51B218940x52054049PPC440GX PPC440GX-3NF667C 667MHz 25mm, 552 PBGA F 0x51B218940x52054049PPC440GX PPC440GX-3NF667E

667MHz

25mm, 552 PBGA

0x51B21894

0x52054049

Notes:

1.Package code: C = leaded ceramic, F = plastic, R = reduced-lead ceramic (RoHS compliant), N = lead-free plastic (RoHS compliant).

2.Case Temperature Range code: C = -40 °C to +85 °C, E = -40 °C to +105 °C for C package and -40 °C to +100 °C for F package, S = -40 °C to +85 °C and no L2 cache support.

3.Z at the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray.

4.Revision code: C = rev 2.1, F = rev 3.1.

Order Part Numbers (Continued)

Product Name Order Part Number

(See Notes and Key drawing)Processor Frequency Package Rev Level PVR Value JTAG ID Part Number PPC440GX-3CC800Ex

Package

Processor Speed Grade 3 Reliability

Case Temperature Range Revision Level

Shipping Package

440GX – Power PC 440GX Embedded Processor

Revision 1.15 – August 30, 2007

Data Sheet

PPC440GX Functional Block Diagram

The PPC440GX is designed using the IBM ? Microelectronics Blue Logic ? methodology in which major functional blocks are integrated together to create an application-specific product (ASIC). This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus ? Architecture.Note: IBM CoreConnect buses provide:

?128-bit PLB interfaces up to 200MHz

?32-bit OPB interfaces up to 83.33MHz, 333MB/s

Address Maps

The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various address regions which the processor can access. The

second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GX processor through the use of mtdcr and mfdcr instructions.

Processor Core DCR Bus

32KB On-chip Peripheral Bus (OPB)

GPIO

IIC UART DMA Bridge

Processor Local Bus (PLB)

DDR SDRAM External Bus Controller

Controller

Clock Control Reset

Power Mgmt

JTAG Trace Timers MMU

Controller OPB Interrupt Controller

Arb 32-bit addr 32-bit data

13-bit addr

32/64-bit data

External

Bus Master Controller Universal I-Cache

32KB D-Cache

(4-Channel)

SRAM 256KB

PPC440

63 internal 18 external

PCI-X Bridge

x2x2

MAL

Ethernet

DCRs

1 GMII or

2 RGMII or 1 TBI or

2 RTBI

GP Timers

1 MII or

2 RMII or

4 SMII

ZMII RGMII I2O Messaging

83MHz max L2 Controller

10/100TAH 10/100/1000 x2133MHz max 166MHz max Bridge

Bridge

32/64-bit data

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

System Memory Address Map (Sheet 1 of 2)

Function Sub Function Start Address End Address Size

Local Memory1DDR SDRAM0 0000 00000 7FFF FFFF2GB SRAM0 8000 00000 8000 3FFF256KB Reserve0 8000 40000 FFFE FFFF

IMU0 FFFF 00000 FFFF FFFF64KB

Internal Peripherals EBC 1 0000 0000 1 3FFF FFFF1GB Reserved 1 4000 0000 1 4000 01FF

UART0 1 4000 0200 1 4000 02078B Reserved 1 4000 0208 1 4000 02FF

UART1 1 4000 0300 1 4000 03078B Reserved 1 4000 0308 1 4000 03FF

IIC0 1 4000 0400 1 4000 041F32B Reserved 1 4000 0420 1 4000 04FF

IIC1 1 4000 0500 1 4000 051F32B Reserved 1 4000 0520 1 4000 05FF

OPB Arbiter 1 4000 0600 1 4000 063F64B Reserved 1 4000 0640 1 4000 06FF

GPIO Controller 1 4000 0700 1 4000 077F128B Ethernet PHY ZMII 1 4000 0780 1 4000 078F16B Ethernet PHY GMII 1 4000 0790 1 4000 079F16B Reserved 1 4000 07A0 1 4000 07FF

Ethernet 0 Controller 1 4000 0800 1 4000 08FF256B Ethernet 1 Controller 1 4000 0900 1 4000 09FF256B General Purpose Timer 1 4000 0A00 1 4000 0AFF256B TCPIP Accelerator 0 1 4000 0B00 1 4000 0BFF256B Ethernet 2 Controller 1 4000 0C00 1 4000 0CFF256B TCPIP Accelerator 1 1 4000 0D00 1 4000 0DFF256B Ethernet 3 Controller 1 4000 0E00 1 4000 0EFF256B Reserved 1 4000 0F00 1 EFFF FFFF

Expansion ROM2 1 F000 0000 1 FFDF FFFF254MB Boot ROM2, 3 1 FFE0 0000 1 FFFF FFFF2MB

440GX – Power PC 440GX Embedded Processor

Revision 1.15 – August 30, 2007

Data Sheet

PCI-X

Reserved 2 0000 0000 2 07FF FFFF PCI-X I/O 2 0800 0000 2 0BFF FFFF 64MB Reserved

2 0C00 0000 2 0EBF FFFF PCI-X External Configuration Registers

2 0EC0 0000 2 0EC0 00078B Reserved

2 0EC0 0008 2 0EC7 FFFF PCI-X Bridge Core Configuration Registers 2 0EC8 0000 2 0EC8 00FF 256B Reserved

2 0EC8 0100 2 0EC8 00FF PCI-X Special Cycle 2 0ED0 0000 2 0EDF FFFF 1MB PCI-X Memory

2 0EE0 0000

F FFFF FFFF

55.76GB Notes:

1.DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.

2.The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.

3.When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 2 FFFE 0000 (128 KB).

System Memory Address Map (Sheet 2 of 2)

Function

Sub Function

Start Address End Address Size

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

DCR Address Map 4KB of Device Configuration Registers

Function Start Address End Address Size

Total DCR Address Space10003FF1KW (4KB)1

By function:

Reserved00000B12W Clocking Power On Reset00C00D2W

System DCRs 00E00F2W

Memory Controller 0100112W

External Bus Controller0120132W

External Bus Master I/F 0140152W

PLB Performance Monitor01601F10W

SRAM02002F16W

L2 Controller03003F16W Reserved04007F64W

PLB 08008F16W

PLB to OPB Bridge Out09009F16W Reserved0A00A78W

OPB to PLB Bridge In 0A80AF8W

Power Management0B00B78W Reserved0B80BF8W

Interrupt Controller 00C00CF16W

Interrupt Controller 10D00DF16W

Clock, Control, and Reset0E00EF16W Reserved0F00FF16W

DMA Controller 10013F64W Reserved14017F64W Ethernet MAL1801FF128W

Base Interrupt Controller20020F16W

Interrupt Controller 221021F16W Reserved2203FF480W Notes:

1.DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit

(word) register. One kiloword (1024W) equals 4KB (4096 bytes).

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet PowerPC 440 Processor Core

The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, ISCSI, routers, switches, printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.

Features include:

?Up to 800MHz operation

?PowerPC Book E architecture

?32KB I-cache, 32KB D-cache

-UTLB Word Wide parity on data and tag address parity with exception force

?Three logical regions in D-cache: locked, transient, normal

?D-cache full line flush capability

?41-bit virtual address, 36-bit (64GB) physical address

?Superscalar, out-of-order execution

?7-stage pipeline

? 3 execution pipelines

?Dynamic branch prediction

?Memory management unit

-64-entry, full associative, unified TLB with parity

-Separate instruction and data micro-TLBs

-Storage attributes for write-through, cache-inhibited, guarded, and big or little endian

?Debug facilities

-Multiple instruction and data range breakpoints

-Data value compare

-Single step, branch, and trap events

-Non-invasive real-time trace interface

?24 DSP instructions

-Single-cycle multiply and multiply-accumulate

-32 x 32 integer multiply

-16 x 16 -> 32-bit MAC

Internal Buses

The PowerPC 440GX features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores.

Features include:

?PLB

-128-bit implementation of the PLB architecture

-Separate and simultaneous read and write data paths

-64-bit address

-Simultaneous control, address, and data phases

-Four levels of pipelining

-Byte enable capability supporting unaligned transfers

-32- and 64-byte burst transfers

-166MHz, maximum 5.2GB/s (simultaneous read and write)(200MHz for 800MHz Rev F parts)

-Processor:bus clock ratios of N:1 and N:2

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

?OPB

-Dynamic bus sizing 32-, 16-, and 8-bit data path

-36-bit address

-83.33MHz, maximum 333MB/s

?DCR

-32-bit data path

-10 bit address

On-Chip SRAM

Features include:

?Four banks of 64KB each for a total of 256KB

?Configurable as either Code (L2) cache or software-controlled on-chip memory, or SRAM

?Memory cycles supported:

-Single beat read and write, 1 to 16 bytes

-32- and 64-byte burst transfers

-Guarded memory accesses

?Sustainable 2.6GB/s peak bandwidth at 166MHz

?Use as an L2 cache improves processor performance and reduces the PLB load

-Cache coherency maintained by a hardware snoop mechanism or software

-Data Array and Tag Array parity

-Unified data and instruction cache

-4-way set associative

-36-bit addressing

-Full LRU replacement algorithm

-Write through, look aside

?Use as Ethernet packet store allows Ethernet packets to be held for processing by the TAH unit

PCI-X Interface

The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory. This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit PCI-X buses. PCI 32/64-bit conventional mode, compatible with PCI Version 2.3, is also supported.

Reference Specifications:

?PowerPC CoreConnect Bus (PLB) Specification Version 3.1

?PCI Specification Version 2.3

?PCI Bus Power Management Interface Specification Version 1.1

Features include:

?PCI-X 1.0a

-Split transactions

-Frequency to 133MHz

-32- and 64-bit bus

?PCI 2.3 backward compatibility

-Frequency to 66MHz

-32- and 64-bit bus

?Can be the PCI Host Bus Bridge or an Adapter Device's PCI interface

?Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an external arbiter

?Support for Message Signaled Interrupts

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet ?Simple message passing capability

?Asynchronous to the PLB

?PCI Power Management 1.1

?PCI register set addressable both from on-chip processor and PCI device sides

?Ability to boot from PCI-X bus memory

?Error tracking/status

?Supports initiation of transfer to the following address spaces:

-Single beat I/O reads and writes

-Single beat and burst memory reads and writes

-Single beat configuration reads and writes (type 0 and type 1)

-Single beat special cycles

DDR SDRAM Memory Controller

The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and memory addressing modes are programmable.

Features include:

?Registered and non-registered industry standard DIMMs

?64-bit memory interface with optional 8-bit ECC (SEC/DED)

?Sustainable 2.6GB/s peak bandwidth at 166MHz (200MHz for 800MHz Rev F parts)

?SSTL_2 logic

? 1 to 4 chip selects

?CAS latencies of 2, 2.5 and 3 supported

?DDR200/266/333 support

?Page mode accesses (up to eight open pages) with configurable paging policy

?Programmable address mapping and timing

?Hardware and software initiated self-refresh

?Power management (self-refresh, suspend, sleep)

External Peripheral Bus Controller (EBC)

Features include:

?Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported

?Up to 83.33MHz operation (333MB/s)

?Burst and non-burst devices

?8-, 16-, 32-bit byte-addressable data bus

?32-bit address, 4GB address space

?Peripheral Device pacing with external “Ready”

?Latch data on Ready, synchronous or asynchronous

?Programmable access timing per device

-256 Wait States for non-burst

-32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses

-Programmable CSon, CSoff relative to address

-Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS

?Programmable address mapping

?External DMA Slave Support

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

?External master interface

-Write posting from external master

-Read prefetching on PLB for external master reads

-Bursting capable from external master

-Allows external master access to all non-EBC PLB slaves

-External master can control EBC slaves for own access and control

Ethernet Controller Interface

Ethernet support provided by the PPC440GX interfaces to the physical layer, but the PHY is not included on the chip.

Features include:

?One to four 10/100 interfaces running in full- and half-duplex modes

-One full Media Independent Interface (MII) with 4-bit parallel data transfer

-Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer

-Four Serial Media Independent Interfaces (SMII)

?One or two GMII interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s -One full Gigabit Media Independent Interface (GMII) with 8-bit parallel data transfer

-Two Reduced Gigabit Media Independent Interfaces (RGMII) with 4-bit parallel data transfer

?One or two TBI interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s -One full Ten Bit Interface (TBI) with 10-bit parallel data transfer

-Two Reduced Ten Bit Interfaces (RTBI) with 4-bit parallel data transfer

?Jumbo frame support (9016 byte)

-Support for Ethernet II formatted frames (RFC894)

-Support for IEEE formatted frames (RFC1042)

-Handles VLAN-tagged frames

TCP/IP Acceleration Hardware (TAH)

Features include:

?Offloads Gigabit Ethernet protocol processing from the CPU

?Checksum verification for TCP/UDP/IP headers in the receive path

?Checksum generation for TCP/UDP/IP headers in the transmit path

?TCP segmentation support in the transmit path

DMA Controller

Features include:

?Supports the following transfers:

-Memory-to-memory transfers

-Buffered peripheral to memory transfers

-Buffered memory to peripheral transfers

?Four channels

?Scatter/Gather capability for programming multiple DMA operations

?8-, 16-, 32-bit peripheral support (OPB and external)

?64-bit addressing

?128 byte FIFO buffer

?Address increment or decrement

?Supports internal and external peripherals

?Support for memory mapped peripherals

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet ?Support for peripherals running on slower frequency buses

Serial Port

Features include:

?One 8-pin UART and one 4-pin UART interface provided

?Selectable internal or external serial clock to allow wide range of baud rates

?Register compatibility with 16750 register set

?Complete status reporting capability

?Fully programmable serial-interface characteristics

?Supports DMA using internal DMA engine

IIC Bus Interface

Features include:

?Two IIC interfaces provided

?Support for Philips? Semiconductors I2C Specification, dated 1995

?Operation at 100kHz or 400kHz

?8-bit data

?10- or 7-bit address

?Slave transmitter and receiver

?Master transmitter and receiver

?Multiple bus masters

?Supports fixed V DD IIC interface

?Two independent 4 x 1 byte data buffers

?Twelve memory-mapped, fully programmable configuration registers

?One programmable interrupt request signal

?Provides full management of all IIC bus protocols

?Programmable error recovery

General Purpose Timers (GPT)

Provides a separate time base counter and additional system timers in addition to those defined in the processor core.

?32-bit Time Base Counter driven by the OPB bus clock

?Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

?Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses.

?The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose.

?Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1).

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

Universal Interrupt Controller (UIC)

Four Universal Interrupt Controllers (UIC) are available. They provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.

Note: Processor specific interrupts (for example, page faults) do not use UIC resources.

Features include:

?18 external interrupts

?63 internal interrupts

?Edge triggered or level-sensitive

?Positive or negative active

?Non-critical or critical interrupt to the on-chip processor core

?Programmable interrupt priority ordering

?Programmable critical interrupt vector for faster vector processing

PLB Performance Monitor

The PLB Performance Monitor (PPM) provides hardware for counting certain events associated with PLB transactions. The contents of the counters can be read by software for analysis and enhancement of PLB performance, or software debug. The data includes identification and duration of the events.

I2O Messaging Unit (IMU)

The IMU interfaces to the PLB as a master or slave and allows messages to be transferred between two PLB masters (for example, the 440 CPU and PCI-X).

Features include:

?Three messaging methods

- 4 Message registers—2 inbound, 2 outbound

- 2 Doorbell registers—1 inbound, 1 outbound

- 4 Circular queues—2 inbound, 2 outbound

?Up to 7 different interrupt outputs generated

?Support for interrupt masking

JTAG

Features include:

?IEEE 1149.1 Test Access Port

?IBM RISCWatch Debugger support

?JTAG Boundary Scan Description Language (BSDL)

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet 25mm, 552-Ball Ceramic (CBGA) Package

440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007

Data Sheet

25mm, 552-Ball Plastic (FC-PBGA) Package

440GX – Power PC 440GX Embedded Processor

Revision 1.15 – August 30, 2007

Data Sheet

Signal Lists

The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each signal name on the ball. The page number listed gives the page in “Signal Functional Description” on page 50 where the signals in the indicated interface group begin. In cases where signals in the same interface group (for example, Ethernet) have different names to distinguish variations in the mode of operation, the names are separated by a comma with the primary name appearing first. These signals are listed only once, and appear alphabetically by the primary name.

Signals Listed Alphabetically (Sheet 1 of 24)

Signal Name

Ball Interface Group

Page

AGND J01Power—Analog ground

AGND J24AGND AA11AMV DD AB11Power—MemClkOut PLL analog voltage 57APV DD G01Power—PCI-X PLL analog voltage 57ASV DD G24Power—SysClk PLL analog voltage

BA0AA16

DDR SDRAM

BA1AD09BankSel0AB15DDR SDRAM

51BankSel1W14

BankSel2AD11BankSel3AD05[BE0]PCIXC0F14PCI-X

50[BE1]PCIXC1E16[BE2]PCIXC2C19[BE3]PCIXC3F20

[BE4]PCIXC4C08[BE5]PCIXC5C03[BE6]PCIXC6G09[BE7]PCIXC7F09BusReq[TrcTS1]AA24External Master Peripheral 54CAS AB05DDR SDRAM

51ClkEn0AD17DDR SDRAM

ClkEn1AB10

ClkEn2Y09ClkEn3

W09

440GX – Power PC 440GX Embedded Processor

Revision 1.15 – August 30, 2007

Data Sheet

DM0T16DDR SDRAM

DM1AA18DM2AB14DM3P13DM4AA09DM5AA07DM6Y03DM7V03DM8AC05DMAAck0N05External Slave Peripheral

DMAAck1

P07DMAAck2[GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0]

P06DMAAck3[GMCRxD1, GMC0RxD1, TBIRxD1, RTBI0RxD1]P11DMAReq0R03External Slave Peripheral

DMAReq1

M11DMAReq2[GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4]

N11DMAReq3[GMCTxEn, GMC0TxCtl, TBITxD8, RTBI0TxD4]P01DQS0AC20DDR SDRAM

DQS1AC16DQS2AC14DQS3AB13DQS4AC11DQS5AC09DQS6Y04DQS7T01DQS8AA05DrvrInh2

A05

System 56Signals Listed Alphabetically (Sheet 2 of 24)

Signal Name

Ball Interface Group

Page

440GX – Power PC 440GX Embedded Processor

Revision 1.15 – August 30, 2007

Data Sheet

ECC0AB07DDR SDRAM

ECC1AB06ECC2AD06ECC3W07

ECC4U09ECC5AC03ECC6AB04ECC7

AD04EMCCD, EMC1RxErr, GMCGTxClk, GMC0TxClk, TBITxClk, RTBI0TxClk J07Ethernet 51EMCCrS, EMC0CrSDV, GMCTxD7, GMC1TxD3, TBITxD7, RTBI1TxD3K07Ethernet 51EMCMDClk J08Ethernet 51EMCMDIO

L05Ethernet 51EMCRxClk, GMCTxD5, GMC1TxD1, TBITxD5, RTBI1TxD1

J02Ethernet 51

EMCRxD0, EMC0RxD0, EMC0RxD G03Ethernet 51EMCRxD1, EMC0RxD1, EMC1RxD E01EMCRxD2, EMC1RxD0, EMC2RxD,GMCTxD0, GMC0TxD0, TBITxD0,RTBI0TxD0

A07

EMCRxD3, EMC1RxD1, EMC3RxD GMCTxD1, GMC0TxD1, TBITxD1,RTBI0TxD1

H09

EMCRxDV, EMC1CrSDV, GMCTxD4, GMC1TxD0, TBITxD4, RTBI1TxD0K01Ethernet 51EMCRxErr, EMC0RxErr, GMCTxD6, GMC1TxD2, TBITxD6, RTBI1TxD2K03Ethernet 51EMCTxClk, EMCRefClk

J06Ethernet

EMCTxD0, EMC0TxD0, EMC0TxD L09Ethernet 51

EMCTxD1, EMC0TxD1, EMC1TxD K05EMCTxD2, EMC1TxD0, EMC2TxD,GMCTxD2, GMC0TxD2, TBITxD2,RTBI0TxD2

J04

EMCTxD3, EMC1TxD1, EMC3TxD,GMCTxD3, GMC0TxD3, TBITxD3,RTBI0TxD3

J03EMCTxEn, EMC0TxEn, EMCSync L06Ethernet

EMCTxErr, EMC1TxEn, GMCRxClk, GMC0RxClk, TBIRxClk0, RTBI0RxClk

C05

Ethernet 51

Signals Listed Alphabetically (Sheet 3 of 24)

Signal Name

Ball Interface Group

Page