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一位全加器

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity adder is

port(a,b,cin:in std_logic;

co,so:out std_logic);

end adder;

architecture Behavioral of adder is

signal temp1,temp2:std_logic;

begin

temp1<= a xor b;

temp2<= temp1 and cin;

so<= temp1 xor cin;

co<= temp2 OR (a AND b);

end Behavioral;

四位全加器

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter10 is

port(

a,b:in std_logic_vector(3 downto 0);

cin:in std_logic;

co:out std_logic;

so:out std_logic_vector(3 downto 0));

end counter10;

architecture Behavioral of counter10 is

signal carry:std_logic_vector(0 to 2);

component adder

port(

a,b,cin:in std_logic;

co,so: out std_logic);

end component;

begin

u0:adder port map(a(0),b(0),cin,carry(0),so(0));

u1:adder port map(a(1),b(1),carry(0),carry(1),so(1)); u2:adder port map(a(2),b(2),carry(1),carry(2),so(2)); u3:adder port map(a(3),b(3),carry(2),co,so(3));

end Behavioral;

60进制计数器library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter60 is

port(clk, clr, en: in std_logic;

q1,q2: out std_logic_vector(3 downto 0);

co: out std_logic);

end counter60;

architecture Behavioral of counter60 is

signal temp:std_logic;

component counter6

port ( clk, clr, en: in std_logic;

q: out std_logic_vector(3 downto 0);

co:out std_logic);

end component;

component counter10

port ( clk, clr, en: in std_logic;

q: out std_logic_vector(3 downto 0);

co: out std_logic);

end component;

begin

u1:counter10 port map(clk,clr,en,q1,temp);

u2:counter6 port map(temp,clr,en,q2,co);

end Behavioral;

6进制计数器

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter6 is

port(clk, clr, en: in std_logic;

q: out std_logic_vector(3 downto 0);

co:out std_logic);

end counter6;

architecture Behavioral of counter6 is

signal temp: std_logic_vector(3 downto 0);

begin

q(0)<=temp(0);

q(1)<=temp(1);

q(2)<=temp(2);

q(3)<=temp(3);

process(clr, clk, en)

begin

if (clr='0') then

temp<=(others=>'0');

co <= '0';

elsif(clk'event and clk='1') then

if(en='1') then

if(temp="0101") then

co<='1';

temp<="0000";

else temp<=temp+'1';

co<='0';

end if;

end process;

end Behavioral;

6进制计数器

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components. --library UNISIM;

--use UNISIM.VComponents.all;

entity counter10 is

port(clk, clr, en: in std_logic;

q: out std_logic_vector(3 downto 0);

co: out std_logic);

end counter10;

architecture Behavioral of counter10 is

signal temp: std_logic_vector(3 downto 0);

begin

q(0)<=temp(0);

q(1)<=temp(1);

q(2)<=temp(2);

q(3)<=temp(3);

process(clr, clk, en)

begin

if (clr='0') then

temp<=(others=>'0');

co <= '0';

elsif(clk'event and clk='1') then

if(en='1') then

if(temp="1001") then

co<='1';

temp<="0000";

else temp<=temp+'1';

co<='0';

end if;

end process;

end Behavioral;

作业：1、如果输出端口q定义成：q: buffer integer range 3 downto 0;还需要内部信号temp 吗？程序怎样修改？

答：不需要内部信号。程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter10 IS

PORT(

clk,clr,en : IN STD_LOGIC;

q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);

co : OUT STD_LOGIC

);

END counter10;

ARCHITECTURE behav OF counter10 IS

BEGIN

PROCESS(clk,clr,en)

BEGIN

IF(clr='1') THEN

q <= "0000";

ELSE

IF(en='1') THEN

IF(clk'EVENT AND clk='1') THEN

IF(q = "1001") THEN

q <= "0000";

co <= '1';

ELSE

q <= q + 1;

co <= '0';

END IF;

END PROCESS;

END behav;

作业：2、将内部信号temp改成局部变量temp可以吗?程序怎样修改？

答：可以。程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter10 IS

PORT(

clk,clr,en : IN STD_LOGIC;

q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

co : OUT STD_LOGIC

);

END counter10;

ARCHITECTURE behav OF counter10 IS

BEGIN

PROCESS(clk,clr,en)

V ARIABLE temp : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

IF (clr='0') THEN

temp := "0000";

co <= '0';

ELSE

IF (en='1') THEN

IF (clk'EVENT AND clk = '1') THEN

IF (temp = 9) THEN

实验收获：

在这次实验中，第一个实验任务为4位加法器，使用的是元件例化的方法，因时课程刚讲这部分内容，所以没遇到什么困难，可以独立完成。第二个实验任务是设计一个60进制计数器，我采用的是元件例化的方法，初期阶段，6进制计数器和10进制计数器都完成的很好，没有疑问，可是在运用component语句来完成60进制计数器时，出现问题了： 1.在定义输出地参量时，不能使用整体向量型，必须将输出端Q定义为两部分，QH和QL （高四位和低四位）。

2.在vhdl语言设计成功后，使用软件仿真输出波形时输出地波形不能完全正确，输出端Q 总是低电平，后经过和老师程序对比，发现6进制计数器和10进制计数器的程序中进位输出端没有写入一个if语句中，经过修改，输出波形又出新问题了，60进制计数器的进位输出端在初始阶段输出错误，在那之后一直找原因，知道经过同学帮忙才发现，在计数器清零的时候未设置进位输出端，使进位输出端输出低电平。

EDA实验报告

电子0901

刘忠强

20092674