WED3DG644V100D1-M中文资料
WED3DG644V-D1
White Electronic Designs
1White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006 Rev. 3
Pin Front Pin Back Pin Front Pin Back Pin Back Pin Back 1V SS 2V SS 51DQ1452DQ4695DQ2196DQ533DQ04DQ3253DQ1554DQ47
97DQ2298DQ545DQ16DQ3355V SS
56V SSv 99DQ23100DQ557DQ28DQ3457NC 58NC 101V CC 102V CC 9DQ310DQ3559NC 60NC
103A6104A711V CC
12V CC VOLTAGE KEY 105A8106BA013DQ414DQ36107V SS 108V SS 15DQ516DQ37
109A9110BA117DQ618DQ3861CLK062CKE0111A10/AP 112A1119DQ720DQ3963V CC 64V CC 113V CC 114V CC 21V SS 22V SS 65RAS#66CAS#115DQM2116DQM623DQM024DQM467WE#68*CKE1117DQM3118DQM725DQM126DQM569CS0#70*A12119V SS 120VSS 27V CC 28V CC 71*CS1#72*A13121DQ24122DQ5629A030A373DNU 74*CK1123DQ25124DQ5731A132A475V SS 76V SS 125DQ26126DQ5833A234A577NC 78NC
127DQ27128DQ5935V SS
36V SS 79NC 80NC 129V CC 130V CC 37DQ838DQ4081V CC 82V CC 131DQ28132DQ6039DQ940DQ4183DQ1684DQ48133DQ29134DQ6141DQ1042DQ4285DQ1786DQ49135DQ30136DQ6243DQ1144DQ4387DQ1888DQ50
137DQ31138DQ6345V CC
46V CC 89DQ1990DQ51139V SS 140V SS 47DQ1248DQ4491V SS 92V SS 141**SDA 142**SCL 49DQ1350DQ4593DQ2094DQ52
143
V CC
144V CC
32MB – 4Mx64 SDRAM, UNBUFFERED
DESCRIPTION
The WED3DG644V is a 4Mx64 synchronous DRAM module which consists of four 4Mx16 SDRAM components in TSOP II package, and one 2Kb EEPROM in an 8 pin TSOP package for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate.
* This product is subject to change without notice.NOTE: C onsult factory for availability of:
? RoHS compliant products ? Vendor source control options ? Industrial temperature option
FEATURES
PC100 and PC133 compatible Burst Mode Operation
Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page 3.3V ± 0.3V Power Supply 144 Pin SO-DIMM JEDEC
? D1: 27.94 (1.10”)
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
* These pins are not used in this module.** These pins should be NC in the system which does not support SPD.
A0 – A11Address input (Multiplexed)BA0-1Select Bank DQ0-63Data Input/Output CLK0Clock input
CKE0Clock Enable input CS0#Chip select Input RAS#Row Address Strobe CAS#Column Address Strobe WE#Write Enable DQM0-7DQM
V CC Power Supply (3.3V)V SS Ground
*V REF Power supply for reference SDA Serial data I/O SCL Serial clock DNU Do not use NC
No Connect
WED3DG644V-D1
White Electronic Designs
2White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006 Rev. 3
FUNCTIONAL BLOCK DIAGRAM
WED3DG644V-D1
White Electronic Designs
3White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006 Rev. 3
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol Value Units Voltage on any pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V CC supply relative to V SS V CC , V CCQ -1.0 ~ 4.6
V Storage Temperature T STG -55 ~ +150
°C Power Dissipation P D 4 W
Short Circuit Current
I OS
50
mA
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter Symbol Min Typ Max Unit Note
Supply Voltage V CC 3.0 3.3 3.6
V Input High Voltage V IH 2.0 3.0V CCQ+0.3V 1Input Low Voltage V IL -0.3—0.8V 2Output High Voltage V OH 2.4——V I OH = -2mA Output Low Voltage V OL ——0.4V I OL = -2mA
Input Leakage Current
I LI
-10
—
10
μA
3Note: 1. V IH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. V IL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ V CCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T A = 25°C, f = 1MHz, V CC = 3.3V, V REF = 1.4V ± 200mV
Parameter
Symbol Max Unit Input Capacitance (A0-A12)C IN125pF Input Capacitance (RAS#,CAS#,WE#)C IN225pF Input Capacitance (CKE0)C IN325pF Input Capacitance (CLK0)C IN419pF Input Capacitance (CS0#)C IN525pF Input Capacitance (DQM0-DQM7)C IN68pF Input Capacitance (BA0-BA1)
C IN725pF Data Input/Output Capacitance (DQ0-DQ63)
C OUT
10
pF
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V SS = 0V, T A = 0°C to +70°C
WED3DG644V-D1
White Electronic Designs
4White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006
Rev. 3
OPERATING CURRENT CHARACTERISTICS
(V CC = 3.3V, T A = 0°C to +70°C)
Version
Parameter Symbol Conditions 133/100Units Note Operating Current (One bank active)I CC1
Burst Length = 1t RC ≤ t RC (min)I OL = 0mA
300
mA
1
Precharge Standby Current in Power Down Mode I CC2P CKE ≤ V IL (max), t CC = 10ns 4mA
I CC2PS CKE & CLK ≤ V IL (max), t CC = ∞
4Precharge Standby Current in Non-Power Down Mode
I CC2N CKE ≥ V IH (min), CS ≥ V IH (min), tcc =10ns Input signals are charged one time during 2048
mA
I CC2NS CKE ≥ V IH (min), CLK ≥V IL (max), t CC = ∞Input signals are stable 24Active Standby Current in Power-Down Mode I CC3P CKE ≥ V IL (max), t CC = 10ns 8mA
I CC3PS CKE & CLK ≤ V IL (max), t CC = ∞
8Active Standby Current in Non-Power Down Mode
I CC3N
CKE ≥ V IH (min), CS ≥ V IH (min), tcc = 10ns Input signals are changed one time during 20ns 80mA I CC3NS CKE ≥ V IH (min), CLK ≤ V IL (max), tcc = ∞Input signals are stable 40
mA Operating Current (Burst mode)
I CC4
Io = mA Page burst
4 Banks activated t CCD = 2CLK 460mA 1Refresh Current I CC5t RC ≥ t RC (min)360mA 2
Self Refresh Current
I CC6
CKE ≤ 0.2V
4
mA
Notes:1. Measured with outputs open.2. Refresh period is 64ms.
WED3DG644V-D1
White Electronic Designs
5White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006 Rev. 3
AC OPERATING TEST CONDITIONS
V CC = 3.3V ± 0.3V, 0 ≤ T A ≤ 70°C
Parameter
Value Unit AC input levels (V IH /V IL )
2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall time
t R /t F = 1/1ns Output timing measurement reference level
1.4
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol Version Unit Note 7.5, 10Row active to row active delay t RRD (min)15ns 1RAS# to CAS# delay t RCD (min)20ns 1Row precharge time t RP (min)20ns 1Row active time t RAS (min)45ns 1
t RAS (max)100us Row cycle time
t RC (min)65ns 1Last data in to row precharge t RDL (min)2CLK 2Last data in to Active delay t DAL (min) 2 CLK + t RP
—Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stop t BDL (min)1CLK 2Col. address to col. address delay t CCD (min)
1CLK 3Number of valid output data
CAS latency=32ea
4CAS latency=2
1
Notes :1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.
WED3DG644V-D1
White Electronic Designs
6White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006 Rev. 3
PACKAGE DIMENSIONS FOR D1
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
ORDERING INFORMATION FOR D1
Part Number
Clock Speed CAS Latency
Height*WED3DG644V10D1x-xx 100MHz CL=227.94 (1.100”)WED3DG644V7D1x-xx 133MHz CL=227.94 (1.100”)WED3DG644V75D1x-xx
133MHz
CL=3
27.94 (1.100”)
NOTES: ? Consult Factory for availability of RoHS products. (G = RoHS Compliant) ? V endor speci ? c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is
to be replaced with the respective vendors code. Consult factory for quali ? ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
? Consult factory for availability of industrial temperature (-40°C to 85°C) option
WED3DG644V-D1
White Electronic Designs
7White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006 Rev. 3
PART NUMBERING GUIDE
WED 3 D G 64 4 V xxx D1 x -x G
WEDC
MEMORY (SDRAM)
SDRAM GOLD DEPTH x64DENSITY 3.3 Volts
CLOCK SPEED (MHz)
PACKAGE D1 = 144 PIN SO-DIMM
INDUSTRIAL TEMP OPTION (For commercial leave "blank"
for industrial add "I") COMPONENT VENDOR NAME
(M = Micron)(S = Samsung)
G = RoHS COMPLIANT (For non-compliant "blank"
for RoHS add “G”)
WED3DG644V-D1
White Electronic Designs
8White Electronic Designs Corporation ? (602) 437-1520 ? https://www.wendangku.net/doc/4b14549728.html,
June 2006 Rev. 3
Document Title
32MB – 4Mx64 SDRAM, UNBUFFERED DRAM DIE OPTIONS:? SAMSUNG: K-Die ? MICRON: Y14W:G
Revision History Rev #
History
Release Date
Status
Rev A Created
11-15-01Advanced Rev 0Changed from Advanced to Final 9-6-02Final Rev 1Updated CAP and I DD specs
6-04Final Rev 2
2.1 Added RoHS and lead-free notes
2.2 Added vendor source and industrial tem notes 2.3 Added part number matrix
1-06
Final
Rev 3 3.1 Updated part number guide
3.2 Updated “ordering information” part number 3.3 Added DRAM die options
6-06Final