Automated combination of simulation and hardware prototyping

Automated Combination of Simulation and Hardware Prototyping

Tero Rissa and Wayne Luk

Department of Computing,Imperial College London

180Queen’s Gate,London SW72BZ,England

{tpr,w.luk}@https://www.wendangku.net/doc/4316223293.html,

Peter Y.K.Cheung

Department of Electrical and Electronic Engineering,Imperial College London

Exhibition Road,London SW72BT,England

p.cheung@https://www.wendangku.net/doc/4316223293.html,

Abstract

This paper presents Inter Sim,a design method that automates the combination of software simulation and hardware prototyping for application development tar-geting platforms based on recon?gurable hardware. The main idea of Inter Sim is to enable simulation of the module under development in software,while the inputs and outputs of that module are connected to other hardware elements in its common opera-tional environment.Interface modules,with appro-priate storage and protocol facilities,are automati-cally inserted in the system to provide the Inter Sim hardware-software interface.This approach offers fast design time without the need to execute repeatedly time-consuming FPGA backend tools such as place and route,full visibility and controllability of the in-ternal signals,simulation in the module’s true hard-ware/software environment,and support for hardware design and veri?cation facilities.An example of In-ter Sim,called Sonic Sim,has been developed for the UltraSONIC recon?gurable computer.It is shown that Sonic Sim can reduce design time to seconds,while tra-ditional tool?ow can take minutes or hours. Keywords:Veri?cation of complex systems,hard-ware/software co-design,recon?gurable hardware rapid prototyping,platform-based design,design methodologies and tools.1Introduction

The increasing complexity of digital system design has motivated researchers and practitioners to search for novel methods to develop and verify large designs.

A promising approach is platform-based design,where hardware and software elements and tools are struc-tured to promote re-use for different designs[8,11]. An essential idea in platform-based design is the clear separation of computation and communication.This separation enables the approach presented in this pa-per to provide transparent communication sockets be-tween prototyping hardware and software simulation environment.This facilitates the automated adaptation of the proposed design method for different hardware platforms.

The solution proposed in this paper aims to alleviate the following system-level veri?cation problems.?Simulation of large and complex systems is pro-hibitively slow.

?It is dif?cult to make simulation test-bench to match real environment.

?Hardware prototyping is time-consuming,as FPGA back-end tools must be run every time the design changes.

?In hardware prototyping,the visibility to internal signals inside an FPGA is limited.

The main contributions of this paper are:

?Inter Sim,a design model that provides a trans-parent interface between the prototyping and the development environment.The bene?ts of this interface are:

1.automated adaptation for a hardware plat-

form,

2.fast design cycle as FPGA implementation

?ow is not required,

3.full visibility of the internal signals,

4.veri?cation of the design under develop-

ment in its operational environment,

5.considerably faster veri?cation time than

simulation,since the environmental signals

are computed in hardware.

?Sonic Sim,an Inter Sim implementation for the Ul-traSONIC recon?gurable computer,demonstrat-ing the concept on an existing platform.Sonic Sim illustrates the feasibility of our approach,and shows real bene?ts in developing and verifying video and imaging applications.

The rest of the paper is organised as follows.Sec-tion2explains the problems involved in recon?gurable hardware/software platform application development, and looks into previous research and tools.Section3 introduces the Inter Sim design model,and Section4 covers the associated design?ow which contains three phases.Section5outlines the UltraSONIC platform, and Section6describes the Sonic Sim implementation. Section7presents the results,while Section8con-cludes the paper.

2Background

Currently there are two common approaches for re-con?gurable hardware/software platform application development:software simulation and hardware pro-totyping.

The?rst approach for application development in-volves software simulation,whose strength includes providing full visibility of the internal signals for the Module Under Development(MUD).There are,how-ever,signi?cant dif?culties with simulation-based de-sign veri?cation,which go beyond the speed of the simulation.When the target is a hardware/software platform,it is usually dif?cult to test the MUD in a realistic https://www.wendangku.net/doc/4316223293.html,ually the platform contains hardware and software elements whose behaviour is not entirely known,and therefore cannot be included in the simulation.Hence it can be dif?cult to generate test vectors for,and interpret the results of,simulating the MUD in isolation from the rest of the system.

Even if the simulation of the environmental com-ponents is possible,simulation time of the full sys-tem would be impractically long,even with a costly hardware emulation system to accelerate simulation. Many researchers have reported that software simula-tion alone does not present an acceptable alternative for large and complex designs,because of the long simulation times that can range from hours to even days[3,9,14].

The second approach involves hardware prototyp-ing,whose strength includes examining the behaviour of the MUD in a realistic operational environment. However,visibility may be limited to physical meth-ods,such as logic analyser probing.This is a major drawback:when a module does not meet the intended functionality,there is often little information to diag-nose the fault.The situation is aggravated by the fact that current Chip Scale Packaging technology does not allow insertion of physical probes,as the pins are hid-den under the device.Considerable amount of research has been done in order to solve the hardware visibility problem[5,17,18].

Our proposed approach,Inter Sim,differs from the aforementioned techniques in that in Inter Sim the MUD can be observed in a realistic environment,with data supplied by other hardware and software ele-ments.The MUD goes through the FPGA implemen-tation?ow only once,as long as the MUD interface remains unchanged.There is no need to run FPGA implementation tools during the design iterations,so the design time is signi?cantly reduced.In contrast, much of the previous work involves putting the design through place and route every time the module func-tionality is changed.One method to shorten design time is to use Xilinx Modular Design Flow[19],which allows the design to be partitioned into smaller blocks for separate implementation.However this method still suffers from some of the drawbacks discussed above.

Figure1.Original design.‘MUD’stands for‘Module Under Development’.

Figure2.Transformed design with Inter Sim module interfaces.

To summarise,the proposed method differs from existing commercial emulation and other simulation acceleration techniques,such as those provided by Axis Systems[1,2]and Mentor Graphics Corporation [12],in the following:

1.Inter Sim does not impose additional costs besides

data storage,while in emulation systems substan-tial overheads can be involved;

2.Inter Sim connects seamlessly to the rest of the

system,such as embedded processors and I/O de-vices;

3.Inter Sim does not require time-consuming FPGA

implementation tools to run after changes in the MUD;

4.Inter Sim veri?cation receives interface signals

from the real environment of the design under development,facilitating a realistic estimation of the hardware resource requirements,execution speed,power consumption and other metrics.

Several commercial tools have been developed to assist design veri?cation.Such tools include Cadence Incisive[4],Mentor Graphics Seamless[13],and Xil-inx System Generator[20].In Inter Sim,with its platform-speci?c interface and components,simula-tion and hardware prototyping can be effectively com-bined without requiring additional tools in the design ?ow.By giving clear limits about what the designer and the tool can and cannot do,Inter Sim narrows its generality but makes it easy and ef?cient to use.

The Inter Sim interface is designed to follow that of the MUD as closely as possible,including driving all outputs.Some previous work aims only to add signal visibility,without output driving capabilities.While researchers have studied application frameworks[15], we are not aware of any automated and ef?cient method which operates in a similar way to Inter Sim.

3Inter Sim Design Model

The main idea of the Inter Sim design model is that the MUD is simulated in software,while everything else in the system is executed in the actual implemen-tation media which can include recon?gurable hard-ware,the host computer,embedded processors,or Digital Signal Processors.To enable this approach,In-ter Sim interface modules are automatically inserted in the system as illustrated in Fig.1and Fig.2.

The core of the Inter Sim approach consists of four interface modules,shown in Fig.2.The Record and Playback modules reproduce the communication inter-face of the MUD to the rest of the system in hardware. Similarly,the Source and Sink modules reproduce the communication interface of the MUD to the develop-ment environment running in software.

The Record and Source modules handle the incom-ing data channels of the MUD,while the Playback and Sink modules handle the outgoing data channels of the MUD.The hardware/software interface is managed by the Inter Sim modules,thus from the system view,the MUD appears directly connected to the rest of the sys-tem as shown in Fig.1.

In addition to the MUD interfaces,all the hard-ware modules are required to buffer enough data to guarantee the integrity of the communication proto-col.The memory requirement greatly depends on the application and the protocol.Depending on the hard-ware/software interface it might also be necessary to buffer data on the host managing the simulation envi-ronment.However,this is rarely the case as the simu-lation environment has greater control to the commu-nication protocol than the hardware modules.For ex-ample,the simulation environment can pause the sim-ulation in order to wait to new data to arrive.

Inter Sim modules are customised to meet the re-quirements of the application communication model, the platform and the interface to the host in order to maintain the transparency of the interface.The gener-ation of the modules can be fully automated,as illus-trated in the Sonic Sim implementation example in Sec-tion5.Here,the separation of computation and com-munication in platform-based design approach plays an important role.Without this separation,the auto-mated creation of MUD independent modules would be signi?cantly harder.Inter Sim modules for different platforms,communication methods and hardware de-velopment environment are collected into the System Database as illustrated in Fig.3.By using this library, the migration from one platform and/or simulation en-vironment to another can be further automated by the Inter Sim Organiser.

The Inter Sim design model places requirements on the communication model between the MUD and the rest of the system,and to the timing behaviour of the MUD.These requirements are necessary to keep In-ter Sim modules transparent to the rest of the system.

Because no assumptions about the duration of the simulation can be made,this timing behaviour must be passed to the MUD in one form or another.For modules using two-way handshaking or other blocking communication method,this requirement can be met by not releasing the incoming communication channel until the simulation is over.In some cases,for example in video stream processing,this is not possible since usually the data stream cannot be stopped,which is the case with the Sonic Sim example in Section5.

In the case of Sonic Sim,another method to meet the requirement has to be found:the simulation is carried out a full frame at a time.In this way,the stream tim-ing(peak throughput)is kept but the latency does not correspond to the module’s real latency.This approach has the drawback of requiring suf?cient memory re-sources to store the full frame.For real-life video ap-plications,external memory must be used,as a frame usually requires more memory than the available on-chip storage in current FPGAs.

All communication between the MUD and the rest of the system must happen through Inter Sim modules. This affects the MUD partitioning,and in some cases it is necessary to include components like external memory in the simulation to achieve practical Inter Sim communication.In addition,hardware resources must be allocated for buffering of data in order to allow In-ter Sim hardware modules to operate transparently.

4Inter Sim Design Flow

The design?ow for Inter Sim,shown in Fig.3,con-tains three phases:the Pre-Design Phase,the Design Iteration Phase,and the Post-Design Phase.Section6 will illustrate the realisation of these phases in the case of Sonic Sim.

Figure3.Design?ow with Inter Sim.

4.1Pre-Design Phase

The design?ow is started by de?ning the interface of a MUD and the conditions for Inter Sim commu-nication.These conditions include the start and stop clauses for Inter Sim operation,and the handshaking between Inter Sim hardware modules and the software host modules.The Inter Sim Record module is con-nected to the inputs of the MUD,and Inter Sim Play-back module is connected to its outputs.The MUD is itself wrapped in a testbench,where its inputs are driven by the Inter Sim Source module and its outputs drives the Inter Sim Sink module(Fig.2).

The design?ow continues with the FPGA imple-mentation of the Inter Sim hardware modules,together with the other hardware modules that locate in the same FPGA.Note that the MUD itself does not go through the FPGA implementation?ow,unlike the rest of the hardware components.The steps in the Pre-Design Phase need to be taken only once in the begin-ning of a new MUD speci?cation,and when the MUD interface or the conditions of Inter Sim communication are changed.

4.2Design Iteration Phase

The Design Iteration Phase is the MUD develop-ment phase.When the system is executed,the MUD functionality is simulated in a hardware simulator run-ning in software.Therefore when changes are made to the MUD,there is no need to go through the FPGA implementation?ow,which signi?cantly reduces the design time.As the MUD is connected transparently to the system,it is executed in its real environment and the results can be observed directly from system be-haviour.

The simulation environment gives full visibility to the internal signals of the MUD,which would other-wise be laborious or impossible to observe.In addi-tion,the MUD can be used as part of the system be-fore developing a bit-accurate model,as long as the interface requirements can be satis?ed.This means that the MUD can be modelled by using a suitable lan-guage,which can range from Java,C++with SystemC libraries to legacy DSP assembler code.Naturally,be-fore entering the Post-Design Phase a synthesisable model must be implemented.

In some cases the MUD timing analysis requires technology mapping and/or placement and routing in-formation for accurate simulation.This requires addi-tional steps to be taken in the Design Iteration Phase, thus increasing the design time.However,the other bene?ts of Inter Sim still remain.This is particularly useful when the MUD functionality meets the func-tional requirements,but fails to operate in the actual hardware.

4.3Post-Design Phase

When the requirements in module functionality has been met,the Inter Sim hardware modules are replaced with the MUD.Now the complete system can be implemented and executed in the target medium,as shown in Fig.1.

The next section describes the UltraSONIC system. The implementation of Inter Sim for this system,called Sonic Sim,will be presented in Section6.

5UltraSONIC

UltraSONIC is a second generation implementa-tion of the SONIC recon?gurable computing platform [6,7].The SONIC platform concept is designed to meet the high-throughput and high-computation de-mand of real-time video applications.Fig.4illus-trates the overall UltraSONIC https://www.wendangku.net/doc/4316223293.html,pu-tation in UltraSONIC is performed in Plug In Pro-

Figure4.The UltraSONIC architecture and the UltraPIPE architecture.

cessing Elements(PIPEs).The PIPEs are connected to each other and to the Local Bus Controller(LBC) with three busses that are optimised for streaming video data.The PIPEFlow(PF)bus is the main I/O channel to each pipe from the PC host.PIPEFlow Chain(PFC)provides a PIPEFlow input(PIPEFlow Left)and output(PIPEFlow Right)to the next PIPE in the chain.This connection scheme provides an ef?-cient way of pipelining the tasks between PIPEs.The Global PIPEFlow(GPF)bus can be used to broadcast data between the PIPEs and the LBC.In addition to the PIPEFlow busses,there are a set of control signals and system busses.The well-de?ned PIPE communi-cation protocol makes possible the independent PIPE development and integration.

The UltraSONIC platform de?nes the PIPEFlow bus topology and streaming protocol.When comply-ing with these,the PIPEs can be implemented https://www.wendangku.net/doc/4316223293.html,mon types of pipes are I/O pipes(for example Serial Digital Interface PIPE)and processing pipes.Sonic Sim is targeted to a recon?gurable pro-cessing PIPE called an UltraPIPE,illustrated on the right in Fig.4.An UltraPIPE contains four parts:PIPE Router(PR),PIPE Memory(PM),PIPE Engine(PE), and PIPE Engine Registers(PE Reg).The PR han-dles the data formatting,memory access arbitration, and the data movement between the PIPE components and in and out of the PIPE.The PM is an external memory designed for fast access of image data in par-allel with the PIPEFlow data.There is suf?cient mem-ory for buffering up to two frames of HDTV video data.All the user-de?ned computation is performed inside the PE.Image data streams from PIPE to PIPE through the PIPEFlow buses.Additionally data can be passed between the PIPE and the host via the memory mapped PE Reg.The components PE,PR and PE Regs in Fig.4are implemented on a Xilinx Virtex1000E FPGA.

The clear separation of the communication(PR)and computation(PE)facilitates design reuse,as the user-de?ned computation modules can be developed sepa-rately from the data?ow.Thus the same core designs can be re-used independently of the UltraSONIC setup and con?guration.

The UltraSONIC Application Programming Inter-face(API)is used to communicate between the host computer and the UltraSONIC.The API functions in-clude FPGA con?guration,PR control,and PE Reg and PM interface commands.This API is used for Sonic Sim hardware-host software communication,and therefore no additional I/O is required.

6Sonic Sim Implementation

Sonic Sim is an example implementation of Inter Sim for the UltraSONIC recon?gurable computer.We shall ?rst describe some operational constraints associated with UltraSONIC.Then we show how Sonic Sim sup-ports the three phases in the design?ow for Inter Sim on the UltraSONIC platform.

Figure5.Sonic Sim Pre-Design Phase.

6.1Constraints

The UltraSONIC streaming protocol does not per-mit halting the stream in the middle of a frame.In order to meet the Inter Sim timing requirements,the Sonic Sim module communications can only occur be-tween frames.In addition,the upstream PIPE or host must wait for the downstream PIPE to?nish the pro-cessing before starting to send a new image,or the tim-ing requirement will be violated.Furthermore,there needs to be suf?cient memory allocated for Sonic Sim to store the internal data.

Since UltraSONIC host interface allows data to be read directly from the hardware to the simulation en-vironment,no frame buffering in the host is required. However,it is necessary for Sonic Sim record and play-back to store a full frame,so PIPE memory banks must be used.Fortunately they can share the same memory area,as the incoming frame can be overwritten after MUD processing.Still,the storage for Sonic Sim re-duces the memory available for the application on the UltraPIPE.There are two main solutions.The?rst is to allocate another PIPE for Sonic Sim operation.This method must be used when the application occupies all the available memory ports.The second is to re-duce image resolution during the design phase to leave enough memory for Sonic Sim.This solution is found to be adequate for the majority of our applications, as using images with reduced resolution also reduces simulation time,but rarely masks design errors.

Figure6.Sonic Sim Design Iteration Phase. 6.2Pre-Design Phase

The streaming format is dictated by the PIPEFlow protocol,thus the start and stop conditions for Sonic Sim modules are?xed to the beginning and end of an image.Hence the user only needs to specify the MUD HDL(Hardware description Language)com-ponent name and the memory locations of Sonic Sim PIPE Engine Registers for the Sonic Sim Organiser. The required?les for Inter Sim Pre-Design Phase are then automatically generated.

This process is illustrated in Fig.5.The Sonic Sim Organiser replaces the MUD component instantia-tion with Sonic Sim Recorder and Playback modules; these Inter Sim modules are speci?c to UltraSONIC. Their hardware implementation for a single PIPEFlow stream MUD takes only44FPGA Slices,which cor-responds to0.4%for an XCV1000E device.The Sonic Sim Organiser also generates a testbench which wraps the MUD to form a VHDL simulation testbench, which connects Sonic Sim host components,the Source and Sink modules,to the MUD(Fig.2).The Sonic Sim Host Con?guration File delivers the interface infor-mation to the Sonic Sim Host that controls the Ultra-SONIC during the Design Iteration Phase.

6.3Design Iteration Phase

The Design Iteration Phase for Sonic Sim is illus-trated in Fig.6.The wrapped MUD HDL testbench is simulated in Model Technology’s ModelSim HDL

simulator.The Sonic Sim Host,comprising Source and Sink modules,is implemented using ModelSim’s For-eign Language Interface(FLI).The Host directly com-municates with the Sonic Sim Record and Playback modules through the UltraSONIC API.The handshak-ing between Sonic Sim hardware and software mod-ules is implemented using PE Registers.The memory mapped locations of these registers are de?ned by the user in the Pre-Design Phase,and delivered to the host in the host con?guration?le.

When the testbench is elaborated in ModelSim,the Sonic Sim Host con?gures the target UltraPIPE us-ing the con?guration bitstream from the Pre-Design Phase.A video frame is processed in three steps.

1.The design is run in UltraSONIC until Sonic Sim

Record has received a full frame of data and stored it to memory.After this it signals the Sonic Sim Host.

2.When signaled,the Sonic Sim Host drives the in-

puts of the MUD with the data in the memory by using Sonic Sim Source FLI process.At the same time,the Sonic Sim Sink process writes the out-puts of the MUD back to the UltraSONIC mem-ory.When the full frame has been simulated,the Sonic Sim Host signals Sonic Sim Playback.

3.The Sonic Sim Playback reads the data from the

memory and reconstructs the PIPEFlow stream.

After streaming of the full frame,Sonic Sim is ready to begin receiving a new frame and the cy-cle repeats for the next frame.

6.4Post-Design Phase

In the Post-Design Phase,the Sonic Sim Organiser is used to remove the Sonic Sim Record and Playback modules,and re-instantiate the MUD to the PIPE En-gine Design.This phase is fully automated by the Sonic Sim Organiser.

7Results

This section contains results involving Sonic Sim,an implementation of Inter Sim for the UltraSONIC plat-form described in the preceding section.

First,recall that the MUD is not changed in any way for Sonic Sim–it is merely wrapped by the Sonic Sim testbench.The MUD can be simulated and debugged exactly as any HDL design in ModelSim by using all the available features,including break pointing and waveform analysis of the internal signals.The numeric results presented here are speci?c to ModelSim and are for guidelines only.It should be noted that Sonic Sim is not ModelSim-speci?c,and any simulation environ-ment with a C-interface can be used.

When the MUD description is changed,only the MUD HDL description needs to be recompiled in ModelSim.Even for large modules,this take at a most few seconds.This compares favourably to minutes or hours of running back-end FPGA implementation tools,such as place and route.

The MUD simulation time depends on the image resolution(amount of data)and the MUD complexity. For a pass-through design,the processing rate in a dual AMD Athlon at2GHz with2GB of memory is about 50K pixels per second.A200by250video stream can be processed with the maximum speed of one frame per second.The pass-through design gives the Sonic Sim overhead in simulation.Beyond the over-head,the simulation time depends on the simulation environment,MUD complexity,and the image size.

Table1illustrates selected experimental simulation performance?gures with ModelSim SE PLUS5.7d running in the setup above.In this table,the Log col-umn shows whether signals were logged for analysis during the simulation.Logging of the signals enables analysis of past events,but it is slower due to increase in disk operations.As a rough complexity metric,the number of memory accesses to Xilinx CoreGen Block-RAM VHDL simulation models and the number of bits evaluated by the simulator per pixel are given re-spectively in the Mem and Bit ops columns.Invert Colours represents the simplest design beyond Pass Through,where the colour bits gets inverted.3x3Con-volution is a design with a scanline buffer of2rows of 1024pixels in a VHDL model of Xilinx CoreGen Du-alport SRAM,and a3x3Convolution?lter.The?gure of about6000pixels per second represents the worst case scenario,as more complex designs rarely need to be isolated from hardware execution to the simulation.

Matrix3is a demonstration application entirely in simulation.This application contains a2-Way3x3 Convolution in the form of a Sobel Edge Detector,a Texture Mapper and an Output Combiner.The ap-

Table1.Example Simulation Performance.

Module Log Pixels/s Mem Bit ops Pass Through No50070080 Pass Through with stand-alone TB No19750080 Invert Colours No475000102 Invert Colours Yes450840102 RGB2YUV Conversion No2790801347 3x3Windowing No1261031405 3x3Convolution No637833565 Texture Mapper No134042723 Output Combiner No173712619 2-Way3x3Convolution No269536227 Matrix3No86777872 Matrix3Yes85677872

plication occupies18%of the Slices and33%of the Block RAMs of a XCV1000E FPGA.The design in-cludes7memory access per pixel and has a28-stage pipeline for processing.The processing rate of around 850pixels per second illustrates that it is important to be able to simulate parts of the design,and to execute as much as possible in hardware.

In a large number of designs,a single frame is suf-?cient to determine whether the MUD has the desired functionality.Therefore,the full design cycle often takes only a few seconds.

The use of Sonic Sim requires a UltraSONIC plat-form with the desired con?guration during module development.Since this is sometimes not possible, the Sonic Sim Host can be used to generate a stand-alone testbench for off-line development.The test-bench is generated according to the data received by the Sonic Sim Record.However,this testbench can only be used for driving the inputs of the design and the outputs must be interpreted by the user.The test-bench must also be regenerated whenever the input data are changed.Because of the increased?le I/O, the maximum simulation speed is reduced to about20 000pixels per second with the same con?guration as above.Hence the stand-alone testbench is not the best choice for full-resolution video streams because of the ?le size requirements and the reduced performance. However,it has been found useful for development with still images.8Summary

This paper presents the Inter Sim design model and a platform speci?c implementation–Sonic Sim for the UltraSONIC recon?gurable computing platform.It is shown that by using a relatively simple platform-speci?c approach,the adaptation of the method can be automated for a particular hardware platform.The two key features of Inter Sim for design validation are: (a)a fast design iteration cycle,and(b)the capability of validating design components in their operational environment.In particular,the design and veri?cation time of a recon?gurable hardware module can be sig-ni?cantly reduced,due to:

1.full visibility of the internal signals of the module

in software,

2.a design cycle where time-consuming stages in

the FPGA implementation?ow is not required, 3.the environment of the module under develop-

ment remains in real hardware.

Current and future work includes extension of the In-ter Sim approach to support other platforms,applica-tions and design environments,such as those based on the SystemC and Handel-C languages[16].It is also useful to explore an integrated framework comprising software simulation,hardware prototyping and formal veri?cation,which would be attractive for design qual-i?cation[10].

Acknowledgements.We thank Dr.Adam Donlin,Xil-inx,inc.,for his valuable comments and suggestions. The support of the Nokia Foundation,the Finnish Cul-tural Foundation,Xilinx,Inc.,and the UK Engineering and Physical Sciences Research Council(Grant num-ber GR/N66599,GR/R31409and GR/R55931)is gratefully acknowledged.

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2003.

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