当前位置：文档库 › ADS5483IRGCT;ADS5483IRGCR;中文规格书,Datasheet资料

ADS5483IRGCT;ADS5483IRGCR;中文规格书,Datasheet资料

f I?Input Frequency?MHz

100

020406080100120140

G068

f I?Input Frequency?MHz

020406080100120140

G069

ADS5481

ADS5482

ADS5483 https://www.wendangku.net/doc/4516249082.html,.....................................................................................................................................................SLAS565C–JUNE2008–REVISED OCTOBER2009 16-Bit,80/105/135-MSPS Analog-to-Digital Converters

Check for Samples:ADS5481ADS5482ADS5483

FEATURES APPLICATIONS

?Wireless Infrastructure(Multi-Carrier GSM,?80/105/135-MSPS Sample Rates

WCDMA,LTE)

?16-Bit Resolution

?Test and Measurement Instrumentation ?SFDR:95dBc at70MHz and135MSPS

?Software-Defined Radio

?SNR:78.6dBFS at70MHz and135MSPS

?Data Acquisition

?Efficient DDR LVDS-Compatible Outputs

?Power Amplifier Linearization

?Internal Dither Available?Communication Instrumentation

?Total Power Dissipation:2.2W?Radar

?Power-Down Mode:70mW?Medical Imaging

?On-Chip High Impedance Analog Buffer

?QFN-64PowerPAD?Package

(9mm×9mm Footprint)

?Industrial Temperature Range:

–40°C to+85°C

DESCRIPTION

The ADS5481/ADS5482/ADS5483(ADS548x)is a16-bit family of analog-to-digital converters(ADCs)that operate from both a5-V supply and3.3-V supply while providing LVDS-compatible digital outputs.The ADS548x integrated analog input buffer isolates the internal switching of the onboard track and hold(T&H)from disturbing the signal source while providing a high-impedance input.An internal reference generator is also provided to simplify the system design.

Designed for highest total ENOB,the ADS548x family has outstanding low noise performance and spurious-free dynamic range.

The ADS548x is available in an QFN-64PowerPAD package.The device is built on Texas Instruments complementary bipolar process(BiCom3)and is specified over the full industrial temperature range(–40°C to +85°C).

SFDR SNR

vs vs

INPUT FREQUENCY INPUT FREQUENCY

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.Copyright?2008–2009,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

ADS5481

ADS5482

ADS5483

SLAS565C–JUNE2008–REVISED https://www.wendangku.net/doc/4516249082.html,

This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Table1.PACKAGE/ORDERING INFORMATION(1)

SPECIFIED

PACKAGE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD TEMPERATURE

DESIGNATOR MARKING NUMBER MEDIA,QUANTITY

RANGE

ADS5481IRGCT Tape and Reel,250 ADS5481QFN-64RGC–40°C to+85°C AZ5481

ADS5481IRGCR Tape and Reel,2000

ADS5482IRGCT Tape and Reel,250 ADS5482QFN-64RGC–40°C to+85°C AZ5482

ADS5482IRGCR Tape and Reel,2000

ADS5483IRGCT Tape and Reel,250 ADS5483QFN-64RGC–40°C to+85°C AZ5483

ADS5483IRGCR Tape and Reel,2000 (1)For the most current product and ordering information see the Package Option Addendum located at the end of this document,or see

the TI website at https://www.wendangku.net/doc/4516249082.html,..

2Submit Documentation Feedback Copyright?2008–2009,Texas Instruments Incorporated

ADS5481

ADS5482

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range,unless otherwise noted.

ADS5481,ADS5482,ADS5483UNIT AVDD5to GND6V Supply voltage AVDD3to GND5V DVDD3to GND5V

AC signal.Valid when AVDD5is within normal operating range.When

AVDD5is off,analog inputs should be<0.5V.If not,the protection

Analog input to GND diode between the inputs and AVDD5will become forward-biased and–0.3to(AVDD5+0.3)V could be damaged or shorten device lifetime(see Figure60).Short

transient conditions during power on/off are not a concern.

Analog INP to INM DC signal±4V Valid when AVDD3is within normal operating range.When AVDD3is

off,clock inputs should be<0.5V.If not,the protection diode between

Clock input to GND the inputs and AVDD3will become forward-biased and could be–0.3to(AVDD3+0.3)V damaged or shorten device lifetime(see Figure67).Short transient

conditions during power on/off are not a concern.

CLKP to CLKM±2.5V Digital data output to GND–0.3to(DVDD3+0.3)V Digital data output plus-to-minus±1V Operating temperature range–40to+85°C Maximum junction temperature+150°C Storage temperature range–65to+150°C ESD,human-body model(HBM)2kV (1)Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periods may

degrade device reliability.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those specified is not implied.Kirkendall voidings and current density information for calculation of expected lifetime are available upon request.

THERMAL CHARACTERISTICS(1)

PARAMETER TEST CONDITIONS TYP UNIT Soldered thermal pad,no airflow20 RθJA

Soldered thermal pad,150-LFM airflow16

°C/W RθJC thermal resistance from the junction to the package case(top)7

RθJP thermal resistance from the junction to the thermal pad(bottom)0.2

(1)Using49thermal vias(7×7array).See PowerPAD Package in the Application Information section.

ADS5481

ADS5482

ADS5483

SLAS565C–JUNE2008–REVISED https://www.wendangku.net/doc/4516249082.html, RECOMMENDED OPERATING CONDITIONS

ADS5481,ADS5482,

ADS5483UNIT

MIN TYP MAX

SUPPLIES

AVDD5Analog supply voltage 4.755 5.25V

AVDD3Analog supply voltage 3.1 3.3 3.6V

DVDD3Output driver supply voltage3 3.3 3.6V

ANALOG INPUT

Differential input range3V PP

VCM Input common mode 3.1V

DIGITAL OUTPUT(DRY,DATA)

Maximum differential output load(parasitic or intentional)5pF

Differential output resistance100?

CLOCK INPUT(CLK)

Max CLK input sample rate(sine wave)10Rated MSPS

Clock

Clock amplitude,differential sine wave(see Figure69) 1.55V PP

Clock duty cycle(see Figure74)455055%

T A Operating free-air temperature–40+85°C ELECTRICAL CHARACTERISTICS(ADS5481,ADS5482,ADS5483)

Typical values at T A=+25°C:minimum and maximum values over full temperature range T MIN=–40°C to T MAX=+85°C, sampling rate=max rated,50%clock duty cycle,AVDD5=5V,AVDD3=3.3V,DVDD3=3.3V,–1dBFS differential input, and3-V PP differential clock,unless otherwise noted.

ADS5481ADS5482ADS5483 PARAMETER TEST CONDITIONS UNIT

MIN TYP MAX MIN TYP MAX MIN TYP MAX

Clock rate80105135MSPS

Resolution161616Bits

ANALOG INPUTS

Differential input range333V PP

Analog input common-mode Self-biased;see VCM

3.1 3.1 3.1V

voltage specification below

Input resistance(dc)Each input to VCM100010001000?

Each input to GND

Input capacitance 3.5 3.5 3.5pF

(including package)

Analog input bandwidth

125125485MHz (–3dB)

Common-mode signal

CMRR Common-mode rejection ratio656565dB

70MHz(see Figure56)

INTERNAL REFERENCE VOLTAGE

VREF Reference voltage 1.2 1.2 1.2V

Analog input common-mode With internal voltage

VCM3 3.15 3.353 3.15 3.353 3.15 3.35V voltage reference output reference

VCM temperature coefficient-1-1-1mV/°C

4Submit Documentation Feedback Copyright?2008–2009,Texas Instruments Incorporated

ADS5481

ADS5482

ADS5483 https://www.wendangku.net/doc/4516249082.html,.....................................................................................................................................................SLAS565C–JUNE2008–REVISED OCTOBER2009 ELECTRICAL CHARACTERISTICS(ADS5481,ADS5482,ADS5483)(continued)

ADS5481ADS5482ADS5483 PARAMETER TEST CONDITIONS UNIT

MIN TYP MAX MIN TYP MAX MIN TYP MAX

DYNAMIC ACCURACY

No missing codes,

DNL Differential linearity error-0.99±0.5 1.0-0.99±0.5 1.0-0.99±0.5 1.0LSB

f IN=30MHz

INL Integral linearity error f IN=30MHz-10±3+10-10±3+10-10±3+10LSB

Offset error-1515-1515-1515mV

Offset temperature coefficient-0.02-0.02-0.02mV/°C

Gain error-6±26-6±26-6±26%FS

Gain temperature coefficient-0.01-0.01-0.01mV/°C

POWER SUPPLY

I AVDD55-V analog316330316330317330mA

V IN=full-scale,

I AVDD3 3.3-V analog131150131150133150mA

f IN=30MHz,

f S=Max rated,Normal

I DVDD3 3.3-V digital/LVDS606560656065mA

operation

Total power dissipation 2.15 2.35 2.15 2.35 2.2 2.35W

I AVDD55-V analog989898mA

I AVDD3 3.3-V analog353535mA

Light sleep mode

(PDWNF=H,PDWNS=L)

I DVDD3 3.3-V digital/LVDS0.070.070.07mA

Total power dissipation605680680680605680mW

I AVDD55-V analog131313mA

I AVDD3 3.3-V analog222mA

Deep sleep mode

(PDWNF=L,PDWNS=H)

I DVDD3 3.3-V digital/LVDS0.070.070.07mA

Total power dissipation701007010070100mW

Fast wakeup time(light sleep)From PDWNF disabled600600600μS

Slow wakeup time(deep From PDWNS disabled

666mS sleep)

AVDD5supply Power-supply rejection ratio,606060dB

Without0.1-μF board supply

AVDD3supply808080dB PSRR capacitors,with1-MHz

supply noise(see

DVDD3supply959595dB

Figure76)

DYNAMIC AC CHARACTERISTICS

f IN=10MHz8180.879

f IN=30MHz78.480.678.480.77679

SNR Signal-to-noise ratio f IN=70MHz80.180.178.6dBFS

f IN=100MHz79.68078.2

f IN=130MHz77.8

f IN=10MHz989897

f IN=30MHz879787988697

SFDR Spurious-free dynamic range f IN=70MHz939195dBc

f IN=100MHz929088

f IN=130MHz85

f IN=10MHz108107102

f IN=30MHz87101871058699

HD2Second-harmonic f IN=70MHz10010195dBc

f IN=100MHz9910092

f IN=130MHz85

ADS5481

ADS5482

ADS5483

SLAS565C–JUNE2008–REVISED https://www.wendangku.net/doc/4516249082.html, ELECTRICAL CHARACTERISTICS(ADS5481,ADS5482,ADS5483)(continued)

ADS5481ADS5482ADS5483 PARAMETER TEST CONDITIONS UNIT

MIN TYP MAX MIN TYP MAX MIN TYP MAX

f IN=10MHz10396110

f IN=30MHz87100879886100

HD3Third-harmonic f IN=70MHz939196dBc

f IN=100MHz929088

f IN=130MHz88

f IN=10MHz989897

f IN=30MHz879787988697

Worst harmonic/spur

f IN=70MHz969798dBc

(other than HD2and HD3)

f IN=100MHz969497

f IN=130MHz96

f IN=10MHz969597

f IN=30MHz849484958394

THD Total harmonic distortion f IN=70MHz938891dBc

f IN=100MHz889286

f IN=130MHz83

f IN=10MHz8079.577.9

f IN=30MHz76.779.576.779.37477.8

SINAD Signal-to-noise and distortion f IN=70MHz78.978.277.4dBc

f IN=100MHz77.87876.6

f IN=130MHz76

f IN1=29.5MHz,f IN2=30.5

MHz,each at–7dBFS,103101100

worst spur

IMD Two-tone SFDR dBFS

f IN1=102MHz,f IN2=103

MHz,each at–7dBFS,90

worst spur

f IN=10MHz(from SINAD

1312.912.64

in dBc)

ENOB Effective number of bits Bits

f IN=30MHz(from SINAD

12.412.912.412.881212.63

in dBc)

Analog inputs shorted

RMS idle-channel noise 1.8 1.8 2.2LSBrms

together

LVDS DIGITAL OUTPUTS

Assumes a100?differential

V OD Differential output voltage(±)load on each LVDS pair and247350454247350454247350454mV

LVDS bias=3.5mA

Common-mode output

V OC 1.125 1.375 1.125 1.375 1.125 1.375V voltage

DIGITAL INPUTS

V IH High level input voltage 2.0 2.0 2.0V

V IL Low level input voltage0.80.80.8V

I IH High level input current PDWNF,PDWNS,DITHER111μA

I IL Low level input current-1-1-1μA

Input capacitance222pF

6Submit Documentation Feedback Copyright?2008–2009,Texas Instruments Incorporated

T0158-02

Sampling Clock Input

Data Clock

Output

Output Data

N –1E = Even Bits = B0, B2, B4, B6, B8, B10, B12, B14O = Odd Bits = B1, B3, B5, B7, B9, B11, B13, B15

Dx_y_P/M are LVDS outputs that have two bits per pair (EVEN and ODD).The values for x and y are 0_1, 2_3, 4_5, ... 14_15.

ADS5481ADS5482ADS5483

https://www.wendangku.net/doc/4516249082.html, .....................................................................................................................................................SLAS565C –JUNE 2008–REVISED OCTOBER 2009

TIMING INFORMATION

Figure 1.Timing Diagram

TIMING CHARACTERISTICS (1)

Typical values at T A =+25°C:minimum and maximum values over full temperature range T MIN =–40°C to T MAX =+85°C,

sampling rate =max rated,50%clock duty cycle,AVDD5=5V,AVDD3=3.3V,DVDD3=3.3V,and 3-V PP differential clock,unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT t a

Aperture delay 200ps Aperture jitter,rms Internal jitter of the ADC

80fs Latency

cycles t CLK Clock period

1e9/CLK 100ns t CLKH Clock pulse duration,high CLK =max rated clock for that part number

0.5e9/CLK 50ns t CLKL Clock pulse duration,low 0.5e9/CLK

50ns t DRY CLK to DRY delay (2)150019002300ps Zero crossing,5-pF parasitic to GND t DATA CLK to DATA delay (2)14001900

2400ps t SKEW DATA to DRY skew t DATA –t DRY ,5-pF parasitic to GND –600

0600ps t RISE DRY/DATA rise time 500ps 5-pF parasitic to GND

t FALL DRY/DATA fall time

500

(1)Timing parameters are assured by design or characterization,but not production tested.

(2)

DRY and DATA are updated on the rising edge of CLK input.The latency must be added to t DATA to determine the overall propagation delay.

AGND

48474645444342

4140393837363534

33ADS548x RGC Package (Top View)

123456789

10111213141516AVDD5AVDD5AGND REF NC NC AGND AVDD5AVDD3AGND INP INM AGND AVDD5AVDD3VCM

A G N D

A V D D 5

A V D D 3

A G N D

C L K M

C L K P

A G N D

A V D D 5

A V D D 3

A G N D

A V D D 5

A V D D 3

A G N D

A V D D 5

A V D D 3

A G N D

6418

6319

6220

61216022

5923

5824

5725

5626

5527

5428

5329

5230

513150

49D4_5_P D4_5_M D2_3_P D2_3_M D0_1_P D0_1_M DVDD3DGND NC NC NC NC DITHER PDWNS PDWNF LVDSB

D G N D

D V D D 3

D 14_15_P

D 14_15_M

D 12_13_P

D 12_13_M

D 10_11_P

D 10_11_M

D 8_9_P

D 8_9_M

D R Y _P

D R Y _M

D V D D 3

D G N D

D 6_7_P

D 6_7_M P0056-08

ADS5481ADS5482ADS5483

SLAS565C –JUNE 2008–REVISED OCTOBER https://www.wendangku.net/doc/4516249082.html,

PIN CONFIGURATION

8Submit Documentation Feedback Copyright ?2008–2009,Texas Instruments Incorporated

ADS5481

ADS5482

Table2.TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME NO.

1,2,8,14,18,

AVDD55V analog supply

24,27,30

9,15,19,25,

AVDD3 3.3V analog supply

28,31

3,7,10,13,17,

AGND20,23,26,29,Analog ground

DVDD342,52,63 3.3V digital supply

DGND41,51,64Digital ground

NC5,6,37-40No connects-leave floating

INP,INM11,12Differential analog inputs(P=plus=true,M=minus=complement)

CLKM,CLKP21,22Differential clock inputs(P=plus=true,M=minus=complement)

Reference voltage input/output(1.2V nominal).To use an external reference and to turn the internal REF4

reference off,pull both PDWNF and PDWNS to logic high(DVDD3).

Analog input common mode,output(3.1V),for use in applications that require use of the internally

VCM16

generated common-mode.See the applications section for more information on using VCM.

External bias resistor for LVDS bias current,normally10k?to GND to provide nominal3.5mA LVDS LVDSB33

current

Light sleep power down,fast wakeup,logic high(DVDD3)=light sleep enabled(bandgap reference PDWNF34

remains on)

Deep sleep power down,slow wakeup,logic high(DVDD3)=deep sleep enabled(bandgap reference is PDWNS35

off)

DITHER36Dither enable,logic high(DVDD3)=dither enabled

DRY_P,

54,53Dataready signal(LVDS clockout)(P=plus=true,M=minus=complement)

DRY_M

D14_15_P,

62,61DDR LVDS output bits14then15(15is MSB)(P=plus=true,M=minus=complement)

D14_15_M

DE_O_P,

43-50,55-62DDR LVDS output bits E(even)then O(odd)(P=plus=true,M=minus=complement)

DE_O_M

D0_1_P,

44,43DDR LVDS output bits0then1(0is LSB)(P=plus=true,M=minus=complement)

D0_1_M

PowerPAD65Analog ground(exposed pad on bottom of package)

?130

?120?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B

?130

?120?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B

?130

?120?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B

?130

?120?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B

ADS5481ADS5482ADS5483

SLAS565C –JUNE 2008–REVISED OCTOBER https://www.wendangku.net/doc/4516249082.html,

TYPICAL CHARACTERISTICS

At T A =+25°C,sampling rate =max rated,50%clock duty cycle,3-V PP differential sinusoidal clock,analog input amplitude =

–1dBFS,AVDD5=5V,AVDD3=3.3V,and DVDD3=3.3V,unless otherwise noted.

ADS5481-80MSPS Typical Data

Plots in this section are with a clock of 80MSPS unless otherwise specified.

ADS5481SPECTRAL PERFORMANCE

FFT for 10MHz INPUT SIGNAL

FFT for 30MHz INPUT SIGNAL

ADS5481SPECTRAL PERFORMANCE

FFT for 60MHz INPUT SIGNAL

FFT for 100MHz INPUT SIGNAL

Figure 4.10Submit Documentation Feedback Copyright ?2008–2009,Texas Instruments Incorporated

分销商库存信息:

ADS5483IRGCT ADS5483IRGCR