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XCR3128-12PC100C中文资料

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Introduction

?Industry's first TotalCMOS? PLD - both CMOS design and process technologies

?Fast Zero Power (FZP?) design technique provides ultra-low power and very high speed

IEEE 1149.1-compliant, JTAG Testing Capability -Four pin JTAG interface (TCK, TMS, TDI, TDO)-IEEE 1149.1 TAP Controller

-JTAG commands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ

3.3V, In-System Programmable (ISP) using the JTAG interface

-On-chip supervoltage generation

-ISP commands include: Enable, Erase, Program, Verify

-Supported by multiple ISP programming plat-forms

?High speed pin-to-pin delays of 10 ns ?Ultra-low static power of less than 100 μA

?100% routable with 100% utilization while all pins and all macrocells are fixed

?Deterministic timing model that is extremely simple to use

?Four clocks available

?Programmable clock polarity at every macrocell ?Support for asynchronous clocking

?Innovative XPLA? architecture combines high-speed with extreme flexibility

?1000 erase/program cycles guaranteed ?20 years data retention guaranteed ?Logic expandable to 37 product terms ?PCI compliant

?Advanced 0.5μ E 2CMOS process

?Security bit prevents unauthorized access

?Design entry and verification using industry standard and Xilinx CAE tools

?Reprogrammable using industry standard device programmers

Innovative control term structure provides either sum terms or product terms in each logic block for:-Programmable 3-state buffer

-Asynchronous macrocell register preset/reset

-Programmable global 3-state pin facilitates "bed of nails" testing without using logic resources

-Available in PLCC, VQFP , and PQFP packages -Available in both commercial and industrial grades

Description

The XCR3128 CPLD (Complex Programmable Logic Device) is the third in a family of CoolRunner ? CPLDs from Xilinx. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZP design technique,the XCR3128 offers true pin-to-pin speeds of 10 ns, while simultaneously delivering power that is less than 100μA at standby without the need for ‘turbo-bits ’ or other power-down schemes. By replacing conventional sense amplifier methods for implementing product terms (a tech-nique that has been used in PLDs since the bipolar era)with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the pat-ented full CMOS FZP design technique. For 5V applica-tions, Xilinx also offers the high speed XCR5128 CPLD that offers these features in a full 5V implementation.

The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 10 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated effi-ciently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns,regardless of the number of PLA product terms used, which results in worst case t PD ’s of only 12.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.

The XCR3128 CPLDs are supported by industry standard CAE tools (CadencE/OrCAD, Exemplar Logic, Mentor,Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design ver-ification uses industry standard simulators for functional and timing simulation. Development is supported on per-sonal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).

XCR3128: 128 Macrocell CPLD

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Product Specification

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The XCR3128 CPLD is electrically reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The XCR3128 also includes an industry-standard, IEEE 1149.1, JTAG interface through which in-system program-ming (ISP) and reprogramming of the device is supported.

XPLA Architecture

Figure 1 shows a high level block diagram of a 128 macro-cell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected

by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-tual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macro-cells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins.

From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks.The contents of the logic block will be described next.

Figure 1: Xilinx XPLA Architecture

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Logic Block Architecture

Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the six control terms can individually be con-figured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 mac-rocells ’ flip-flops. The PAL array consists of a programma-ble AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programma-ble OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density.

Each macrocell has five dedicated product terms from the PAL array. The pin-to-pin t PD of the XCR3128 device through the PAL array is 10 ns. If a macrocell needs more than five product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32product terms, which are available for use by all 16 macro-cells. The additional propagation delay incurred by a mac-rocell using one or all 32 PLA product terms is just 2.5 ns.So the total pin-to-pin t PD for the XCR3128 using six to 37product terms is 12.5 ns (10 ns for the PAL + 2.5 ns for the PLA).

Figure 2: Xilinx XPLA Logic Block Architecture

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Macrocell Architecture

Figure 3 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D- or T-type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner fam-ily members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are four clocks available on the XCR3128 device. Clock 0(CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2(CLK2), and Clock 3 (CLK3) can either be used as a syn-chronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). The timing for asynchronous clocks is different in that the t CO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the t SU time is reduced.

Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell ’s flip-flop. The Pre-set/Reset feature for each macrocell can also be disabled.Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied. The other four

control terms (CT2-CT5) can be used to control the Output Enable of the macrocell ’s output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell ’s output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global 3-state (GTS) pin, which, when enabled and pulled Low, will 3-state all the outputs of the device.This pin is provided to support "In-circuit Testing" or "Bed-of-nails" testing.

There are two feedback paths to the ZIA: one from the mac-rocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path,while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the mac-rocell. When the I/O pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic imple-mented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated (see the section on “T erminations ” on page 9 in this data sheet and the application note Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunner ? CPLDs ).

Figure 3: XCR3128 Macrocell Architecture

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Simple Timing Model

Figure 4 shows the CoolRunner Timing Model. The Cool-Runner timing model looks very much like a 22V10 timing model in that there are three main timing parameters,including t PD , t SU , and t CO . In other competing architec-tures, the user may be able to fit the design into the CPLD,but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependen-cies on the number of parallel expanders borrowed, shar-able expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model.

TotalCMOS Design Technique for Fast Zero Power

Xilinx is the first to offer a TotalCMOS CPLD, both in pro-cess technology and design technique. Xilinx employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs which are both high performance and low power, breaking the para-digm that to have low power, you must have low perfor-mance. Refer to Figure 5 and Table 1 showing the I CC vs.Frequency of our XCR3128 TotalCMOS CPLD (data taken w/eight up/down, loadable 16 bit counters at 3.3V, 25°C).

Figure 4: CoolRunner Timing Model

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JTAG Testing Capability

JTAG is the commonly-used acronym for the Boundary Scan Test (BST) feature defined for integrated circuits by IEEE Standard 1149.1. This standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of spe-cialized test equipment. BST provides the ability to test the external connections of a device, test the internal logic of the device, and capture data from the device during normal operation. BST provides a number of benefits in each of the following areas:?

Testability

-Allows testing of an unlimited number of interconnects on the printed circuit board

-Testability is designed in at the component level -Enables desired signal levels to be set at specific pins (Preload)

Data from pin or core logic signals can be examined during normal operation ?

Reliability

-Eliminates physical contacts common to existing test fixtures (e.g., "bed-of-nails")

-Degradation of test equipment is no longer a concern

-Facilitates the handling of smaller, surface-mount components

-Allows for testing when components exist on both sides of the printed circuit board ?

Cost

-Reduces/eliminates the need for expensive test equipment

-Reduces test preparation time -Reduces spare board inventories

The Xilinx XCR3128's JTAG interface includes a TAP Port and a TAP Controller, both of which are defined by the IEEE 1149.1 JTAG Specification. As implemented in the Xilinx

Figure 5: I CC vs. Frequency @ V CC = 3.3V, 25°C

Table 1: I CC vs. Frequency (V CC = 3.3V, 25°C)Frequency (MHz)0120406080100Typical I CC (mA)

.03

.06

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XCR3128, the TAP Port includes four of the five pins (refer to T able 2) described in the JTAG specification: TCK, TMS,TDI, and TDO. The fifth signal defined by the JTAG specifi-cation is TRST* (Test Reset). TRST* is considered an optional signal, since it is not actually required to perform BST or ISP . The Xilinx XCR3128 saves an I/O pin for gen-eral purpose use by not implementing the optional TRST*signal in the JTAG interface. Instead, the Xilinx XCR3128supports the test reset functionality through the use of its power up reset circuit, which is included in all Xilinx CPLDs.The pins associated with the power up reset circuit should connect to an external pull-up resistor to keep the JTAG signals from floating when they are not being used.In the Xilinx XCR3128, the four mandatory JTAG pins each require a unique, dedicated pin on the device. However, if JTAG and ISP are not desired in the end-application, these pins may instead be used as additional general I/O pins.The decision as to whether these pins are used for JTAG/ISP or as general I/O is made when the JEDEC file is generated. If the use of JTAG/ISP is selected, the dedi-cated pins are not available for general purpose use. How-ever, unlike competing CPLD ’s, the Xilinx XCR3128 does allow the macrocell logic associated with these dedicated pins to be used as buried logic even when JTAG/ISP is selected. Table 3 defines the dedicated pins used by the four mandatory JTAG signals for each of the XCR3128package types.

The JTAG specifications defines two sets of commands to support boundary-scan testing: high-level commands and low-level commands. High-level commands are executed via board test software on an a user test station such as automated test equipment, a PC, or an engineering work-station (EWS). Each high-level command comprises a sequence of low level commands. These low-level com-mands are executed within the component under test, and therefore must be implemented as part of the TAP Control-ler design. The set of low-level boundary-scan commands implemented in the Xilinx XCR3128 is defined in T able 4.By supporting this set of low-level commands, the XCR3128 allows execution of all high-level boundary-scan commands.

Table 2: JTAG Pin Description

PIN NAME

DESCRIPTION

TCK

Test Clock Output

Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively. TCK is also used to clock the TAP Controller state machine.

TMS Test Mode Select Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode operation.

TDI Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK.

TDO

Test Data Output

Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The signal is tri-stated if data is not being shifted out of the device.

Table 3: XCR3128 JTAG Pinout by Package Type

Device XCR3128(Pin Number / Macrocell #)

TCK TMS TDI TDO

84-pin PLCC 62 / 96 (F15)23 / 48 (C15)14 / 32 (B15)71 / 112 (G15)100-pin PQFP 64 / 96 (F15)17 / 48 (C15) 6 / 32 (B15)75 / 112 (G15)100-pin VQFP 62 / 96 (F15)15 / 48 (C15) 4 / 32 (B15)73 / 112 (G15)128-pin TQFP 82 / 96 (F15)21 / 48 (C15) 8 / 32 (B15)95 / 112 (G15)160-pin PQFP

99 / 96 (F15)

22 / 48 (C15) 9 / 32 (B15)

112/ 112 (G15)

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3.3V In-System Programming (ISP)

ISP is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic sys-tem before, during, and after its manufacture and shipment to the end customer. ISP provides substantial benefits in each of the following areas:?

Design

-Faster time-to-market

-Debug partitioning and simplified prototyping

-Printed circuit board reconfiguration during debug -Better device and board level testing ?

Manufacturing

-Multi-Functional hardware -Reconfigurability for test

-Eliminates handling of "fine lead-pitch" components for programming

-Reduced Inventory and manufacturing costs -Improved quality and reliability

Field Support

-Easy remote upgrades and repair

-Support for field configuration, re-configuration, and customization

The Xilinx XCR3128 allows for 3.3V, in-system program-ming/reprogramming of its EEPROM cells via its JTAG interface. An on-chip charge pump eliminates the need for externally-provided supervoltages, so that the XCR3128may be easily programmed on the circuit board using only the 3.3-volt supply required by the device for normal opera-tion. A set of low-level ISP basic commands implemented in the XCR3128 enable this feature. The ISP commands implemented in the Xilinx XCR3128 are specified in T able 5Please note that an ENABLE command must precede all ISP commands unless an ENABLE command has already been given for a preceding ISP command and the device has not gone through a Test-Logic/Rest TAP Controller State. See also Table 5 Programming Specifications.

Table 4: XCR3128 Low-Level JTAG Boundary-Scan Commands

Instruction (Instruction Code)Register Used

Description

Sample/Preload (0010)

Boundary-Scan Register The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register prior to selection of the other boundary-scan test instructions.

Extest (0000)

Boundary-Scan Register The mandatory EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data would typically be loaded onto the latched parallel outputs of Boundary-Scan Shift-Register using the Sample/Preload instruction prior to selection of the EXTEST instruction.

Bypass (1111)

Bypass Register Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. The Bypass instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle.

Idcode (0001)

Boundary-Scan Register

Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed circuit board. Thus, in circumstances where the component population may vary, it is possible to deter-mine what components exist in a product.

HighZ (0101)

Bypass Register

The HIGHZ instruction places the component in a state in which all of its system logic outputs are placed in an inactive drive state (e.g., high impedance). In this state, an in-circuit test system may drive signals onto the connections normally driven by a component output without incurring the risk of damage to the compo-nent. The HighZ instruction also forces the Bypass Register between TDI and TDO.

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Terminations

The CoolRunner XCR3128 CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O pins when fabricating a PC board. Allowing unused inputs and I/O pins to float can cause the voltage to be in the linear region of the CMOS input structures, which can increase the power consumption of the device. The XCR3128CPLDs have programmable on-chip pull-down resistors on each I/O pin. These pull-downs are automatically activated by the fitter software for all unused I/O pins. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the XCR3128 device be left uncon-nected.

There are no on-chip pull-down structures associated with the dedicated input pins. Xilinx recommends that any unused dedicated inputs be terminated with external 10k ?pull-up resistors. These pins can be directly connected to V CC or GND, but using the external pull-up resistors main-tains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes.When using the JTAG/ISP functions, it is also recom-mended that 10k ? pull-up resistors be used on each of the pins associated with the four mandatory JTAG signals. Let-

ting these signals float can cause the voltage on TMS to come close to ground, which could cause the device to enter JTAG/ISP mode at unspecified times. See the appli-cation notes JTAG and ISP Overview for Xilinx XPLA1 and XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunner CPLDs for more informa-tion.

JTAG and ISP Interfacing

A number of industry-established methods exist for JTAG/ISP interfacing with CPLD ’s and other integrated cir-cuits. The Xilinx XCR3128 supports the following methods:?PC parallel port

?Workstation or PC serial port ?Embedded processor

?Automated test equipment ?Third party programmers

High-End JTAG and ISP tools

A Boundary-Scan Description Language (BSDL) descrip-tion of the XCR3128 is also available from Xilinx for use in test program development. For more details on JTAG and ISP for the XCR3128, refer to the related application note:JTAG and ISP Overview for Xilinx XPLA1 and XPLA2CPLDs .

Table 5: Programming Specifications Symbol

Parameter

Min.Max.Unit DC Parameters

V CCP

V CC supply program/verify 3.0 3.6V I CCP I CC limit program/verify 200

mA V IH Input voltage (High) 2.0

V V IL Input voltage (Low)0.8V V SOL Output voltage (Low)0.5

V V SOH Output voltage (High) 2.4V TDO_I OL Output current (Low)8mA TDO_I OH Output current (High)-8mA AC Parameters f MAX CLK maximum frequency 10MHz PWE Pulse width erase 100ms PWP Pulse width program 10ms PWV Pulse width verify 10μs INIT Initialization time

100μs TMS_SU TMS setup time before TCK =10ns TDI_SU TDI setup time before TCK =10ns TMS_H TMS hold time after TCK =25ns TDI_H TDI hold time after TCK =25

ns TDO_CO TDO valid after TCK Ο

40ns

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Absolute Maximum Ratings 1

Operating Range

DC Electrical Characteristics For Commercial Grade Devices

Commercial: 0°C ≤ T AMB ≤ +70°C; 3.0V ≤ V CC ≤ 3.6V Symbol Parameter

Min.Max.Unit V CC

Supply voltage 2-0.57.0V V I Input voltage -1.2V CC + 0.5V V OUT Output voltage -0.5V CC + 0.5

V I IN Input current -3030mA I OUT Output current

-100100mA T J Maximum junction temperature -40150°C T str

Storage temperature

-65

150

°C

Notes:

1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.

Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied.

2. The chip supply voltage must rise monotonically.

Product Grade Temperature Voltage Commercial 0 to +70°C 3.3V ± 10%Industrial

-40 to +85°C

3.3V ± 10%

Symbol Parameter

Test Conditions

Min.Max.Unit V IL Input voltage low V CC = 3.0V 0.8V V IH Input voltage high V CC = 3.6V

2.0

V V I Input clamp voltage V CC = 3.0V, I IN = -18 mA -1.2V V OL Output voltage low V CC = 3.0V, I OL = 8 mA 0.5

V V OH Output voltage high V CC = 3.0V, I OH = -8 mA 2.4V I I Input leakage current

V IN = 0 to V CC -1010μA I OZ 3-stated output leakage current V IN = 0 to V CC

-10

10μA I CCQ 1Standby current V CC = 3.6V, T AMB = 0°C

60μA I CCD 1, 2Dynamic current

V CC = 3.6V, T AMB = 0°C at 1 MHz 2mA V CC = 3.6V, T AMB = 0°C at 50 MHz 50mA I OS Short circuit output current 3One pin at a time for no longer than 1 second

-50

-100mA C IN Input pin capacitance 3T AMB = 25°C, f = 1 MHz 8pF C CLK Clock input capacitance 3T AMB = 25°C, f = 1MHz 5

12pF C I/O

I/O pin capacitance 3

T AMB = 25°C, f = 1MHz

Notes:

1. See Table 1 on page 6 for typical values.

2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing.

3. Typical values, not tested.

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AC Electrical Characteristics 1 For Commercial Grade Devices

Commercial: 0°C ≤ T AMB ≤ +70°C; 3.0V ≤ V CC ≤ 3.6V Symbol Parameter

101215Unit Min.Max.Min.Max.Min.Max.t PD_PAL Propagation delay time, input (or feedback node) to output through PAL

210212215ns t PD_PLA Propagation delay time, input (or feedback node) to output through PAL + PLA

312.5314.5317.5ns t CO

Clock to out (global synchronous clock from pin)

ns t SU_PAL Setup time (from input or feedback node) through PAL 678ns t SU_PLA Setup time (from input or feedback node) through PAL + PLA 8.5

9.5

10.5

ns t H Hold time

ns t CH Clock High time 344ns t CL Clock Low time 3

ns t R Input Rise time 202020ns t F

Input Fall time

ns f MAX1Maximum FF toggle rate 2 1/(t CH + t CL )

167125125MHz f MAX2Maximum internal frequency 2 1/(t SUPAL + t CF )877465MHz f MAX3Maximum external frequency 2 1/(t SUPAL + t CO )776659

MHz t BUF

Output buffer delay time

1.5 1.5 1.5ns t PDF_PAL Input (or feedback node) to internal feedback node delay time through PAL

20.5210.5213.5ns t PDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA

113133

16ns t CF Clock to internal feedback node delay time 5.5 6.57.5ns t INIT Delay from valid V DD to valid reset 505050μs t ER Input to output disable 312.51417ns t EA Input to output valid 12.51417ns t RP Input to register preset 141619ns t RR

Input to register reset

Notes:

1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.

2. This parameter guaranteed by design and characterization, not by test.

3. Output C L = 5 pF.

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DC Electrical Characteristics For Industrial Grade Devices

Industrial: -40°C ≤ T AMB ≤ +85°C; 3.0V ≤ V CC ≤ 3.6V Symbol Parameter

Test Conditions

Min.Max.Unit V IL Input voltage Low V CC = 3.0V 0.8V V IH Input voltage High V CC = 3.6V

2.0

V V I Input clamp voltage V CC = 3.0V, I IN = -18 mA -1.2V V OL Output voltage Low V CC = 3.0V, I OL = 8 mA 0.5

V V OH Output voltage High V CC = 3.0V, I OH = -8 mA 2.4V I I Input leakage current

V IN = 0 to V CC -1010μA I OZ 3-stated output leakage current V IN = 0 to V CC

-10

10μA I CCQ 1Standby current V CC = 3.6V, T AMB = -40°C

75μA I CCD 1, 2Dynamic current

V CC = 3.6V, T AMB = -40°C at 1 MHz 2mA V CC = 3.6V, T AMB = -40°C at 50 MHz 50mA I OS Short circuit output current 3One pin at a time for no longer than 1 second

-50

-130mA C IN Input pin capacitance 3T AMB = 25°C, f = 1 MHz 8pF C CLK Clock input capacitance 3T AMB = 25°C, f = 1MHz 5

12pF C I/O

I/O pin capacitance 3

T AMB = 25°C, f = 1MHz

Notes:

1. See Table 1 on page 6 for typical values.

2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs DISabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing.

3. Typical values, not tested.

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AC Electrical Characteristics 1 For Industrial Grade Devices

Industrial: -40°C ≤ T AMB ≤ +85°C; 3.0V ≤ V CC ≤ 3.6V Symbol Parameter

1215Unit Min.

Max.Min.Max.t PD_PAL Propagation delay time, input (or feedback node) to output through PAL 212215ns t PD_PLA Propagation delay time, input (or feedback node) to output through PAL + PLA

314.5317.5ns t CO

Clock to out (global synchronous clock from pin)27.5

ns t SU_PAL Setup time (from input or feedback node) through PAL 78ns t SU_PLA Setup time (from input or feedback node) through PAL + PLA 9.510.5ns t H Hold time

ns t CH Clock High time 34ns t CL Clock Low time 34

ns t R Input Rise time 2020ns t F

Input Fall time

ns f MAX1Maximum FF toggle rate 2 1/(t CH + t CL )167125MHz f MAX2Maximum internal frequency 2 1/(t SUPAL + t CF )7765MHz f MAX3Maximum external frequency 2 1/(t SUPAL + t CO )6959

MHz t BUF

Output buffer delay time

1.5 1.5ns t PDF_PAL Input (or feedback node) to internal feedback node delay time through PAL

210.5213.5ns t PDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA

3133

16ns t CF Clock to internal feedback node delay time 67.5ns t INIT Delay from valid V CC to valid reset 5050μs t ER Input to output disable 31315.5ns t EA Input to output valid 1315.5ns t RP Input to register preset 1517ns t RR

Input to register reset

Notes:

1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating.

2. This parameter guaranteed by design and characterization, not by test.

3. Output C L = 5 pF.

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Switching Characteristics

The test load circuit and load values for the AC Electrical Characteristics are illustrated below.

Figure 6: t PD_PAL vs. Output Switching

Figure 7: Voltage Waveform

Table 6: t PD_PAL vs. Number of Outputs Switching (V CC = 3.3 V, T = 25°C) Number Of Outputs 12481216Typical (ns)

7.9

8.1

8.3

8.4

8.6

Pin Function And Layout

XCR3128: 100-pin and 160-pin PQFP Pin Function Table

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XCR3128: 84-pin PLCC, 100-Pin VQFP, and 128-pin TQFP Pin Function Table

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84-pin PLCC

100-pin PQFP

100-pin VQFP

128-pin TQFP

160-pin PQFP

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Ordering Information

Revision Table

Component Availability

Pins 84

100

128

160

Type Plastic PLCC

Plastic PQFP Plastic VQFP Plastic TQFP Plastic PQFP Code

PC84PQ100VQ100TQ128PQ160XCR3128

-15C, I C, I C, I C, I C, I -12C, I C, I C, I C, I C, I -10

Example: XCR3128 -10 PC 84 C

T emperature Range Number of Pins Package Type

Speed Options

-15: 15 ns pin-to-pin delay -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay

Temperature Range

C = Commercial, T A = 0°C to +70°C I = Industrial, T A = –40°C to +85°C Packaging Options PC84: 84-pin PLCC PQ100: 100-pin PQFP VQ100: 100-pin VQFP TQ128: 128-pin TQFP PQ160: 160-pin PQFP

Device Type Speed Options