HM1-6551883中文资料

March 1997

HM-6551/883

256 x 4 CMOS RAM

Features

?This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.?Low Power Standby. . . . . . . . . . . . . . . . . . . .50μW Max ?Low Power Operation . . . . . . . . . . . . .20mW/MHz Max ?Fast Access Time. . . . . . . . . . . . . . . . . . . . . .220ns Max ?Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min ?TTL Compatible Input/Output ?High Output Drive - 1 TTL Load ?Internal Latched Chip Select ?High Noise Immunity ?On-Chip Address Register ?Latched Outputs ?Three-State Output

Description

The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous cir-cuit design techniques are employed to achieve high perfor-mance and low power operation. On chip latches are provided for address and data outputs allowing ef?cient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays.

The HM-6551/883 is a fully static RAM and may be main-tained in any state for an inde?nite period of time. Data retention supply voltage and supply current are guaranteed over temperature.

Ordering Information

Pinout

HM-6551/883 (CERDIP)

TOP VIEW

PACKAGE TEMPERATURE RANGE

220ns 300ns PKG. NO.CERDIP

-55o C to +125o C

HM-6551B/883

HM1-6551/883

F22.4

PIN DESCRIPTION A Address Input E Chip Enable W Write Enable S Chip Select D Data Input Q

Data Output

1221213141516171819212011

109876532A2A1A0A5A6A7D0GND Q0D1A4Q3D3Q2D2Q1

4A3VCC W S1E S2File Number

2988.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Functional Diagram

NOTES:

1.Select Latch: L Low → Q = D and Q latches on rising edge of L.

2.Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.

3.All lines positive logic-active high.

4.Three-State Buffers: A high → output active.

5.Data Latches: L High → Q = D and Q latches on falling edge of L.

GATED ROW DECODER

A032

55

A

A1A5A6A7A

LATCHED ADDRESS REGISTER

32 x 32MATRIX

D 3

3

A

A

S1

S2W E LATCH

SELECT A4

A3A2LATCHED ADDRESS

REGISTER

LATCHES DATA OUTPUT

GATED COLUMN

DECODER AND DATA I/O

D0A A A A

A

A A A L

88

88D

D

D

D1D2D3

D Q L

Q

Q

Q Q Q0Q1Q2Q3

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Input, Output or I/O Voltage . . . . . . . . . . .GND -0.3V to VCC +0.3V ESD Classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1Thermal ResistanceθJAθJC CERDIP Package . . . . . . . . . . . . . . . .60o C/W15o C/W Maximum Storage Temperature Range . . . . . . . . .-65o C to +150o C Maximum Junction T emperature. . . . . . . . . . . . . . . . . . . . . .+175o C Maximum Lead T emperature (Soldering 10s). . . . . . . . . . . .+300o C Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1930 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied.

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . .-55o C to +125o C Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . .40ns Max.

TABLE1.HM-6551/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested

PARAMETER SYMBOL

(NOTE 1)

CONDITIONS

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITS

MIN MAX

Output Low Voltage VOL VCC = 4.5V

IOL = 1.6mA

1, 2, 3-55o C≤ T A≤ +125o C-0.4V

Output High Voltage VOH VCC = 4.5V

IOH = -0.4mA

1, 2, 3-55o C≤ T A≤ +125o C 2.4-V

Input Leakage Current II VCC = 5.5V,

VI = GND or VCC

1, 2, 3-55o C≤ T A≤ +125o C-1.0+1.0μA

Output Leakage Current IOZ VCC = 5.5 V,

VO = GND or VCC

1, 2, 3-55o C≤ T A≤ +125o C-1.0+1.0μA

Data Retention Supply Current ICCDR VCC = 2.0V,E = VCC

IO = 0mA,

VI = VCC or GND

1, 2, 3-55o C≤ T A≤ +125o C-10μA

Operating Supply Current ICCOP VCC = 5.5V, (Note 2)

E = 1MHz, IO = 0mA

VI = VCC or GND

1, 2, 3-55o C≤ T A≤ +125o C-4mA

Standby Supply Current ICCSB VCC = 5.5V,

IO = 0mA

VI = VCC or GND

1, 2, 3-55o C≤ T A≤ +125o C-10μA

NOTES:

1.All voltages referenced to device GND.

2.Typical derating 1.5mA/MHz increase in ICCOP.

TABLE2.HM-6551/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested

PARAMETER SYMBOL (NOTES 1, 2)

CONDITIONS

GROUP A

SUB-

GROUPS TEMPERATURE

LIMITS

UNITS

HM-6551B/883HM-6551/883

MIN MAX MIN MAX

Chip Enable Access Time (1)TELQV VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C-220-300ns

Address Access Time (2)TAVQV VCC = 4.5 and

5.5V, Note 3

9, 10, 11-55o C≤ T A≤ +125o C-220-300ns

Chip Select 1 Output Enable Time (3)TS1LQX VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C5-5-ns

Write Enable Output Disable Time (4)TWLQZ VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C-130-150ns

Chip Select 1 Output Disable Time (5)TS1HQZ VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C-130-150ns

Chip Enable Pulse Negative Width (6)TELEH VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C220-300-ns

Chip Enable Pulse Positive Width (7)TEHEL VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C100-100-ns

Address Setup Time (8)TAVEL VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C0-0-ns

Chip Select 2 Setup Time (9)TS2LEL VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C0-0-ns

Address Hold Time(10)TELAX VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C40-50-ns

Chip Select 2 Hold Time (11)TELS2X VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C40-50-ns

Data Setup Time(12)TDVWH VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C100-150-ns

Data Hold Time(13)TWHDX VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C0-0-ns

Chip Select 1 Write Pulse Setup Time (14)TWLS1H VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C120-180-ns

Chip Enable Write Pulse Setup Time (15)TWLEH VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C120-180-ns

Chip Select 1 Write Pulse Hold Time (16)TS1LWH VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C120-180-ns

Chip Enable Write Pulse Hold Time (17)TELWH VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C120-180-ns

Write Enable Pulse Width (18)TWLWH VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C120-180-ns

Read or Write Cycle Time (19)TELEL VCC = 4.5 and

5.5V

9, 10, 11-55o C≤ T A≤ +125o C320-400-ns

NOTES:

1.All voltages referenced to device GND.

2.Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:

IOL = 1.6mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

3.TAVQV = TELQV + TAVEL.

TABLE3.HM-6551B/883 AND HM-6551/883 ELECTRICAL PERFORMANCE SPECIFICATIONS

PARAMETER SYMBOL CONDITIONS NOTE TEMPERATURE

LIMITS

UNITS MIN MAX

Input Capacitance CI VCC = Open, f = 1MHz, All

Measurements Referenced to

Device Ground

1T A = +25o C-10pF

Output Capacitance CO VCC = Open, f = 1MHz, All

Measurements Referenced to

Device Ground

1T A = +25o C-12pF

NOTE:

1.The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major

process and/or design changes.

TABLE4.APPLICABLE SUBGROUPS

CONFORMANCE GROUPS METHOD SUBGROUPS

Initial Test100%/5004-

Interim Test100%/50041, 7, 9

PDA100%/50041

Final Test100%/50042, 3, 8A, 8B, 10, 11

Group A Samples/50051, 2, 3, 7, 8A, 8B, 9, 10, 11

Groups C & D Samples/50051, 7, 9

Timing Waveforms

The HM-6551/883 Read Cycle is initiated by the falling edge of E. This signal latches the input address word and S2 into on-chip registers providing the minimum setup and hold times are met. After the required hold time, these inputs may change state without affecting device operation.S2 acts as a high order address and simpli?es decoding. For the output to be read,E,S1 must be low and W must be high.S2 must have been latched low on the falling edge of E. The output

data will be valid at access time (TELQV). The HM-6551/883has output data latches that are controlled by E. On the ris-ing edge of E the present data is latched and remains in that state until E falls. Also on the rising edge of E,S2 unlatches and controls the outputs along with S1. Either or both S1 or S2 may be used to force the output buffers into a high impedance state.

TELAX (8) TAVEL

(10)(8) TAVEL

A

NEXT

-1TIME

012345

REFERENCE

(9) TS2LEL

TELS2X (11)

(9) TS2LEL

TELQV (1)TAVQV (2)

TS1HQZ (5)

VALID OUTPUT

(3) TS1LQX

HIGH

D

Q

W

S1

S2

E

VALID

(19) TELEL

TELEH (6)

TEHEL (7)(7) TEHEL

FIGURE 1.READ CYCLE

TRUTH TABLE

TIME REFERENCE

INPUTS

OUTPUTS

FUNCTION

E S1S2W A D Q -1H

H X X X X Z Memory Disabled

0X L H V X Z Addresses and S2 are Latched,Cycle Begins

1L L X H X X X Output Enabled but Undefined 2L

L X H X X V Data Output Valid

3L X H X X V Outputs Latched, Valid Data,S2 Unlatches

4H H X X X X Z Prepare for Next Cycle (Same as -1)

5

X

L

H

V

X

Z

Cycle Ends, Next Cycle Begins (Same as 0)

Timing Waveforms (Continued)

In the Write Cycle the falling edge of E latches the addresses and S2 into on-chip registers.S2 must be latched in the low state to enable the device. The write portion of the cycle is de?ned as E,W,S1 being low and S2 being latched simulta-neously. The W line may go low at any time during the cycle providing that the write pulse setup times (TWLEH and TWLS1H) are met. The write portion of the cycle is terminated on the ?rst rising edge of either E,W, or S1.

If a series of consecutive write cycles are to be executed, the W line may be held low until all desired locations have been written. If this method is used, data setup and hold times must be referenced to the ?rst rising edge of E or S1. By positioning

the write pulse at different times within the E and S1 low time (TELEH), various types of write cycles may be performed. If the S1 low time (TS1LS1H) is greater than the W pulse, plus an output enable time (TS1LQX), a combination read-write cycle is executed. Data may be modi?ed an inde?nite number of times during any write cycle (TELEH).

The HM-6551/883 may be used on a common I/O bus struc-ture by tying the input and output pins together. The multiplex-ing is accomplished internally by the W line. In the write cycle,when W goes low, the output buffers are forced to a high impedance state. One output disable time delay (TWLQZ)must be allowed before applying input data to the bus.

(8) TAVEL

VALID

(8) TAVEL

NEXT

TELEH (6)

(11)

TWHDX (13)

TELEL (19)

(9) TS2LEL

TEHEL (7)TELS2X (9) TS2LEL

TWLEH (15)

TDVWH (12)TWLWH (18)TS1LWH (16)

TWLS1H (14)

-1

TIME

1

2345

REFERENCE

A

E

S2

D W

S1

(10)TELAX TEHEL (7)

DATA VALID

TELWH (17)

FIGURE 2.WRITE CYCLE

TRUTH TABLE

TIME REFERENCE

INPUTS

OUTPUTS

FUNCTION

E S1S2W A D Q -1H

H X X X X Z Memory Disabled

0X L X

V X Z Cycle Begins, Addresses and S2 are Latched

1L L X X X Z Write Period Begins 2L

L X X V Z Data In is Written 3X X H X X Z Write is Completed

4H H X X X X Z Prepare for Next Cycle (Same as -1)5

X

L

X V

X

Z

Cycle Ends, Next Cycle Begins (Same as 0)

Test Load Circuit

NOTE:

1.Test head capacitance includes stray and jig capacitance.

Burn-In Circuit

HM-6551/883CERDIP

NOTES:

All resistors 47k ?±5%.F0 = 100kHz ±10%.

F1 = F0÷2, F2 = F1÷ 2,F3 = F2÷2 . . . F12 = F11÷2.VCC = 5.5V ±0.5V .VIH = 4.5V ±10%.VIL = -0.2V to +0.4V .C1 = 0.01μF Min.

DUT 1.5V IOL

IOH

+-

(NOTE 1) CL

EQUIVALENT CIRCUIT

12212

13141516171819212011109

8

76532

4F7F9F4F5F10F3F8F2F0F3F3A2

A1A0A5A6A7D0

GND Q0D1

A3A4Q3D3Q2D2Q1VCC W S1E S2C1

F3F3F3

F6F11

F3

F3F1F0VCC

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certi?cation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speci?cations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site https://www.wendangku.net/doc/4b17499421.html,

Die Characteristics

DIE DIMENSIONS:

132 x 160 x 19±1mils METALLIZATION:T ype: Si - Al

Thickness: 11k ?±2k ?GLASSIVATION:T ype: SiO 2

Thickness: 8k ?±1k ?

WORST CASE CURRENT DENSITY:1.337 x 105 A/cm 2LEAD TEMPERATURE (10s soldering):≤300o C

Metallization Mask Layout

HM-6551/883

NOTE:Pin numbers correspond to DIP Package only.

S1

E

S2

Q3

D3

Q2D2Q1D1

Q0

D0

GND

A7

A6

A5A0

A1

A2

A3

A4

VCC W