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A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS
A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

A0.3V10-bit1.17f SAR ADC With Merge and Split Switching in90nm CMOS

Jin-Yi Lin and Chih-Cheng Hsieh

Abstract—This paper presents a10-bit ultra-low voltage en-ergy-ef?cient SAR ADC.The proposed merge-and-split(MS) switching effectively reduces DAC switching energy by83%com-pared with conventional one without the need of extra reference voltage and the issue of common-mode voltage variation. To maintain good input linearity,a new double-bootstrapped sample-and-hold(S/H)circuit is proposed under an ultra-low voltage of0.3V.In addition,by employing asymmetric logic in SAR control,the leakage power is reduced with the penalty of slight conversion speed degradation.The test chip fabricated in 90nm CMOS occupied a core area of0.03.With a single 0.3V supply and a Nyquist rate input,the prototype consumes35 nW at90kS/s and achieves an ENOB of8.38bit and a SFDR of 78.2dB,respectively.The operation frequency is scalable up to2 MS/s and power supply range from0.3V to0.5V.The resultant FOMs are1.17-to-1.78fJ/conv.-step.

Index Terms—Low power,low voltage,SAR ADC.

I.I NTRODUCTION

I N THE PAST FEW years,with the advancement of large-

scale integrated circuits,there has been a growing interest in the design of wireless sensor network for implantable,portable, and wearable applications.These sensing devices are gener-ally used for detecting and monitoring biomedical or environ-mental signals such as electrocardiographic(ECG),electroen-cephalography(EEG),electromyography(EMG),temperature, humidity,sound,and so on.In the sensor nodes,the power should be supplied by energy harvesting technologies to reduce the maintenance cost for battery replacement.Most of the small size energy harvesting devices,such as solar cells,can generate extremely low output voltage,and limited power.Therefore,ul-tralow-voltage and low-power operation is inevitable for wire-less sensor nodes.

The sensed signals are usually digitized by ADCs with mod-erate resolution(8–12bits)and sampling rate(1–1000kS/s).In these applications,ADCs are the most critical and power hungry blocks.Among various ADC architectures,successive approx-imation register(SAR)ADC shows a better power ef?ciency. Furthermore,SAR ADC bene?ts from technology downscaling because of two major reasons:1)SAR ADC mainly consists of digital circuits which get faster in advanced technologies,and is compatible with digital processors;and2)SAR ADC is an

Manuscript received April28,2014;revised July14,2014and August04, 2014;accepted August06,2014.Date of current version January06,2015.This research is particularly supported by National Science Council,Taiwan under Contract NSC102-2221-E-007-132and102-2220-E-007-008.This paper was recommended by Associate Editor A.M.A.Ali.

The authors are with the Department of Electrical Engineering,National Tsing-Hua University,Hsinchu30013,Taiwan(e-mail:jinyilin19@https://www.wendangku.net/doc/4e18371662.html,; cchsieh@https://www.wendangku.net/doc/4e18371662.html,.tw).

Color versions of one or more of the?

gures in this paper are available online at https://www.wendangku.net/doc/4e18371662.html,.

Digital Object Identi?er10.1109/https://www.wendangku.net/doc/4e18371662.html,mon10-bit asynchronous SAR ADC.

opamp-free architecture.In other words,SAR ADC does not require high gain and high bandwidth opamps,which consume large static power,and suffer from short channel effect and low supply voltage in advanced process.These reasons arouse many researches on exploring SAR ADC in depth.

Power consumption in a SAR ADC mainly lies in the DAC network,the comparator,and the SAR control logics,and the leakage current needs to be carefully manipulated as well.Many researches have shown interests in reducing DAC switching power[1]–[5].Compared to the conventional switching se-quence,the energy-saving[1],charge average switching(CAS) [2],set-and-down[3],-based[4],and,partial?oating[5] switching sequences reduce switching energy by69%,74.8%, 81%,90%,and94%,respectively.To reduce comparator noise, data-driven noise reduction[6]and majority vote comparison [7]are proposed.With respect to digital circuit,reducing supply voltage and employing advanced technology is bene?cial[1], [2],[6]–[14].However,analog circuits become challenging in low supply operation due to the reduced signal swing and barely turn-on resistance of MOS switch.In addition,by carefully selecting transistor size and threshold voltage,one could minimize the overall power consumption with the design trade-off between speed(dynamic power consumption)and leakage current(static power consumption).

This brief aims at enhancing SAR ADC power ef?-ciency by pushing down the supply voltage to0.3V and proposing low-voltage design techniques.For low voltage design,the simplest SAR architecture is preferred and em-ployed in this work,as shown in Fig. 1.Asynchronous clocking helps frequency scaling because only one external sampling clock is required.To overcome the non-linearity degraded by weakly turn-on switch,a new advanced double-boosted sample-and-hold(S/H)is proposed.In addition, a merge-and-split(MS)switching DAC without common-mode voltage shift is developed to reduce the switching energy of DAC network by83%compared to conventional one.Consid-ering leakage current,asymmetric logics and multi-threshold MOS devices are employed for the optimal SAR control logics with trade-off of speed and leakage power.

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Fig.2.Block diagram of the proposed10-bit asynchronous SAR ADC.

The paper is organized as follows.Section II introduces the MS switching method,and Section III describes the design and implementation of the SAR ADC.Measurement results are shown in Section IV and conclusions are given in Section V.

II.P ROPOSED ADC A RCHITECTURE

Fig.2shows the schematic of the proposed10-bit asyn-chronous SAR ADC.To suppress supply voltage noise and have good common-mode noise rejection,the fully differential architecture is employed.The DAC array is used as sampling capacitor and its MSB capacitor is split into sub-arrays.Thus, the DAC array is composed of two identical sub-DAC arrays called and,which are connected to and at sampling phase,respectively.By doing so, the DAC arrays can be switched on the opposite side,and maintain constant common-mode voltage at conversion phase. In addition,local boosted switches(,–9,11–19) are implemented for MS switching,and only two reference voltages of(VDD)and(gnd)are required.

Fig.3(a)CAS DAC switching[2]with a4-bit ex-ample.Since the implementation is symmetrical,only the

condition is illustrated for simplicity.During the sampling phase,the input signals are sampled onto the top plates of DAC,while and are reset to and and are reset to0.After the sampling phase,comparator makes?rst decision directly without switching any capacitor,and the result is

(for).Then,the2C of and are switched to0and to generate a1/2shift on top plates.If,the necessary 1/4shift on top plates is accomplished by switching the1C of and to0and,respectively. Nevertheless,If, the required1/4shift on top plates is accomplished by merging the2C in and.The same procedure is conducted until the bit is?nished.

Fig.3(b)shows the proposed MS DAC switching with a4-bit example.During the sampling phase,the input signals are sam-pled onto the top plates of DAC,while and

are reset to and and are reset to0.Next, the comparator makes?decision directly,and the result is (for).Then,all the capacitors of and are merged to generate a1/2shift on plates.If,the necessary1/4shift on top plates is accomplished by split-ting the2C in and and switching them to0and,respectively.Nevertheless,If

,the required1/4shift on top plates is accomplished by merging the2C in and.The same procedure is conducted until the bit is resolved.

The quantitative energy consumption of CAS and MS methods in each switching step is also shown in the Fig.3.In the most energy-wasting switching(?rst step switching),the MS switching applies merging operation instead of switching the2C to and0,respectively,and the energy consumption is instead of.In the following switching step, either the merging operation or the new introduced splitting operation is employed to accomplish successive approximation. For an n-bit SAR ADC,if the probability of each digital output code is equal,the average switching energy of conven-tional[3],CAS[2],monotonic[3],-based[4]methods can be derived as

(1)

(2)

(3)

(4) The average switching energy for an n-bit SAR ADC using the proposed MS switching procedure can be derived as

(5) However,the CAS and MS switching consume reset energy, which can be derived as

(6) For a10-bit case,the CAS,set-and-down,and-based switching procedures consume88.6,255.5and170.2, respectively,while the proposed MS switching consumes only21.6.Although the CAS and MS switching methods energy than the monotonic and-based switching methods during the conversion phase,they must be pre-charged at the sampling phase and consume reset energy,which is255.5.Fig.4shows the

Fig.3.(a)A4-bit conversion example of the CAS DAC switching method.(b)A4-bit conversion example of the proposed MS DAC switching method. switching energy curves versus output code of MS switching

and the other well-known techniques including both sampling

Compared to set-and-down(255.5)and CAS(344.1

)techniques,MS(233.9)switching consumes

8.5%and32%less energy,respectively.It also solves the

common-mode voltage variation issue of set-and-down and

hence obviates the distortion at conversion phase.Although

-based switching(170.2)is the most energy-ef?cient

among all techniques,realizing the required extra reference

voltage()at0.3V is arduous.Considering the required

unit capacitors,MS switching is the same as the other methods

and is half of the conventional one.

Assuming the bottom-plate voltage of the being switched ca-

pacitor on the p-side is and the one on the n-side is

,as shown in Fig.5(a).merging operation,assuming

Fig.4.Switching energy versus output code.

TABLE I

C OMPARISON OF

D IFFERENT S WITCHING P

ROCEDURES

Fig.5.DAC switching voltage (a)before merging operation.(b)After merging operation.

the capacitor is equal to ,the voltages on both

side then can be as

(7)

,where is the sum of total capacitors

.Hence,the voltage change on top plates

is

(8)

Considering the

noise,assuming the is disturbed by noise and becomes before operation,then the merged voltage would have shift from ideal value,making input voltage shift of

(9)

However,the voltage change on top plates is still the same as ideal case.That is,the reference voltage variation only causes input common-mode voltage variation during merging operation.Then considering the splitting operation,the is splitting ?rst and the and are connected to constant voltages,respectively to Fig.5(a)].The common-mode voltage shift caused by merging operation is erased and be-comes the same as the condition before merging operation.In addition,to reduce comparator input common-mode voltage variation,the

switch sizes of on both sides are designed the same to cancel out the charge-injection and clock feedthrough effects.

During comparison phase,the noise would couple to the comparator input via DAC array and the mount depends on

Fig.6.DAC array of the proposed MS switching.

the number of capacitors connected to .Therefore,different switching sequence would induce different noise pro ?le.Taking the proposed MS switching as an example,at ?rst comparison the noise on the top plates is 0,because the noises on p-side and n-side are common-mode and canceled out,as shown in Fig.3(b).At second comparison,if

,the noise on the top plates is .

Nevertheless,if ,the noise on the top becomes .However,by care-fully examining the switching CAS and MS tech-niques,as shown in Fig.3,each switching step has the same

noise.This is true for -base and monotonic as well.Hence,the linearity degradation due to noise is the same for all these switching methods.Besides the noise,the mismatch of capacitive DAC array is a main error source which deteriorates ADC linearity.For matching concerns,a large capacitor in the DAC array is usually composed of multiple identical unit capacitors.Due to process variation,the practical capacitance of each unit capacitor devi-ates from the nominal value.Suppose the unit capacitor is mod-eled with a nominal value of and a standard deviation of .Therefore,for n-bit ADC with MS switching,the capacitance of each capacitor,shown in Fig.6can be expressed as:

(10)

where i is an integer representing the bit position,

is the unit capacitance and is the error term.Assuming that the error dis-tributions of unit capacitors are independent and identically dis-tributed (i.i.d.)Gaussian random variables,the mean and vari-ance of the error terms are

(11)

The differential input voltage of the comparator before it makes the last decision (i.e.,all bits are decided except the LSB)can be expressed as

(12)

where

is the digital estimation,represents the comparator decision for the nth bit (or 1),is

the input signal difference,and is the reference voltage. Subtracting the nominal value yields the error INL

(13) with variance

(14) For the proposed MS switching procedure,MSB is determined mismatch-independently,and worst cases INL occur at the VFS/4and3VFS/4,where VFS means the full scale signal.At these two transitions,the most capacitors are switched.Therefore,the variance of maximum INL error is derived as

(15) Therefore,the maximum INL of MS switching is

(16) The DNL is the difference of two adjacent codes expressed as

(17) The maximum DNL of MS switching is the code distance between the middle code transition and its previous one.The error term of middle code is generated at the MSB decision and it is error free with top-plate sampling.Therefore,the variance of the maximum DNL error is derived

as Fig.7.Static performance with a SAR ADC using CAS switching method and MS switching method.

(18)

Therefore,the maximum DNL of MS switching is

(19) The same derivation procedures are applied to CAS switching,and the maximum INL and DNL can be expressed as(20)and(21).

(20)

(21) To verify the theoretical analysis above,behavioral simu-lations for a10-bit SAR ADC with CAS and MS switching were developed.The only error source is the random mismatch of capacitors and each capacitor cell has a Gaussian random error with a standard deviation of3%.Fig.7shows the root-mean-square(rms)of DNL and INL of10000Monte-Carlo runs.As expected,the worst DNL is at the middle code and the worst INL occurs at the VFS/4and3VFS/4for both CAS and MS switching.The DNL of MS switching is better than CAS switching by a factor of and the INL by a factor of. Therefore,for the same peak DNL and INL,MS switching can use smaller unit capacitor than CAS switching.

III.I MPLEMENTATION OF K EY B UILDING B LOCKS

The fundamental building blocks of the proposed MS switching ADC are two S/H circuits,a dynamic comparator, SAR control logics,and two capacitive DAC networks.The de-tailed design consideration of the building blocks are described in the following subsections.

A.Double-Bootstrapped Sample-and-Hold

The double-bootstrapped switch shown in Fig.8performs the S/H function.With the bootstrapped switch,the gate-source voltage of the sampling transistors(and)are?xed at the double supply voltage,which makes the on-resistance a small constant value and thus improves the switch linearity. When is high,and are pre-charged to VDD.After becomes low,and are connected in series by a low threshold PMOS to improve boosting speed.The transient

Fig.8.Double-bootstrapped

sample-and-hold.

Fig.9.Transient simulation of S/H turn-on speed with low Vt and with stan-dard Vt at the SS

corner.

Fig.10.Transient simulation of S/H at the FF

corner.

Fig.11.Simulated FFT plot of S/H at the FF corner.

simulation of the worst case (SS corner)is shown in Fig.9.

Under the same sampling clock,the turn-on speed with low Vt

can improve 15%compared to normal Vt one.

In addition,operating at low sampling frequency,the holding voltage on DAC array will be degraded due to the leakage current.The transient simulation of conventional double-boot-strapped S/H [14]with two switch sizes (half width and double length for equal resistance)operated at the FF corner is dis-played in Fig.10.The common used method of stacked MOS (and )[12]is also shown in Fig.10.The

leakage

Fig.12.(a)Simple S/H circuit.(b)Transient simulation of negative gate bias and negative body bias at the FF corner.

current of stacked MOS is slightly smaller than the one of double length.However,because of large leakage current,the holding voltage changes larger than 1LSB.With an input signal of common-mode voltage 0.15V and amplitude 0.3Vpp,Fig.11shows the simulated FFT plot of S/H at the FF corner.Although the stacked MOS can improve linearity,the ENOB (6.16bit)and SFDR (39.78dB)are still not enough for 10-bit ADC.Therefore,a modi ?ed S/H should be introduced to achieve 10-bit linearity under 0.3V supply.By adding three MOS and one capacitor ,the negative holding voltage is implemented.From simulation shown in Fig.10,the leakage current of is reduced from 90pA to 40pA under

small drain-to-source voltage

of and the leakage current is kept small under large voltage of as well.As the FFT plot of Fig.11shows,the ENOB and SFDR of the proposed double-bootstrapped S/H are improved to 12.3bit and 75.84dB,respective.To compare the difference of the proposed negative gate bias and the negative body bias [12],the circuit shown in Fig.12(a)is used for transient simulation.Assuming V out is initially 0V ,when Vg is 0.3V and Vb is 0V (negative gate bias),the leakage current is 70fA and keeps constant.However,with the negative body bias case (Vg is 0V and Vb is 0.3V),the leakage current is between 40pA to 220pA and oscillates with input frequency.Since the threshold voltage of the sampling switch depends on input voltage,the negative body bias would cause input-dependent non-linearity and its resultant ENOB and SFDR with Nyquist rate input are 7.66bit and 48.86dB,respectively.

B.Dynamic Comparator With Dummy Input Pair

The conventional dynamic latch typed comparator,shown in Fig.13is employed for no static current consumption.When is low,and is high,the comparator is at reset phase,and the comparator outputs and are pull high.In addi-tion,the drain and source of input pair (and )are also reset to VDD to cancel out the coupling effect of and ,and make each comparison have the same initial When becomes high and becomes low,the com-parison starts,and the voltage of

are pulled from VDD to

Fig.13.Schematic of dynamic

comparator.

Fig.14.Transient simulation of dynamic comparator.

gnd rapidly.Hence,the input common-mode voltage is cou-pled down by

and degrades ADC linearity.To resolve this problem,a input pair is employed,as shown in Fig.13.The voltage of is reset to gnd and go to VDD at the be-ginning of comparison,which makes an opposite coupling ef-fect and maintains the input common-mode voltage constant.Fig.14shows the transient simulation of dynamic comparator.The input common-mode voltage variation of the comparator with dummy pair is 38.8%less than the one without dummy pair,and at reset phase,it can rapidly recover to 150mV with reset switch .In addition,the differential input voltage variation with dummy pair is less than the one without dummy pair as well.

C.SAR Controls With Asymmetric Logic

Fig.15shows a timing diagram of the proposed SAR ADC.At the rising edge of ,is sampled onto the DAC

array,and after the falling edge of

,the ADC starts bit conversion by triggering the ?rst rising edge of comparison clock .Beyond this point,the ADC operates in asyn-chronous mode and the

signal indicates the completion of comparisons by its edges,and the decision result

is passed to SAR Controls directly to increase DAC

settling time.As soon as the ADC ?nishes AD conversion,the ADC enters sleep mode.The self-power gating proposed in [10]can only reduce the leakage current at sleep phase.However,in a full rate SAR ADC,the duration of sleep phase is nearly zero,so the power gating is helpless.In this work,we propose a new technique to reduce the leakage current at active phase by employing asymmetric logic.Fig.16shows the waveform of one bit SAR control.The initial value of SAR control is reset to low,and the equivalent resistance of PMOS

(turn-off)dominates the leakage current.after SAR switching,

the waveform would become high and the leakage current is

Fig.15.Timing diagram of the proposed SAR ADC.

Fig.16.Waveform of one bit SAR control.

determined by .By increase the resistance of ,the leakage current is reduced after SAR switching with the penalty of slower reset speed.In the SAR logic implementation of this work,high Vt devices are used to replace normal Vt devices to increase instead of increasing gate length.Because all the SAR controls are reset at the same time,the conversion speed only degrades slightly.From simulation,the design with asymmetric logic can reduce about 20%power consumption of SAR controls with only 3%degradation of maximum sampling frequency.

D.Capacitive DAC Network

The ?nger typed metal-oxide-metal (MOM)[9]unit capac-itor is used in the DAC network.A 3-bit DAC network layout with previous proposed structure,shown in Fig.17(a)has large routing error because the routing line near the DAC array has

larger parasitic capacitance

,resulting in unequal unit capacitance.To reduce this routing error,the routing lines should be far enough to have little parasitic ca-pacitance.However,the large distance increase the chip area and bottom-plate parasitic capacitance,which increases DAC settling time and power consumption.Instead of increasing dis-tance,this work proposes a modi ?ed ?nger typed MOM capac-itor,shown in Fig.17(b).The shielding structure is incorporated into the unit capacitor,which not only increases the unit ca-pacitance but also reduces the undesired parasitic capacitance.The unit capacitor of the proposed SAR ADC is composed of

TABLE II

P ERFORMANCE C OMPARISON W ITH S TATE -OF -THE -A RT W

ORKS

https://www.wendangku.net/doc/4e18371662.html,yout of 3-bit DAC network.(a)Finger typed metal-oxide-metal

(MOM)unit capacitor.(b)Modi ?ed ?nger typed metal-oxide-metal (MOM)unit

capacitor.

Fig.18.Die photograph of the proposed SAR

ADC.

Fig.19.Measured DNL and INL at 90kS/s (0.3V).

M4-to-M7layers and has a unit capacitance about 2fF for ca-pacitor matching and kT/C noise consideration.Therefore,the

total sampling capacitance of one capacitor network is 1pF.The two capacitive DAC networks occupy a total active area of ,about 22%of the whole ADC.

IV .M EASUREMENT R ESULTS

The proposed 10-bit MS switching SAR ADC was fabricated in 90nm CMOS technology and the die photograph is shown in Fig.18with a core area of 0.031.A.Static Performance

The static performance of the proposed ADC is evaluated by using a histogram test after applying a slow sinusoid input.Op-erating at 0.3V and 90kS/s,the measured DNL and INL are

and ,respec-tively,as shown in Fig.19.The DNL and INL of proposed MS

switching are worse than those of CAS switching [2],shown in Table II,mainly because of unit capacitance scaling (5fF to 2fF).Theoretically,the DNL and INL would be 2.5times larger.However,thanks to the DNL and INL improvement induced in Section II,and the proposed modi ?ed ?nger typed MOM capac-itor,the DNL and INL (0.38LSB and 0.68LSB)are only 1.12and 1.29times larger than those (0.34LSB and 0.51LSB)of CAS switching,respectively.B.Dynamic Performance

Fig.20shows the measured fast Fourier transform (FFT)plots with an input frequency of close to Nyquist frequency.The resultant SNDR at 90kS/s,600kS/s,and 2MS/s are 52.18dB,55.21dB,and 55.79dB,respectively,and the corresponding ENOB are 8.38bit,8.88bit,and 8.97bit,respective.In addi-tion,all of measured SFDR are above 78dB,which proves the proposed double-bootstrapped S/H has good linearity under low supply voltage.

Fig.21illustrates the SNDR and SFDR as a function of input frequency for supply voltage of 0.3V–0.5V.The SNDR drops within 0.3dB when the input frequency is increased to Nyquist

Fig.20.Measured spectrum and SNDR/SFDR of near Nyquist-rate input at (a)90kS/s.(b)600kS/s.(c)2

MS/s.

Fig.21.

Measured SNDR&SFDR as a function of input frequency (–0.5V).

Fig.22.The power distribution of the prototype for .

frequency,so the effective resolution bandwidth (ERBW)is higher than Nyquist frequency.

C.Power Consumption and Comparisons

The measured total power dissipation at 0.3V supply is 35nW with 11.7%in the S/H,14%in the comparator,28.1%in the DAC,and 46.2%in the digital SAR logics,as shown in Fig.22.The total power consumption at 0.4V and 0.5V supply are 372nW and 1.8,respectively.

To compare the proposed ADC with other state-of-the-art SAR ADCs,the ?gure-of-merit (FOM)is used.

(22)

where is the sampling frequency,ERBW is the effective res-olution bandwidth,and ENOB is the effective number of bits at a Nyquist input.

Table II shows a summary of the measured performance and a comparison to other state-of-the-art works.With the proposed MS technique and corresponding design for low supply voltage,the prototype achieves a best FOM of 1.17fJ/conversion-step at 0.3V and https://www.wendangku.net/doc/4e18371662.html,pared to other low-power SAR ADCs,this work with a wide sampling frequency range of 90kS/s-to-2

MS/s presents FOMs of 1.17-to-1.78fJ/conversion-step at 0.3V-to-0.5V supply and can operate at the lowest supply voltage for 10-bit resolution.

V .C ONCLUSION

In this paper,a 10-bit SAR ADC for biomedical system or sensor network is presented.The proposed energy-ef ?cient MS switching procedure reduces the DAC power consump-tion without common-mode voltage shift and extra reference voltage.In addition,the new proposed double-bootstrapped S/H improves sampling linearity under ultra-low voltage of 0.3V.The modi ?ed comparator enhances comparison accuracy,and the ?nger typed MOM capacitor with shielding structure is employed to reduce parasitic capacitance and increase unit capacitance.Furthermore,the asymmetric logic is proposed to take trade-off between leakage current and operation speed at conversion phase.The prototype ADC occupies an active area of 0.031,and achieves 90kS/s-to-2MS/s operation speeds with FOMs of 1.17-to-1.78fJ/conversion-step at 0.3V-to-0.5V supply.

A CKNOWLEDGMENT

The authors thank MediaTek for supporting of this work and National Chip Implementation Center (CIC)for fabrication of the test chip.

R EFERENCES

[1]W.Y.Pang,C.S.Wang,Y.K.Chang,N.K.Chou,and C.K.Wang,“A

10-bit 500-KS/s low power SAR ADC with splitting capacitor for bio-medical applications,”in Proc.IEEE Asian Solid-State Circuits Conf.,Nov.2009,pp.149–152.

[2]C.-Y.Liou and C.-C.Hsieh,“A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS,”in IEEE ISSCC Dig.Tech.Papers ,Feb.2013,pp.280–281.[3]C.C.Liu,S.J.Chang,G.Y.Huang,and Y.Z.Lin,“A 10-bit 50-MS/s

SAR ADC with a monotonic capacitor switching procedure,”IEEE J.Solid-State Circuits ,vol.45,no.4,pp.731–740,Apr.2010.

[4]Y.Zhu,C.-H.Chan,U.-F.Chio,S.-W.Sin,S.-P.U,R.P.Martins,and

F.Maloberti,“A 10-bit 100-MS/s reference-free SAR ADC in 90nm CMOS,”IEEE J.Solid-State Circuits ,vol.45,no.6,pp.1111–1121,Jun.2010.

[5]C.H.Kuo and C.E.Hsieh,“A high energy-ef ?ciency SAR ADC based

on partial ?oating capacitor switching technique,”in Proc.IEEE ESS-CIRC ,2011,pp.475–478.

[6]P.Harpe,E.Cantatore,and A.van Roermund,“A 2.2/2.7fJ/conver-sion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction,”in IEEE ISSCC Dig.Tech.Papers ,Feb.2013,pp.270–271.

[7]M.Ahmadi and W.Namgoong,“A 3.3fJ/conversion-step 250kS/s 10

b SAR ADC using optimized vote allocation,”in Proc.IEEE Custom Integr.Circuits Conf.(CICC),Sep.2013,pp.1–4,22–25.

[8]H.-Y.Tai,H.-W.Chen,and H.-S.Chen,“A 3.2fJ/c.-s.0.35V 10b 100

KS/s SAR ADC in 90nm CMOS,”in Proc.IEEE Symp.VLSI Circuits ,Jun.2012,pp.92–93,13–15.

[9]P.J.A.Harpe,C.Zhou,Y.Bi,N.P.v.d.Meijs,X.Wang,K.Philips,

G.Dolmans,and H.D.Groot,“A 268bit 10MS/s asynchronous SAR ADC for low energy radios,”J.Solid-State Circuits ,vol.46,no.7,pp.1585–1595,Jul.2011.

[10]R.Sekimoto,A.Shikata,K.Yoshioka,T.Kuroda,and H.Ishikuro,

“A 0.5-V 5.2-fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650pW by boosted self-power gating in 40-nm CMOS,”IEEE J.Solid-State Circuits ,vol.48,no.11,pp.2628–2636,Nov.2013.

[11]H.-Y.Tai,Y.-S.Hu,H.-W.Chen,and H.-S.Chen,“A 0.85fJ/conver-sion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS,”in IEEE ISSCC Dig.Tech.Papers ,Feb.2014,pp.196–197.

[12]X.Zhou and Q.Li,“A 160mV 670nW 8-bit SAR ADC in 0.13

CMOS,”in Proc.IEEE Custom Integr.Circuits Conf.(CICC),Sep.2012,pp.1–4,9–12.

[13]P.Harpe,G.Dolmans,K.Philips,and H.de Groot,“A 0.7V 7-to-10

bit 0-to-2MS/s ?exible SAR ADC for ultra low-power wireless sensor nodes,”in Proc.IEEE ESSCIRC ,Sep.2012,pp.373–376.

[14]S.-I.Chang,K.Al-Ashmouny,and Y.Euisik,“A0.5V20fJ/conver-

sion-step rail-to-rail SAR ADC with programmable time-delayed con-trol units for low-power biomedical application,”in Proc.IEEE ESS-

CIRC,Sep.2011,pp.

339–342.

Jin-Yi Lin received his B.S.degree in electrical engineering from National Hsing Hua Univer-sity,Taiwan,in2010.Now he is working toward the Ph.D degree.His research interests include mixed analog/digital circuit design,especially in analog-to-digital converters.He currently is involved in the development of low power,small area,and high resolution SAR ADC for biomedical and3D IC

applications.

Chih-Cheng Hsieh received his B.S.,M.S.,and

Ph.D.degrees from the institute of electronics engi-

neering,National Chiao-Tung University,Hsinchu,

Taiwan,in1990,1991,and1997,respectively.

He served with the Army of Taiwan as a Second

Lieutenant from1997–1999.From1999–2007,he

worked with a IC design house,the Pixart Imaging

Inc.,Taiwan,and was involved in the development

of CMOS image sensor ICs for PC,consumer,and

mobile phone applications.He led the Mixed-Mode

IC department as a Senior Manager and helped the company become an IPO successfully in2007.He has proposed many inventions to improve the function and quality of CMOS image sensor ICs, and has been granted12U.S.patents and23Taiwan patents.In2007,he joined the Department of Electrical Engineering,National Tsing-Hua University, Hsinchu,Taiwan,where he is currently an Assistant Professor.

Dr.Hsieh's research interests include CMOS image sensor IC development for biomedical,space,robot,and customized applications;smart sensor IC with array level pre-processing;and low power analog&mixed-mode IC design.

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