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A6B595中文资料

Data Sheet

26185.122

8-BIT SERIAL-INPUT,DMOS POWER DRIVER

The A6B595KA and A6B595KLW combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, sole-noids, and other medium-current or high-voltage peripheral power loads.

The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high.

A CMOS serial-data output enables cascade connections in appli-cations requiring additional drive lines. Similar devices with reduced r DS(on) are available as the A6595KA and A6595KLW.

The A6B595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high.

The A6B595KA is furnished in a 20-pin dual in-line plastic

package. The A6B595KLW is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames,reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C.

FEATURES

s 50 V Minimum Output Clamp Voltage

s 150 mA Output Current (all outputs simultaneously)s 5 ? Typical r DS(on)

s Low Power Consumption

s Replacements for TPIC6B595N and TPIC6B595DW

6B595

ADVANCE INFORMATION

(Subject to change without notice)

January 24, 2000

Always order by complete part number:Part Number Package R θJA

R θJC A6B595KA 20-pin DIP 55°C/W 25°C/W A6B595KLW 20-lead SOIC

70°C/W 17°C/W

6B595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000Copyright ? 1999, Allegro MicroSystems, Inc.

FUNCTIONAL BLOCK DIAGRAM

5075100125150

2.5

0.5

A L L O W A

B L E P A

C K A G E P O W E R

D I S S I P A T I O N I N W A T T S

AMBIENT TEMPERATURE IN °C

2.0

1.5

1.0

Dwg. GS-004A

S U F F

I X

'L W ', R =

70°C /W

θJ A S U F F I X 'A

', R = 5

5°C /W θJ A LOGIC SYMBOL

456714

1516

1718

13Dwg. FP-043

GROUND Dwg. FP-013-4

CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE

(ACTIVE LOW)

SERIAL DATA OUT

SERIAL-PARALLEL SHIFT REGISTER

D-TYPE LATCHES

LOGIC SUPPLY REGISTER

CLEAR

(ACTIVE LOW)

OUT 0OUT N

GROUND

Grounds (terminals 10, 11, and 19) must be connected together externally.

6B595

8-BIT SERIAL-INPUT,DMOS POWER DRIVER

https://www.wendangku.net/doc/551590676.html,

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

SERIAL DATA OUT

LOGIC INPUTS DMOS POWER DRIVER OUTPUT

OUT

RECOMMENDED OPERATING CONDITIONS

over operating temperature range

Logic Supply Voltage Range, V DD ............... 4.5 V to 5.5 V High-Level Input Voltage, V IH ............................ ≥ 0.85V DD Low-level input voltage, V IL ................................. ≤0.15V DD

6B595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

Limits

Characteristic Symbol Test Conditions Min.Typ.Max.Units Output Breakdown V (BR)DSX I O = 1 mA

50——V Voltage Off-State Output I DSX

V O = 40 V, V DD = 5.5 V

—0.1 5.0μA Current

V O = 40 V, V DD = 5.5 V, T A = 125°C

—0.158.0μA Static Drain-Source r DS(on)I O = 100 mA, V DD = 4.5 V

— 4.2 5.7?On-State Resistance

I O = 100 mA, V DD = 4.5 V, T A = 125°C — 6.89.5?I O = 350 mA, V DD = 4.5 V (see note)

— 5.58.0?Nominal Output I ON V DS(on) = 0.5 V, T A = 85°C —90—mA Current

Logic Input Current

I IH V I = V DD = 5.5 V —— 1.0μA I IL

V I = 0, V DD = 5.5 V ——-1.0μA SERIAL-DATA V OH

I OH = -20 μA, V DD = 4.5 V 4.4 4.49—V Output Voltage

I OH = -4 mA, V DD = 4.5 V

4.0 4.2—V V OL I OL = 20 μA, V DD = 4.5 V —0.0050.1V I OL = 4 mA, V DD = 4.5 V

—0.30.5V Prop. Delay Time

t PLH I O = 100 mA, C L = 30 pF —150—ns t PHL

I O = 100 mA, C L = 30 pF —90—ns Output Rise Time t r I O = 100 mA, C L = 30 pF —200—ns Output Fall Time t f I O = 100 mA, C L = 30 pF —200—ns Supply Current

I DD(OFF)V DD = 5.5 V, Outputs OFF —20100μA I DD(ON)V DD = 5.5 V, Outputs ON

—150300μA I DD(fclk)

f clk = 5 MHz, C L = 30 pF, Outputs OFF

—

0.4

5.0

Typical Data is at V DD = 5 V and is for design information only.NOTE — Pulse test, duration ≤100 μs, duty cycle ≤2%.

ELECTRICAL CHARACTERISTICS at T A = +25°C, V DD = 5 V, t ir = t if ≤ 10 ns (unless otherwise specified).

6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER

https://www.wendangku.net/doc/551590676.html, TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are V DD and Ground)

OUT

Dwg. WP-029-2

OUT

Dwg. WP-030-2

A.Data Active Time Before Clock Pulse

(Data Set-Up Time), t su(D).......................................... 20 ns B.Data Active Time After Clock Pulse

(Data Hold Time), t h(D).............................................. 20 ns

C.Clock Pulse Width, t w(CLK)............................................. 40 ns

D.Time Between Clock Activation

and Strobe, t su(ST)....................................................... 50 ns

E.Strobe Pulse Width, t w(ST).............................................. 50 ns

F.Output Enable Pulse Width, t w(OE)................................ 4.5 μs NOTE – Timing is representative of a 12.5 MHz clock.

Higher speeds are attainable.

Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT.

Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion).

When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches.

6B595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

TEST CIRCUITS

I V Single-Pulse Avalanche Energy Test Circuit

and Waveforms

E AS = I AS x V (BR)DSX x t AV /2

6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER

https://www.wendangku.net/doc/551590676.html, TERMINAL DESCRIPTIONS

Terminal No.Terminal Name Function

1NC No internal connection.

2LOGIC SUPPLY(V DD) The logic supply voltage (typically 5 V).

3SERIAL DATA IN Serial-data input to the shift-register.

4-7OUT0-3Current-sinking, open-drain DMOS output terminals.

8CLEAR When (active) low, the registers are cleared (set low).

9OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all

output drivers are turned OFF (blanked).

10GROUND Reference terminal for output voltage measurements (OUT0-3).

11GROUND Reference terminal for output voltage measurements (OUT0-7).

12STROBE Data strobe input terminal; shift register data is latched on rising edge.

13CLOCK Clock input terminal for data shift on rising edge.

14-17OUT4-7Current-sinking, open-drain DMOS output terminals.

18SERIAL DATA OUT CMOS serial-data output to the following shift register.

19GROUND Reference terminal for input voltage measurements.

20NC No internal connection.

NOTE — Grounds (terminals 10, 11, and 19) must be connected together externally.

6B595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

A6B595KA

Dimensions in Inches (controlling dimensions)

Dimensions in Millimeters (for reference only)

NOTES:1.Exact body and lead configuration at vendor’s option within limits shown.

2.Lead spacing tolerance is non-cumulative

3.Lead thickness is measured at seating plane or below.

Dwg. MA-001-20 in

Dwg. MA-001-20 mm

6B595

8-BIT SERIAL-INPUT,DMOS POWER DRIVER

https://www.wendangku.net/doc/551590676.html,

A6B595KLW

Dimensions in Inches (for reference only)

Dimensions in Millimeters (controlling dimensions)

Dwg. MA-008-20 mm

1.27

BSC

NOTES:1.Exact body and lead configuration at vendor’s option within limits shown.

2.Lead spacing tolerance is non-cumulative.

6B595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

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6B595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

This page intentionally left blank

https://www.wendangku.net/doc/551590676.html,

6B595

8-BIT SERIAL-INPUT,

DMOS POWER DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be

required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi-bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.