当前位置：文档库 › Am75DL9608HGT70IT中文资料

Am75DL9608HGT70IT中文资料

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-inally developed the specification, these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate,and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

Am75DL9608HG

Data Sheet

Publication Number 30772 Revision A Amendment +1 Issue Date November 17, 2003

THIS PAGE LEFT INTENTIONALLY BLANK.

ADVANCE INFORMATION

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. 11/18/03

Publication# 30772Rev:A Amendment/+1Issue Date: November 17, 2003

Refer to AMD’s Website (https://www.wendangku.net/doc/572576380.html,) for the latest information.

Am75DL9608HG

Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM

64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM DISTINCTIVE CHARACTERISTICS

MCP Features

■Power supply voltage of 2.7 to 3.3 volt ■High performance

—Flash access time as fast as 70 ns

—Pseudo SRAM access time as fast as 55 ns

■Package

—73-Ball FBGA

■Operating Temperature

—–40°C to +85°C

Flash Memory Features

(Am29DL640H/Am29DL320G)

—Features apply to Am29DL640H and Am29DL320G

independently.

ARCHITECTURAL ADVANTAGES ■Simultaneous Read/Write operations

—Data can be continuously read from one bank while

executing erase/program functions in another bank. —Zero latency between read and write operations

■Flexible Bank ? architecture

—Read may occur in any of the three banks not being written

or erased.

—Four banks may be grouped by customer to achieve desired

bank divisions.

■Manufactured on 0.17 μm process technology

(Am29DL320G), 0.13 μm process technology (Am29DL640H)■SecSi? (Secured Silicon) Sector

—Extra 256 byte sector on Am29DL640H —Extra 256 byte sector on Am29DL320G

—Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data

—Customer lockable: Sector is one-time programmable. Once

sector is locked, data cannot be changed.

■Zero Power Operation

—Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero.

■Boot sectors

—Top and bottom boot sectors in Am29DL640H —Top or bottom boot options in Am29DL320G

■Compatible with JEDEC standards

—Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS ■High performance

—Access time as fast as 70 ns

—Program time: 4 μs/word typical utilizing Accelerate function

■Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz —10 mA active read current at 5 MHz

—200 nA in standby or automatic sleep mode

■Minimum 1 million erase cycles guaranteed per sector ■20 year data retention at 125°C

—Reliable operation for the life of the system

SOFTWARE FEATURES

■Supports Common Flash Memory Interface (CFI)■Program/Erase Suspend/Erase Resume

—Suspends program/erase operations to allow

programming/erasing in same bank

■Data# Polling and Toggle Bits

—Provides a software method of detecting the status of

program or erase cycles

HARDWARE FEATURES

■Any combination of sectors can be erased ■Ready/Busy# output (RY/BY#)

—Hardware method for detecting program or erase cycle

completion

■Hardware reset pin (RESET#)

—Hardware method of resetting the internal state machine to

the read mode

■WP#/ACC input pin

—Write protect (WP#) protects sectors 0, 1, 140, and 141 in

Am29DL640H, and two outermost boot sectors in Am29DL320G

—Acceleration (ACC) function accelerates program timing

■Sector protection

—Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or erase operation within that sector

—Temporary Sector Unprotect allows changing data in

protected sectors in-system

Pseudo SRAM Features

■Power dissipation

—Operating: 30 mA maximum —Standby: 60 μA maximum

■CE1s# and CE2s Chip Select

■Power down features using CE1s# and CE2s ■Data retention supply voltage: 2.7 to 3.3 volt

■Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

GENERAL DESCRIPTION

The Am75DL9608HG consists of two flash memory devices (one 64-Mbit Am29DL640H and one 32-Mbit Am29DL320G), and one 8 Mbit pseudo SRAM device. Am29DL640H and Am29DL320G Features

Am29DL640H is a 64megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words. The Am29DL320G is a 32megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words. Word mode data appears on DQ15–DQ0. The device is de-signed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers.

The device is available with an access time of 70 or 85 ns and is offered in a 73-ball FBGA package. Standard control pins—chip enable (CE#fx), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for the program and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. Sector addresses are fixed, system software can be used to form user-defined bank groups.

During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im-prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

The Am29DL640H can be organized as both a top and bottom boot sector configuration.

The Am29DL320G can be organized as either a top or bottom boot sector configuration. Top boot configura-tion is shown in the following table.Bottom boot configuration is shown in the following ta-ble.

Available on Am29DL640H and Am29DL320G, the SecSi? (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The Secure Sector SecSi Indica-tor Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part.

Factory locked parts provide several options. The Se-cure SectorSecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash ser-vice), or both. Customer Lockable parts may utilize the Secure SectorSecSi Sector as a one-time programma-ble area.

The AMD DMS (Data Management Software) man-ages data programming, enables EEPROM emulation, and eases historical sector erase flash limitations. For more information on DMS or to obtain the software, contact AMD or an authorized representative.

The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device sta-tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode.

The sector erase architecture allows memory sec-tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V CC detector that automatically inhibits write opera-tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem-ory. This can be achieved in-system or via program-ming equipment.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re-duced in both modes.

Bank Megabits Sector Sizes

Bank 18 Mb

Eight 4 Kword, Fifteen 32 Kword

Bank 224 Mb Forty-eight 32 Kword Bank 324 Mb Forty-eight 32 Kword

Bank 48 Mb

Eight 4 Kword, Fifteen 32 Kword

Bank Megabits Sector Sizes

Bank 1 4 Mb

Eight 4 Kword, Seven 32 Kword

Bank 212 Mb T wenty-four 32 Kword Bank 312 Mb T wenty-four 32 Kword Bank 4 4 Mb Eight 32 Kword

Bank Megabits Sector Sizes Bank 1 4 Mb Eight 32 Kword Bank 212 Mb Twenty-four 32 Kword Bank 312 Mb Twenty-four 32 Kword

Bank 4 4 Mb

Eight 4 Kword,

Seven 32 Kword

2Am75DL9608HG November 17, 2003

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Memory Block Diagram . . . . . . . . . . . . . . . 7 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8 Special Package Handling Instructions (8)

Ordering Information . . . . . . . . . . . . . . . . . . . . . .10 MCP Device Bus Operations . . . . . . . . . . . . . . . .10 Table 1. Device Bus Operations—Flash Word Mode (11)

Flash Device Bus Operations . . . . . . . . . . . . . . .12 Requirements for Reading Array Data (12)

Writing Commands/Command Sequences (12)

Simultaneous Read/Write Operations with Zero Latency (12)

Automatic Sleep Mode (13)

RESET#: Hardware Reset Pin (13)

Output Disable Mode (13)

Table 2. Am29DL640H Sector Architecture (14)

Table 3. Am29DL640H Bank Address (17)

Table 4. Am29DL640H SecSi? Sector Addresses (17)

Table 5. Am29DL320G Top Boot Sector Addresses (18)

Table 6. Am29DL320G Top Boot SecSi TM Sector Addresses (19)

Table 7. Am29DL320G Bottom Boot Sector Addresses (20)

Table 8. Am29DL320G Bottom Boot SecSi TM Sector Addresses (21)

Table 9. Am29DL640H Boot Sector/Sector Block

Addresses for Protection/Unprotection (22)

Table 10. Am29DL320G Top Boot Sector/Sector

Block Addresses for Protection/Unprotection (23)

Table 11. Am29DL320G Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection (23)

Write Protect (WP#) (24)

Table 12. WP#/ACC Modes (24)

Temporary Sector Unprotect (24)

Figure 1. Temporary Sector Unprotect Operation (25)

Figure 2. In-System Sector Protect/Unprotect Algorithms (26)

SecSi? (Secured Silicon) Sector

SectorFlash Memory Region (27)

Table 13. SecSi Sector Programming (27)

Figure 3. SecSi Sector Protect Verify (28)

Hardware Data Protection (28)

Common Flash Memory Interface (CFI) . . . . . . .28 Table 14. Am29DL640H CFI Query Identification String (29)

Table 15. Am29DL640H System Interface String (29)

Table 16. Am29DL640H Device Geometry Definition (30)

Table 17. Am29DL640H Primary Vendor-Specific

Extended Query (31)

Table 18. Am29DL320G CFI Query Identification String (32)

Table 19. Am29DL320G System Interface String (32)

Table 20. Am29DL320G Device Geometry Definition (33)

Table 21. Am29DL320G Primary Vendor-Specific

Extended Query (34)

Flash Command Definitions . . . . . . . . . . . . . . . .35 Reading Array Data (35)

Reset Command (35)

Autoselect Command Sequence (35)

Enter SecSi? Sector/Exit SecSi Sector

Command Sequence (35)

Program Command Sequence (36)

Figure 4. Program Operation (37)

Chip Erase Command Sequence (37)

Sector Erase Command Sequence (37)

Figure 5. Erase Operation (38)

Erase Suspend/Erase Resume Commands (38)

Table 22. Am29DL640H and Am29DL320G Command Definitions 39 Flash Write Operation Status . . . . . . . . . . . . . . . 40 DQ7: Data# Polling (40)

Figure 6. Data# Polling Algorithm (40)

DQ6: Toggle Bit I (41)

Figure 7. Toggle Bit Algorithm (41)

DQ2: Toggle Bit II (42)

Reading Toggle Bits DQ6/DQ2 (42)

DQ5: Exceeded Timing Limits (42)

DQ3: Sector Erase Timer (42)

Table 23. Write Operation Status (43)

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 44 Figure 8. Maximum Negative Overshoot Waveform (44)

Figure 9. Maximum Positive Overshoot Waveform (44)

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 45 CMOS Compatible (45)

Figure 10. I CC1 Current vs. Time (Showing Active and

Automatic Sleep Currents) (46)

Figure 11. Typical I CC1 vs. Frequency (46)

Pseudo SRAM DC and

Operating Characteristics . . . . . . . . . . . . . . . . . . 47 Figure 12. Standby Current ISB CMOS (47)

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 13. Test Setup (48)

Figure 14. Input Waveforms and Measurement Levels (48)

Flash AC Characteristics . . . . . . . . . . . . . . . . . . 49 Pseudo SRAM CE#s Timing (49)

Figure 15. Timing Diagram for Alternating

Between Pseudo SRAM to Flash (49)

Read-Only Operations (50)

Figure 16. Read Operation Timings (50)

Hardware Reset (RESET#) (51)

Figure 17. Reset Timings (51)

Erase and Program Operations (52)

Figure 18. Program Operation Timings (53)

Figure 19. Accelerated Program Timing Diagram (53)

Figure 20. Chip/Sector Erase Operation Timings (54)

Figure 21. Back-to-back Read/Write Cycle Timings (55)

Figure 22. Data# Polling Timings (During Embedded Algorithms). 55 Figure 23. Toggle Bit Timings (During Embedded Algorithms) (56)

Figure 24. DQ2 vs. DQ6 (56)

Temporary Sector Unprotect (57)

Figure 25. Temporary Sector Unprotect Timing Diagram (57)

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram (58)

Alternate CE#f Controlled Erase and Program Operations (59)

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings (60)

Pseudo SRAM AC Characteristics . . . . . . . . . . . 61 Power Up Time (61)

Read Cycle (61)

Figure 28. Pseudo SRAM Read Cycle—Address Controlled (61)

Figure 29. Pseudo SRAM Read Cycle (62)

Write Cycle (63)

Figure 30. Pseudo SRAM Write Cycle—WE# Control (63)

Figure 31. Pseudo SRAM Write Cycle—CE1#s Control (64)

Figure 32. Pseudo SRAM Write Cycle—

UB#s and LB#s Control (65)

November 17, 2003Am75DL9608HG3

Flash Erase And Programming Performance . . .66 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 66 BGA Package Capacitance . . . . . . . . . . . . . . . . 66 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . 66 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . .67 FTA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm (67)

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . .68 Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Memory Block Diagram . . . . . . . . . . . . . . . 7 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8 Special Package Handling Instructions (8)

Ordering Information . . . . . . . . . . . . . . . . . . . . . .10 MCP Device Bus Operations . . . . . . . . . . . . . . . .10 Table 1. Device Bus Operations—Flash Word Mode (11)

Flash Device Bus Operations . . . . . . . . . . . . . . .12 Requirements for Reading Array Data (12)

Writing Commands/Command Sequences (12)

Simultaneous Read/Write Operations with Zero Latency (12)

Automatic Sleep Mode (13)

RESET#: Hardware Reset Pin (13)

Output Disable Mode (13)

Table 2. Am29DL640H Sector Architecture (14)

Table 3. Am29DL640H Bank Address (17)

Table 4. Am29DL640H SecSi? Sector Addresses (17)

Table 5. Am29DL320G Top Boot Sector Addresses (18)

Table 6. Am29DL320G Top Boot SecSi TM Sector Addresses (19)

Table 7. Am29DL320G Bottom Boot Sector Addresses (20)

Table 8. Am29DL320G Bottom Boot SecSi TM Sector Addresses (21)

Table 9. Am29DL640H Boot Sector/Sector Block

Addresses for Protection/Unprotection (22)

Table 10. Am29DL320G Top Boot Sector/Sector

Block Addresses for Protection/Unprotection (23)

Table 11. Am29DL320G Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection (23)

Write Protect (WP#) (24)

Table 12. WP#/ACC Modes (24)

Temporary Sector Unprotect (24)

Figure 1. Temporary Sector Unprotect Operation (25)

Figure 2. In-System Sector Protect/Unprotect Algorithms (26)

SecSi? (Secured Silicon) Sector

SectorFlash Memory Region (27)

Table 13. SecSi Sector Programming (27)

Figure 3. SecSi Sector Protect Verify (28)

Hardware Data Protection (28)

Common Flash Memory Interface (CFI) . . . . . . .28 Table 14. Am29DL640H CFI Query Identification String (29)

Table 15. Am29DL640H System Interface String (29)

Table 16. Am29DL640H Device Geometry Definition (30)

Table 17. Am29DL640H Primary Vendor-Specific

Extended Query (31)

Table 18. Am29DL320G CFI Query Identification String (32)

Table 19. Am29DL320G System Interface String (32)

Table 20. Am29DL320G Device Geometry Definition (33)

Table 21. Am29DL320G Primary Vendor-Specific

Extended Query (34)

Flash Command Definitions . . . . . . . . . . . . . . . .35 Reading Array Data (35)

Reset Command (35)

Autoselect Command Sequence (35)

Enter SecSi? Sector/Exit SecSi Sector

Command Sequence (35)

Program Command Sequence (36)

Figure 4. Program Operation (37)

Chip Erase Command Sequence (37)

Sector Erase Command Sequence (37)

Figure 5. Erase Operation (38)

Erase Suspend/Erase Resume Commands (38)

Table 22. Am29DL640H and Am29DL320G Command Definitions 39 Flash Write Operation Status . . . . . . . . . . . . . . . 40 DQ7: Data# Polling (40)

Figure 6. Data# Polling Algorithm (40)

DQ6: Toggle Bit I (41)

Figure 7. Toggle Bit Algorithm (41)

DQ2: Toggle Bit II (42)

Reading Toggle Bits DQ6/DQ2 (42)

DQ5: Exceeded Timing Limits (42)

DQ3: Sector Erase Timer (42)

Table 23. Write Operation Status (43)

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 44 Figure 8. Maximum Negative Overshoot Waveform (44)

Figure 9. Maximum Positive Overshoot Waveform (44)

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 45 CMOS Compatible (45)

Figure 10. I CC1 Current vs. Time (Showing Active and

Automatic Sleep Currents) (46)

Figure 11. Typical I CC1 vs. Frequency (46)

Pseudo SRAM DC and

Operating Characteristics . . . . . . . . . . . . . . . . . . 47 Figure 12. Standby Current ISB CMOS (47)

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 13. Test Setup (49)

Figure 14. Input Waveforms and Measurement Levels (49)

Flash AC Characteristics . . . . . . . . . . . . . . . . . . 50 Pseudo SRAM CE#s Timing (50)

Figure 15. Timing Diagram for Alternating

Between Pseudo SRAM to Flash (50)

Read-Only Operations (51)

Figure 16. Read Operation Timings (51)

Hardware Reset (RESET#) (52)

Figure 17. Reset Timings (52)

Erase and Program Operations (53)

Figure 18. Program Operation Timings (54)

Figure 19. Accelerated Program Timing Diagram (54)

Figure 20. Chip/Sector Erase Operation Timings (55)

Figure 21. Back-to-back Read/Write Cycle Timings (56)

Figure 22. Data# Polling Timings (During Embedded Algorithms). 56 Figure 23. Toggle Bit Timings (During Embedded Algorithms) (57)

Figure 24. DQ2 vs. DQ6 (57)

Temporary Sector Unprotect (58)

Figure 25. Temporary Sector Unprotect Timing Diagram (58)

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram (59)

Alternate CE#f Controlled Erase and Program Operations (60)

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings (61)

Pseudo SRAM AC Characteristics . . . . . . . . . . . 62 Power Up Time (62)

Read Cycle (62)

Figure 28. Pseudo SRAM Read Cycle—Address Controlled (62)

4Am75DL9608HG November 17, 2003

Figure 29. Pseudo SRAM Read Cycle (63)

Write Cycle (64)

Figure 30. Pseudo SRAM Write Cycle—WE# Control (64)

Figure 31. Pseudo SRAM Write Cycle—CE1#s Control (65)

Figure 32. Pseudo SRAM Write Cycle—

UB#s and LB#s Control (66)

Flash Erase And Programming Performance . . .67Latchup Characteristics . . . . . . . . . . . . . . . . . . . 67 BGA Package Capacitance . . . . . . . . . . . . . . . . . 67 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 67 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 68 FTA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm (68)

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 69

November 17, 2003Am75DL9608HG5

6Am75DL9608HG November 17, 2003

PRODUCT SELECTOR GUIDE

MCP BLOCK DIAGRAM

Part Number Am75DL9608HG

Speed Options

Standard Voltage Range: V CC = 2.7–3.3 V

Flash Memory

(Am29DL640H, Am29DL320G)

Pseudo SRAM

75707570Max Access Time (ns)70705570CE# Access (ns)70705570OE# Access (ns)

FLASH MEMORY BLOCK DIAGRAM

* Addresses for Am29DL640H are A21–A0. Address for Am29DL320G are A20–A0.

November 17, 2003Am75DL9608HG7

8Am75DL9608HG November 17, 2003

CONNECTION DIAGRAM

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data

integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

73-Ball FBGA Top View

PIN DESCRIPTION

A18–A0=19 Address Inputs (Common)

A21–A19, A-1 = 4 Address Inputs (Flash)

DQ15–DQ0=16 Data Inputs/Outputs (Common) CE#f1=Flash Chip Enable 1

(Am29DL640H)

CE#f2=Flash Chip Enable 2

(Am29DL320G)

CE#1s=Pseudo SRAM Chip Enable 1

CE2s=Pseudo SRAM Chip Enable 2

OE#=Output Enable (Common)

WE#=Write Enable (Common)

RY/BY#=Ready/Busy Output

UB#s=Upper Byte Control (Pseudo SRAM) LB#s=Lower Byte Control (Pseudo SRAM) RESET#=Hardware Reset Pin, Active Low WP#/ACC=Hardware Write Protect/

Acceleration Pin (Flash)

V CC f=Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage supply

tolerances)

V CC s=Pseudo SRAM Power Supply

V SS=Device Ground (Common)

NC=Pin Not Connected Internally LOGIC SYMBOL

DQ15–DQ0

A18–A0

CE#f1

OE#

WE#

RESET#

UB#s

RY/BY#

WP#/ACC

A21–A19

LB#s

CE1#s

CE2s

CE#f2

November 17, 2003Am75DL9608HG9

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

MCP DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca-tion. The register is a latch used to store the com-mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Am75DL9608HG T75I T

TAPE AND REEL

T=7 inches

S=13 inches

TEMPERATURE RANGE

I =

Industrial

(–40°C to +85°C)

SPEED OPTION

75=70 ns Flash + 55 ns pSRAM

70=70 ns Flash + 70 ns pSRAM (See page 5)

BOOT SECTOR ARCHITECTURE

T=Top Boot of Am29DL320G Flash

B=Bottom Boot of Am29DL320G Flash

PROCESS TECHNOLOGY

H=0.13 μm (Am29DL640H)

G=0.17 μm (Am29DL320G)

PSEUDO SRAM DEVICE DENSITY

8=8Mbits

AMD DEVICE NUMBER/DESCRIPTION

Am75DL9608HG

Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM

Am29DL640H 64 Megabit (8/4 M x 16-Bit) and

Am29DL320G 32 Megabit (4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM

Valid Combinations

Order Number Package Marking

Am75DL9608HGT70I Am75DL9608HGB70I T, S

M750000000

M750000001

Am75DL9608HGT75I Am75DL9608HGB75I T, S

M750000002

M750000003

10Am75DL9608HG November 17, 2003

November 17, 2003Am75DL9608HG 11

Table 1.

Device Bus Operations—Flash Word Mode

Legend: L = Logic Low = V IL , H = Logic High = V IH , V ID = 11.5–12.5 V , V HH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, A IN = Address In, D IN = Data In, D OUT = Data Out Notes:

1.Other operations except for those indicated in this column are inhibited.

2.Do not apply CE#fx = V IL , CE1#s = V IL and CE2s = V IH at the same time.

3.Don’t care or open LB#s or UB#s.

4.If WP#/ACC = V IL , the boot sectors will be protected. If WP#/ACC = V IH the boot sectors protection will be removed.

If WP#/ACC = V ACC (9V), the program time will be reduced by 40%.

5.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

6.If WP#/ACC = V IL , the two outermost boot sectors remain protected. If WP#/ACC = V IH , the two outermost boot sector protection

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V HH, all sectors will be unprotected.

7.Only one flash device should be accessed at a time. For Am29DL640H flash access, CE#f1 = V IL , CE#f2 = V IH . For Am29DL320G

flash access, CE#f1 = V IH , CE#f2 = V iL .

8.CE#1s= V IL , CE2s= V IH , CE#f1=V IH and CE#f2=V IH when accessing pseudo SRAM.

Operation (Notes 1, 2)CE#f1

CE#f2(Note 7)

CE1#s (Note 8)CE2s

(Note 8)

OE#WE#

Addr.

LB#s UB#s RESET#WP#/

ACC

(Note 4)DQ7–DQ0DQ15–DQ8Read from Flash

H X L

A IN X

L/H

D OUT D OUT X L Write to Flash L H X H L A IN X X H (Note 4)

D IN D IN X L Standby V CC ± 0.3 V H X X X X X X V CC ± 0.3 V H

High-Z

X L Output Disable L

L H H H X L X H

L/H High-Z High-Z

H H X X L Flash Hardware Reset

X H X X

X X

L L/H High-Z High-Z

X L Sector Protect (Note 5)

X H

L SADD, A6 = L, A1 = H, A0 = L X X

V ID

L/H

D IN

X L Sector Unprotect (Note 5)

X H

L SADD, A6 = H, A1 = H, A0 = L X X

V ID

(Note 6)

D IN

X L T emporary Sector Unprotect

X H X X X X

X X V ID

(Note 6)

D IN High-Z X

Read from Pseudo SRAM

H L H L H

A IN

L H X D OUT

D OUT H L High-Z D OUT L H D OUT High-Z Write to Pseudo SRAM

H L H X L

A IN

L H X D IN

D IN H L High-Z D IN L

D IN

High-Z

FLASH DEVICE BUS OPERATIONS

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE#f and OE# pins to V IL. CE#f is the power control and selects the device. OE# is the output con-trol and gates array data to the output pins. WE# should remain at V IH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com-mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered.

Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram.

I CC1 in the DC Characteristics table represents the ac-tive current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in-cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to V IL, and OE# to V IH.

The device features an Unlock Bypass mode to facili-tate faster programming. Once a bank enters the Un-lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Byte/Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se-quences.

An erase operation can erase one sector, multiple sec-tors, or the entire device. Table 2 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Flash Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank.

I CC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The Flash AC Characteristics section contains timing specifica-tion tables and timing diagrams for write operations. Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima-rily intended to allow faster manufacturing throughput at the factory.

If the system asserts V HH on this pin, the device auto-matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor-mal operation. Note that V HH must not be asserted on WP#/ACC for operations other than accelerated pro-gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon-nected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page23 for related infor-mation.

Autoselect Functions

If the system writes the autoselect command se-quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter-nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Se-quence sections for more information. Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus-pended to read from or program to another location within the same bank (except the sector being erased). Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6f and I CC7f in the table represent the cur-rent specifications for read-while-program and read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the de-vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE#f and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de-

12Am75DL9608HG November 17, 2003

vice requires standard access time (t CE) for read ac-cess when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or program-ming, the device draws active current until the operation is completed.

I CC3f in the table represents the standby current speci-fication.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard ad-dress access timings provide new data when ad-dresses are changed. While in sleep mode, output data is latched and always available to the system.

I CC5f in the table represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-setting the device to reading array data. When the RE-SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device is ready to accept another command sequence, to en-sure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (I CC4f). If RESET# is held at V IL but not within V SS±0.3 V, the standby cur-rent will be greater.

The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory.

If RESET# is asserted during a program or erase op-eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys-tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo-rithms). The system can read data t RH after the RE-SET# pin returns to V IH.

Refer to the Flash AC Characteristics tables for RE-SET# parameters and to Figure 15 for the timing dia-gram.

Output Disable Mode

When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state.

November 17, 2003Am75DL9608HG13

Table 2.Am29DL640H Sector Architecture

Bank Sector Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

Bank 1

SA000000000008/400000h–00FFFh SA100000000018/401000h–01FFFh SA200000000108/402000h–02FFFh SA300000000118/403000h–03FFFh SA400000001008/404000h–04FFFh SA500000001018/405000h–05FFFh SA600000001108/406000h–06FFFh SA700000001118/407000h–07FFFh SA80000001xxx64/3208000h–0FFFFh SA90000010xxx64/3210000h–17FFFh SA100000011xxx64/3218000h–1FFFFh SA110000100xxx64/3220000h–27FFFh SA120000101xxx64/3228000h–2FFFFh SA130000110xxx64/3230000h–37FFFh SA140000111xxx64/3238000h–3FFFFh SA150001000xxx64/3240000h–47FFFh SA160001001xxx64/3248000h–4FFFFh SA170001010xxx64/3250000h–57FFFh SA180001011xxx64/3258000h–5FFFFh SA190001100xxx64/3260000h–67FFFh SA200001101xxx64/3268000h–6FFFFh SA210001101xxx64/3270000h–77FFFh SA220001111xxx64/3278000h–7FFFFh

14Am75DL9608HG November 17, 2003

Bank 2SA230010000xxx64/3280000h–87FFFh SA240010001xxx64/3288000h–8FFFFh SA250010010xxx64/3290000h–97FFFh SA260010011xxx64/3298000h–9FFFFh SA270010100xxx64/32A0000h–A7FFFh SA280010101xxx64/32A8000h–AFFFFh SA290010110xxx64/32B0000h–B7FFFh SA300010111xxx64/32B8000h–BFFFFh SA310011000xxx64/32C0000h–C7FFFh SA320011001xxx64/32C8000h–CFFFFh SA330011010xxx64/32D0000h–D7FFFh SA340011011xxx64/32D8000h–DFFFFh SA350011000xxx64/32E0000h–E7FFFh SA360011101xxx64/32E8000h–EFFFFh SA370011110xxx64/32F0000h–F7FFFh SA380011111xxx64/32F8000h–FFFFFh SA390100000xxx64/32F9000h–107FFFh SA400100001xxx64/32108000h–10FFFFh SA410100010xxx64/32110000h–117FFFh SA420101011xxx64/32118000h–11FFFFh SA430100100xxx64/32120000h–127FFFh SA440100101xxx64/32128000h–12FFFFh SA450100110xxx64/32130000h–137FFFh SA460100111xxx64/32138000h–13FFFFh SA470101000xxx64/32140000h–147FFFh SA480101001xxx64/32148000h–14FFFFh SA490101010xxx64/32150000h–157FFFh SA500101011xxx64/32158000h–15FFFFh SA510101100xxx64/32160000h–167FFFh SA520101101xxx64/32168000h–16FFFFh SA530101110xxx64/32170000h–177FFFh SA540101111xxx64/32178000h–17FFFFh SA550110000xxx64/32180000h–187FFFh SA560110001xxx64/32188000h–18FFFFh SA570110010xxx64/32190000h–197FFFh SA580110011xxx64/32198000h–19FFFFh SA590100100xxx64/321A0000h–1A7FFFh SA600110101xxx64/321A8000h–1AFFFFh SA610110110xxx64/321B0000h–1B7FFFh SA620110111xxx64/321B8000h–1BFFFFh SA630111000xxx64/321C0000h–1C7FFFh SA640111001xxx64/321C8000h–1CFFFFh SA650111010xxx64/321D0000h–1D7FFFh SA660111011xxx64/321D8000h–1DFFFFh SA670111100xxx64/321E0000h–1E7FFFh SA680111101xxx64/321E8000h–1EFFFFh SA690111110xxx64/321F0000h–1F7FFFh SA700111111xxx64/321F8000h–1FFFFFh Table 2.Am29DL640H Sector Architecture (Continued)

Bank Sector Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

November 17, 2003Am75DL9608HG15

Bank 3

SA711000000xxx64/32200000h–207FFFh SA721000001xxx64/32208000h–20FFFFh SA731000010xxx64/32210000h–217FFFh SA741000011xxx64/32218000h–21FFFFh SA751000100xxx64/32220000h–227FFFh SA761000101xxx64/32228000h–22FFFFh SA771000110xxx64/32230000h–237FFFh SA781000111xxx64/32238000h–23FFFFh SA791001000xxx64/32240000h–247FFFh SA801001001xxx64/32248000h–24FFFFh SA811001010xxx64/32250000h–257FFFh SA821001011xxx64/32258000h–25FFFFh SA831001100xxx64/32260000h–267FFFh SA841001101xxx64/32268000h–26FFFFh SA851001110xxx64/32270000h–277FFFh SA861001111xxx64/32278000h–27FFFFh SA871010000xxx64/32280000h–28FFFFh SA881010001xxx64/32288000h–28FFFFh SA891010010xxx64/32290000h–297FFFh SA901010011xxx64/32298000h–29FFFFh SA911010100xxx64/322A0000h–2A7FFFh SA921010101xxx64/322A8000h–2AFFFFh SA931010110xxx64/322B0000h–2B7FFFh SA941010111xxx64/322B8000h–2BFFFFh SA951011000xxx64/322C0000h–2C7FFFh SA961011001xxx64/322C8000h–2CFFFFh SA971011010xxx64/322D0000h–2D7FFFh SA981011011xxx64/322D8000h–2DFFFFh SA991011100xxx64/322E0000h–2E7FFFh SA1001011101xxx64/322E8000h–2EFFFFh SA1011011110xxx64/322F0000h–2FFFFFh SA1021011111xxx64/322F8000h–2FFFFFh SA1031100000xxx64/32300000h–307FFFh SA1041100001xxx64/32308000h–30FFFFh SA1051100010xxx64/32310000h–317FFFh SA1061100011xxx64/32318000h–31FFFFh SA1071100100xxx64/32320000h–327FFFh SA1081100101xxx64/32328000h–32FFFFh SA1091100110xxx64/32330000h–337FFFh SA1101100111xxx64/32338000h–33FFFFh SA1111101000xxx64/32340000h–347FFFh SA1121101001xxx64/32348000h–34FFFFh SA1131101010xxx64/32350000h–357FFFh SA1141101011xxx64/32358000h–35FFFFh SA1151101100xxx64/32360000h–367FFFh SA1161101101xxx64/32368000h–36FFFFh SA1171101110xxx64/32370000h–377FFFh SA1181101111xxx64/32378000h–37FFFFh Table 2.Am29DL640H Sector Architecture (Continued)

Bank Sector Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

16Am75DL9608HG November 17, 2003

November 17, 2003Am75DL9608HG 17

Note:The address range is A21:A0

Table 3.

Am29DL640H Bank Address

Table 4.

Am29DL640H SecSi ? Sector Addresses

Bank 4

SA1191110000xxx 64/32380000h–387FFFh SA1201110001xxx 64/32388000h–38FFFFh SA1211110010xxx 64/32390000h–397FFFh SA1221110011xxx 64/32398000h–39FFFFh SA1231110100xxx 64/323A0000h–3A7FFFh SA1241110101xxx 64/323A8000h–3AFFFFh SA1251110110xxx 64/323B0000h–3B7FFFh SA1261110111xxx 64/323B8000h–3BFFFFh SA1271111000xxx 64/323C0000h–3C7FFFh SA1281111001xxx 64/323C8000h–3CFFFFh SA129

1111010xxx 64/323D0000h–3D7FFFh SA1301111011xxx 64/323D8000h–3DFFFFh SA1311111100xxx 64/323E0000h–3E7FFFh SA1321111101xxx 64/323E8000h–3EFFFFh SA1331111110xxx 64/323F0000h–3F7FFFh SA13411111110008/43F8000h–3F8FFFh SA13511111110018/43F9000h–3F9FFFh SA13611111110108/43FA000h–3FAFFFh SA13711111110118/43FB000h–3FBFFFh SA13811111111008/43FC000h–3FCFFFh SA13911111111018/43FD000h–3FDFFFh SA14011111111108/43FE000h–3FEFFFh SA141

1111111111

8/4

3FF000h–3FFFFFh

Bank A21–A191000

2001, 010, 0113100, 101, 110

111

Device Sector Size (x16)

Address Range Am29DL640H

256 bytes

00000h–0007Fh

Table 2.

Am29DL640H Sector Architecture (Continued)

Bank

Sector Sector Address

A21–A12Sector Size (Kbytes/Kwords)

(x16)

Address Range

18Am75DL9608HG November 17, 2003

Table 5.

Am29DL320G Top Boot Sector Addresses

Sector Sector Address

A20–A12Sector Size (Kbytes/Kwords)

(x16)

Address Range B a n k 4

SA0000000xxx 64/32000000h–07FFFh SA1000001xxx 64/32008000h–0FFFFh SA2

000010xxx 64/32010000h–17FFFh SA3000011xxx 64/32018000h–01FFFFh SA4000100xxx 64/32020000h–027FFFh SA5000101xxx 64/32028000h–02FFFFh SA6000110xxx 64/32030000h–037FFFh SA7000111xxx 64/32038000h–03FFFFh B a n k 3

SA8001000xxx 64/32040000h–047FFFh SA9001001xxx 64/32048000h–04FFFFh SA10001010xxx 64/32050000h–057FFFh SA11001011xxx 64/32058000h–05FFFFh SA12001100xxx 64/32060000h–067FFFh SA13001101xxx 64/32068000h–06FFFFh SA14001110xxx 64/32070000h–077FFFh SA15001111xxx 64/32078000h–07FFFFh SA16010000xxx 64/32080000h–087FFFh SA17010001xxx 64/32088000h–08FFFFh SA18

010010xxx 64/32090000h–097FFFh SA19010011xxx 64/32098000h–09FFFFh SA20010100xxx 64/320A0000h–0A7FFFh SA21010101xxx 64/320A8000h–0AFFFFh SA22010110xxx 64/320B0000h–0B7FFFh SA23010111xxx 64/320B8000h–0BFFFFh SA24011000xxx 64/320C0000h–0C7FFFh SA25011001xxx 64/320C8000h–0CFFFFh SA26011010xxx 64/320D0000h–0D7FFFh SA27011011xxx 64/320D8000h–0DFFFFh SA28011100xxx 64/320E0000h–0E7FFFh SA29011101xxx 64/320E8000h–0EFFFFh SA30011110xxx 64/320F0000h–0F7FFFh SA31011111xxx 64/320F8000h–0FFFFFh B a n k 2

SA32100000xxx 64/32100000h–107FFFh SA33100001xxx 64/32108000h–10FFFFh SA34100010xxx 64/32110000h–117FFFh SA35100011xxx 64/32118000h–11FFFFh SA36100100xxx 64/32120000h–127FFFh SA37100101xxx 64/32128000h–12FFFFh SA38

100110xxx 64/32130000h–137FFFh SA39100111xxx 64/32138000h–13FFFFh SA40101000xxx 64/32140000h–147FFFh SA41101001xxx 64/32148000h–14FFFFh SA42101010xxx 64/32150000h–157FFFh SA43101011xxx 64/32158000h–15FFFFh SA44101100xxx 64/32160000h–167FFFh SA45101101xxx 64/32168000h–16FFFFh SA46101110xxx 64/32170000h–177FFFh SA47

101111xxx

64/32

178000h–17FFFFh