TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. C)
TMS320C55x DSP CPU Programmer’s Reference
Supplement
SPRU652C
November 2002
Revised November 2003
Copyright 2003, Texas Instruments Incorporated
REVISION HISTORY
This revision history highlights the technical changes made to SPRU652B to generate SPRU652C. Scope: Updated Section 4, Documentation Support, etc.
Contents
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1.1Quality and Reliability Conditions8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMX Definition8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMP Definition8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS Definition8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Important Notices About CPU Advisories9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1Prototype Silicon Advisory Information9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2Useful Information Regarding Assembler Diagnostic Messages9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1ERROR Diagnostics9
2.2.2WARNING Diagnostics9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3REMARK Diagnostics9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3C55x CPU Known Design Advisories to Functional Specifications11
. . . . . . . . . . . . . . . . . . . . .
CPU_72C54CM Bit Update and *CDP With T0 Index is not Pipeline-Protected11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_73Certain Instructions not Pipeline-Protected From Resets12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_76DELAY Smem Does not Work With Circular Addressing13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_79IDLE Cannot Copy the Content of ICR to ISTR13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_80Nested Local Repeat Corrupted After C54CM Bit Reset14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_81WHILE Instruction in Slot #2 is not Protected14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_82‘if (cond true) goto’ at the End of Local Repeat Fails15
. . . . . . . . . . . . . . . . . . . . . .
CPU_83BRAF Updated Incorrectly in Certain Cases of Conditional Execution15
. . . . . .
CPU_84SP/SSP Access Followed by a Conditional Execute is not Protected Against Interrupts16
. . . . . . . . . . . . . . . . . . . . .
CPU_85Local Repeat With C54CM = 1 may be Corrupted on its Last Iteration17
. . . . . . . . . . .
CPU_86Corruption of CSR or BCRx Register Read When Executed in Parallel With Write17
. . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_87Context Restore Just Before Return Instruction Sometimes Fails18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_88Incorrect Context Store of BRAF During Interrupt Servicing19
. . . . . . . . . . . . . . . . . . . . . .
CPU_89Internal Overflow not Detected When Using the Left Shift Command20
. . . . . . . . . . . . . . . . . . . . . . . . .
CPU_90CPU Bypass Can Cause Corruption of a Read Following a Write21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_91C16, XF, and HM Bits not Reinitialized by Software Reset22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_92Consecutive C-Bus Accesses may not Work22 CPU_93Interrupted Conditional Execution After Memory Write may Execute Unconditionally
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
in the D Unit24 CPU_94Interrupted Conditional Execution After Long Memory-Mapped Register Write
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
is Executed Unconditionally in the D Unit / AD Unit25 CPU_95BRCx Decrement may not Work When gotoP24 is put at End of Blockrepeat
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
With C54CM = 027
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_96gotoP24 Within Blockrepeat Exits the Loop28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_97RETA = Lmem || Lmem = RETA may not Work29
. . . . . . . . . . . . . . . . .
CPU_98BANZ at the End of Inner Loop in Native Mode may Corrupt Program Flow30
CPU_99Return_int (Under a Fast Return Configuration) may Cause Improper Operation of
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Repeats and Conditional Executions31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_100Interrupted Single Repeat is not Resumed After RETI32 CPU_102Page Register Update and CPU Bypass Corrupts Following Memory Read33
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
CPU_103C54x Instruction, FRET[D] is not Protected Against Prior C54CM Bit Update35
. . . . . . . . .
CPU_104Blockrepeat Corrupted if Preceded by Localrepeat With C54CM = 1 and BRC0 = 035 CPU_106Move (Shift and Store) Instructions Incompatible With C54x When C54CM Bit = 1
and SST Bit = 136
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU_107Conditional Call With False Condition Corrupts RETA38 CPU_108Long (32-Bit) Read From MMR Gets Corrupted39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .
CPU_109Bus Error Issued on Byte Access to I/O Space With Address Range 0x0 to 0x5f40 CPU_110Relative Branch in ISR Corrupts Program Flow When Localrepeat With C54CM = 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
is Interrupted41
. . . . . . . . . . . . . .
CPU_111C54CM Bit Modification Followed by a mar Instruction Not Pipeline-Protected42 CPU_112Data Page Register and Stack Pointer Update Not Pipeline-Protected Against
Data Move Instructions43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4Documentation Support45
1Introduction
This document describes functional exceptions to the CPU behavior described in the
TMS320C55x DSP CPU Reference Guide (literature number SPRU371). Non-CPU issues are
described in the device-specific silicon errata. [For advisories on the OMAP5910 dual-core
processor, see the OMAP5910 Dual-Core Processor Silicon Errata (literature number
SPRZ016).] See section 4 for a listing of related documentation.
A quick reference table (Table 1) is included so that advisory descriptions may be quickly
located from the short description of each advisory. The advisory number in the first column of
the table is referenced in the title of each advisory description that follows in Section 3. The
columns on the right of the table indicate whether the advisory is present on the indicated
silicon revision. The CPU advisories can be grouped into three primary categories:
?Parallel Execution Issues
These issues are related to specific combinations of instructions executed in parallel. In
most cases, these issues can be avoided by not executing the instructions in parallel.
?Pipeline-protection Issues
These issues are cases where the pipeline is not properly automatically protected for
specific instruction sequences. In most cases, these problems can be corrected by
rearranging the instruction sequences, or by adding NOP instructions.
?Other Issues
These are the issues that do not fall into one of the above two categories.
The legend following indicates which symbols are used for each case.
||The advisory is present on this silicon revision and is related to parallel instruction execution.
P The advisory is present on this silicon revision and is related to pipeline protection.
X The advisory is present on this silicon revision and not related to either of the above categories.
fixed The advisory is not present on this silicon revision.
N/A The advisory is not applicable to this device.
All trademarks are the property of their respective owners.
Table 1.Quick Reference Table
Table 1.Quick Reference Table (Continued)
1.1Quality and Reliability Conditions
TMX Definition
Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or
(2) product reliability for products classified as TMX. By definition, the product has not
completed data sheet verification or reliability performance qualification according to TI Quality
Systems Specifications.
The mere fact that a TMX device was tested over a particular temperature and voltage ranges
should not, in any way, be construed as a warranty of performance.
TMP Definition
TI does not warranty product reliability for products classified as TMP. By definition, the
product has not completed reliability performance qualification according to TI Quality Systems
Specifications; however, products are tested to a published electrical and mechanical
specification.
TMS Definition
Fully-qualified production device
2Important Notices About CPU Advisories
2.1Prototype Silicon Advisory Information
The list of advisories included in this document may include all prototype versions of a device. As prototype silicon revisions become obsolete, they will be removed from this document. Please consult your local sales
representative if you need information concerning previous silicon revisions not listed in this document.
2.2Useful Information Regarding Assembler Diagnostic Messages
The TMS320C55x Assembler will generate three types of diagnostic messages when it detects a potential or
probable Silicon Exception.
2.2.1ERROR Diagnostics
The assembler generates ERROR diagnostics in cases where it can fully determine that the code will cause a
silicon exception to occur on hardware.
2.2.2WARNING Diagnostics
The assembler generates WARNING diagnostics in cases where it can fully determine that the code will cause a silicon exception to occur on hardware, but which, under certain circumstances, may not be an issue for the user.
2.2.3REMARK Diagnostics
The assembler generates REMARK diagnostics in conditions where it can fully determine that the code may cause
a silicon exception to occur on hardware, but the exception itself also depends on non-visible trigger conditions that
the assembler has no knowledge of, such as whether interrupts are enabled.
Since the assembler cannot determine the state of these trigger conditions, it cannot know that the exception will affect this code. Therefore, it generates a REMARK to instruct the user to examine the code and evaluate whether this is a potential silicon exception situation. (Please see the following sections for how to suppress remarks in
situations where you have determined that the other trigger conditions do not exist.)
Intended Treatment of REMARK Diagnostics
The intent of generating REMARK diagnostics is to inform the user that the code could potentially cause a silicon exception and that it should be reviewed by the user side by side with the trigger conditions and a determination be made whether the code is a potential silicon exception situation.
If the code is determined to be a potential silicon exception situation, users should modify their code to prevent that exception from occurring.
If users determine that their code will not cause a silicon exception based on the trigger conditions, then the
REMARK that the assembler generates can be suppressed. There are two methods of doing so; please see the “Suppressing REMARK Diagnostics” section.
Suppressing REMARK Diagnostics
Once the user determines that a silicon exception REMARK diagnostic is not appropriate for the code as written, the REMARK diagnostic can be suppressed in one of the following ways.
REMARK Directives:
The .noremark/.remark directives can be used to suppress the generation of a REMARK diagnostic for particular regions of code. The .noremark directive turns off the generation of a particular REMARK diagnostic. The .remark directive re-enables the generation of a particular REMARK diagnostic.
A ’.noremark ##’ (where ## is the remark id) directive is placed at the beginning of the region, and a ’.remark ##’directive is placed at the end of the region.
NOTE: The .noremark/.remark directive combination should always be placed around
the entire region of code that participates in the potential silicon exception. Otherwise,
spurious diagnostics may still be generated.
Additionally, the user has the option of disabling a silicon exception diagnostic for the entire file by placing just the .noremark directive at the top of the assembly file. However, this may be dangerous if, during inevitable code maintenance, the code is modified by someone not familiar with all the exception conditions. Please take great care when using the directives in this manner.
REMARK Command-Line Options:
The compiler shell (cl55) supports a command line option to suppress a particular REMARK diagnostic. The shell option ?ar# (where # is the assembler’s silicon exception id as described above) will suppress the named REMARK for the entire scope of all assembly files compiled with that command. Using the option ?ar without a number will suppress all REMARK diagnostics.
Again, this may be dangerous if, during inevitable code maintenance, the code is modified by someone not familiar with all the silicon exception conditions. Please take great care when using the command-line REMARK options. Using the .noremark/.remark directives covering the shortest possible range of source lines is much safer. PENDING Assembler Notification Status:
In the advisory descriptions, an assembler notification status marked “Pending” indicates the current version of the code generation tools do not yet detect the condition. As versions of the tools are released, known issues are included.
3C55x CPU Known Design Advisories to Functional Specifications
Revision(s) Affected:See Table 1
Details:When the C54CM bit in status register 1 (ST1_55) is set to 1, the T0 index for
single/dual/coefficient memory accesses should be replaced with AR0 for 54x compatibility.
Therefore, if a C54CM bit update is followed by an instruction utilizing the Data Address
Generator and T0 index, a stall should be generated to postpone the Data Address Generator
until the C54CM bit update is complete. In the following cases, the stall is not created and the
incorrect index is used (AR0/T0):
Case 1
C54CM bit update by bit instruction
0?4 cycles
B-bus access with ‘coef(*CDP+T0)’ using address modifier: *ABS16(#k) or *(#k).
Case 2
C54CM bit update by MMR write
0?5 cycles
B-bus access with ‘coef(*CDP+T0)’ using address modifier: *ABS16(#k) or *(#k).
Algebraic example
bit(ST1,#5) = #1; set C54CM (=1)
AC0 = *(#60h)*coef(*(CDP+T0)); T0 incorrectly used as index
Mnemonic example
BSET #5, ST1_55; set C54CM (=1)
MOV (#60h)*coef(*(CDP+T0)), AC0; T0 incorrectly used as index
; 0xaaaa
Assembler Notification:Assembler (versions 2.00 and later) will generate a REMARK when this condition is found. Workaround(s): 1.In the case where the C54CM bit is updated by a bit instruction, maintain at least 5 cycles
(useful code or NOPs) between the C54CM bit update and the Data Address Generator
instruction.
2.In the case where the C54CM bit is updated by a MMR write of ST1_55, maintain at least
6 cycles (useful code or NOPs) between the C54CM bit update and the Data Address
Generator instruction.
Revision(s) Affected:See Table 1
Details:In the following cases, instructions may not execute properly due to insufficient pipeline
protection from reset conditions:
Case 1
The following instruction(s) is not executed properly when closely preceded by a hardware or
software reset:
DP = #K16;OR
Data Address Generator operation affected by any status bit;OR
if (cond) execute (AD Unit)
These instructions (which depend on ST0_55, ST1_55 and ST2_55) will not execute correctly
if they are located in the first four instructions following the reset (including the delay slot in the
reset vector).
Case 2
IFR0/1 or ST1 MMR read instructions may return invalid read data when followed by a
software reset.
Case 3
The BRAF bit is not cleared correctly by a software reset which follows the
bit (ST1, #BRAF) = #1 instruction.
Assembler Notification:None
Workaround:Use the appropriate workaround, based on the Case.
Case 1
Do not put the following instruction(s) in the delay slot (last four bytes after the interrupt
vector). Also do not use the following instruction(s) as the first, second, or third instructions at
beginning of program space:
DP = #K16;OR
DAGEN-operation affected by any status bit;OR
if (cond) execute (AD Unit)
Case 2
Ensure at least 3 cycles between IFR0/1 or ST1 MMR read and a software reset.
Case 3
Ensure at least 5 cycles between bit(ST1, #BRAF) = #1 and a software reset
Revision(s) Affected:See Table 1
Details:When using circular addressing mode with the ‘DELAY Smem’ instruction in the following
case:
smem = (end address of a circular buffer)
the incorrect destination address is used for the delay instruction. The destination address
used is (end of circular buffer)+1, which is outside of the circular buffer. The correct
functionality would be for the destination address to wrap around to the beginning address of
the circular buffer.
Assembler Notification:Assembler (version 2.3 and later) will detect the use of delay (Smem) and generate a
REMARK.
Workaround:Do not use circular addressing mode with the ‘DELAY’ instruction.
Revision(s) Affected:See Table 1
Details:When an IDLE instruction is decoded, the content of the Idle Configuration Register (ICR) is supposed to be copied to the Idle Status Register (ISTR) when the instruction preceding the
IDLE completes its write phase. However, during the following sequence, the ICR to ISTR
copy does not happen:
1.IDLE is decoded.
2. A wakeup interrupt condition (NMI or any maskable interrupt which is enabled in the
IER0/IER1 registers) is captured or is currently pending.
3.The ICR to ISTR would normally happen here, but does not occur.
Assembler Notification:None
Workaround:Make sure all interrupts are masked (disabled) via the IER0/IER1 registers before IDLE
instruction is decoded. This workaround does not work for the NMI interrupt.
Revision(s) Affected:See Table 1
Details:When the following conditions occur:
? A local repeat follows another local repeat (nested local repeats).
?The first local repeat is stalled in the address phase due to a C54CM bit update from
1 to 0,
The CPU jumps to the wrong instruction address when leaving the outer repeat loop.
Algebraic example
bit(ST1,#5) = #0
nop
nop;insert additional NOP here to implement workaround
localrepeat {;instruction stalled in address phase
localrepeat {
:
}
:
};instruction pointer is incorrect upon leaving outer
loop
Assembler Notification:Assembler (version 2.30 and greater) will generate a WARNING when these conditions occur. Workaround(s): 1.In the case of a C54CM bit update by a bit instruction to register ST1. Ensure that the
C54CM bit update occurs a least four (4) cycles before the first local repeat.
2.In the case of a C54CM bit update by an MMR instruction. Ensure that the C54CM bit
update occurs a least five (5) cycles before the first local repeat.
Revision(s) Affected:See Table 1
Details:When WHILE instruction is located as second slot and single repeated instruction follows after one null slot that is caused by any pipeline discontinuity, the WHILE instruction is not pipeline
protected. If the single repeat instruction follows WHILE instruction immediately or there are
more than one null slot, it works.
Assembler Notification:Assembler (version 1.83 and greater) will generate an ERROR when a WHILE operation is
found in the second position of a parallel pair.
Workaround:Do not use the WHILE instruction in the second slot of a parallel instruction pair.
Revision(s) Affected:See Table 1
Details:Within any local repeat block if a conditional branch instruction is placed at the second to last position, and the branch target is at the last position of the loop, the program flow is corrupted.
This is the case regardless of whether the local repeat is the outer loop or a nested inner loop.
Algebraic example
localrepeat{
.
.
.
if (cond true) goto TARGET
TARGET
nop
}
.
Assembler Notification:None
Workaround:Do not use this instruction sequence.
Revision(s) Affected:See Table 1
Details:When C54CM=1 and one of the following cases occurs, the BRAF bit is modified regardless of the condition.
?if(cond=false)Execute(D_unit) k bit(ST1, @BRAF) = #0/1
?while(cond=false && (RPTC < k8)) bit(ST1, @BRAF) = #0/1
Assembler Notification:Assembler (version 2.3 and greater) will attempt to detect the cases above and generate a
WARNING.
Workaround(s): https://www.wendangku.net/doc/582992341.html,e the AD-unit instead of the D-unit in the conditional execution instruction
OR
Do not use parallelism (use conditional execute of next instruction as opposed to
conditional execute of parallel instruction).
2.Do not use a bit instruction that modifies BRAF within the WHILE instruction
Revision(s) Affected:See Table 1
Details:Any of the following instructions are not protected against interrupts when followed by a
AD-unit conditional execute instruction for which the condition is false.(This exception only
applies to conditional execution of the next instruction and not a conditional execute of a
parallel instruction):
?MMR-read access to SP/SSP
?dst = XSP/XSSP
?dbl(Lmem) = XSP/XSSP
?push_both(XSP/XSSP)
?XSP/XSSP = pop()
?MMR-write access to SP/SSP
Algebraic example
...{
nop
SP = SP - #1
.if (TC1) execute (SD_Unit) ;where TC1=0, condition is false.
AR6 ?= #1
...
Assembler Notification:Assembler (version 2.3 and greater) will attempt to identify a code sequence that may cause the exception, and will generate a REMARK.
Workaround(s): 1.When SP/SSP is read in the read phase, insert two (2) NOPs between the SP/SSP
instruction and the conditional execute instruction.
2.When SP/SSP is read or written in the execute phase, insert three (3) NOPs between the
SP/SSP instruction and the conditional execute instruction.
3.When SP/SSP is written in the write phase, insert four (4) NOPs between the SP/SSP
instruction and the conditional execute instruction.
Revision(s) Affected:See Table 1
Details:Under the following conditions during a local repeat loop:
?C54CM = 1
?The program fetch is occurring to restart the last iteration of the local repeat loop
?The program fetch is stalled
The local repeat may be overwritten even though the last iteration has not been completed. Assembler Notification:Assembler (version 2.3 and greater) will generate a WARNING when a .C54CM_ON directive is seen and a local repeat is encountered.
Workaround:Do not use local repeat loops with C54CM = 1.
Revision(s) Affected:See Table 1
Details:Under the following conditions:
?CSR, BRC0, or BRC1 register is read in the EXE phase in parallel with a write to the same
register
?The instruction is stalled due to a previous write access
The register read may be corrupted, returning the new value from the register write instruction.
The possible parallel instruction pairs which may cause this condition are as follows:
Smem= CSR k CSR = TAx;Smem should be updated by old register value, but
Smem = CSR k CSR = Smem;updated to TAx value instead
Smem = BRC0k BRC0 = TAx
Smem = BRC0k BRC0 = Smem
TAx= BRC0k BRC0 = TAx
TAx =BRC0k BRC0 = Smem
Smem = BRC1k BRC1 = TAx
Smem = BRC1k BRC1 = Smem
TAx= BRC1k BRC1 = TAx
TAx =BRC1k BRC1 = Smem
Assembler Notification:Assembler (version 2.3 and greater) will detect the above parallel pairs and generate a
WARNING.
Workaround:Do not execute these instructions in parallel.
Revision(s) Affected:See Table 1
Details: A context restore just before the return instruction sometimes fails. There are two cases in
which this condition may occur:
Case 1: When the C54CM bit in ST1_55 is updated via MMR write just before the return
instruction, a failure may occur. In the following sequence:
*(ST1_55) =
return
the new value of the C54CM bit is not used by the return instruction. This may eventually lead
to a BRAF recovery error. When C54CM=1, BRAF is not recovered by return. When
C54CM=0, BRAF is recovered.
This failure occurs under the following conditions:
?C54CM bit is modified by ST1_55 context restore, AND
?the return condition is either ‘return’ with slow-return configuration, OR, ‘if() return’ with
fast or slow return configuration.
Case 2: Altering the BRAF bit just before ‘return_int’ instruction. In the following sequence:
C54CM = #1
...
any BRAF update
return_int
In the fast-return configuration, BRAF is recovered immediately after return_int is decoded
(along with return address). Due to lack of pipeline protection, the BRAF contents recovered
by ‘return_int’ is overwritten by the instruction preceding ‘return_int’.
This failure occurs under the following conditions:
?C54CM = 1, AND
?the return condition is either ‘return’ with fast-return configuration.
Assembler Notification:Assembler (version 2.3 and greater) will generate a REMARK when it detects the above
instruction sequences.
Workaround:Use one of the following workarounds.
Case 1: Insert at least one NOP between the MMR access and the return instruction.
Case 2: Do not recover the BRAF context with an instruction that accesses BRAF. Instead, let
the return instruction recover the BRAF content.
Revision(s) Affected:See Table 1
Details:When an interrupt is serviced while a blockrepeat loop is active, the context pushed onto the stack incorrectly stores the BRAF bits as 0. Upon returning from the interrupt service routine,
the CPU acts as if no loop is active. The program execution will continue sequentially past the
end of the active loop. in other words, the blockrepeat loop is not re-activated upon return from
an interrupt.
This condition occurs when the second instruction of a parallel instruction pair is a call (only
call L16 is legal for such an instruction pair). The condition can occur when these parallel
instructions are placed before the loop as well as within the loop.
Algebraic example
...
...
blockrepeat{
...
...; upon return from interrupt, loop becomes inactive.
}
OR
...
blockrepeat{
...
...
...; upon return from interrupt, loop becomes inactive.
}
Assembler Notification:Assembler (version 2.3 and greater) will detect any instruction with a parallel call L16 and
generate a REMARK.
Workaround:Since interrupts are asynchronous, the only workaround is NOT to utilize the following parallel instruction pair.
Revision(s) Affected:See Table 1
Details:In native 55x mode (C54CM=0) when performing left shifts using 32-bit computational mode (M40=0) with the sign extension mode bit set to UNSIGNED (SXMD=0), any overflow in ACx
should result in a saturate 40-bit value of 0x 00 7FFF FFFF. However, if ACx[39..32] = 0xFF
and a left shift occurs with the shift value ≥0x8, then ACx gets zeroed.
Example
SXMD = #0
M40 = #0
AC2 = FF 0000 0000h
DR1 = 0x0008h
TARGET*AR4 = HI(saturate(AC2 << DR1))
; *AR4 = 0x0000
; Expected value should be *AR4 = 0x7FFF.
Assembler Notification:Assembler will emit a REMARK for any instruction containing a left shift of an accumulator
(ACx) by DRx or a constant ≥ 8.
Workaround:None
计算机中央处理器CPU的发展
计算机中央处理器CPU的发展 (兰州大学信息科学与工程学院10级电信基地班胡亚昆) 摘要：上个世纪中期至今，计算机的发展日新月异。CPU是计算机的核心。本文以美国Intel 公司推出的CPU为例，详细介绍了计算机CPU的发展。 关键词：CPU 数据总线时钟频率80X86 Pentium Core 1. 引言 自1946年第一台计算机问世以来，计算机的发展已经历了电子管、晶体管、中小规模集成电路、大规模集成电路和超大规模集成电路4个阶段。而中央处理器（Central Processing Unit，简称CPU）正是现代计算机系统的核心和引擎，计算机日新月异的发展在很大程度上归结为CPU技术的发展。通常，计算机的发展是以CPU的发展为表征的。根据摩尔定律，我们知道微处理器集成度每个18个月翻一番，芯片的性能也随之提高一倍左右。目前世界上生产CPU最强的公司是美国著名的Intel公司。本文将从Intel公司推出的第一台微处理器4004逐个介绍到Intel最近推出的Core系列处理器，通过这些介绍来让大家深刻地了解计算机中央处理器CPU的发展。 2. Intel 4004 1971年，Intel公司推出了世界上第一款微处理器4004，这是第一个可用于微型计算机的四位微处理器。它包含2300个晶体管，功能相当有限，而且速度还很慢，被当时的蓝色巨人IBM以及大部分商业用户不屑一顾，但是它毕竟是划时代的产品。从此以后，Intel便与微处理器结下了不解之缘。 3. 8086/8088/80186/80188 1978年，Intel公司正式推出了8086CPU，这是该公司生产的第一个16位芯片，内外数据总线均为16位，地址总线20位，主存寻址范围为1MB，时钟频率为5MHz，集成度只有0.040百万件/个。 由于当时的外设接口是8位，8086的16位外设数据线不能直接与外设接口连接，这一点限制了8086的推广。于是，1979年，Intel公司推出了准16位处理器8088，它只是将数据总线改为8位，其他设计都没有交大的改变，应用较为广泛。 8086/8088CPU内部结归纳起来可分为控制单元、逻辑单元和存储单元三大部分。这三大部分互相协调，对命令各数据进行分析、判断、运算并控制计算机协调工作。以后不管什么样的CPU，其内部结构都可归纳为这三部分。 8086/8088的指令是以字节为基础构成的，建立了指令预取队列，将取指令和执行指令这两个操作分别由总线接口单元（BIU）和执行单元（EU）来完成，提高了微处理器的指令执行速度。 8086/8088内有8个通用寄存器（AX，BX,CX,DX,SP,BP,SI,DI），4个段寄存器（SS,ES,DS,CS）和2个控制寄存器（IP,FLAGS）,这些寄存器全部是16位寄存器。 8086/8088无高速缓存。 随后，Intel公司80186/80188，它们的核心分别是8006/8088，配以定时器、中断控制器、DMA控制器等支持电路，功能更多，速度更快。80186/80188指令系统比8086/8088增加了若干实用的指令，涉及堆栈操作、位移指令、输入输出指令、过程指令、边界检测及乘法指令。
中央处理器的发展
中央处理器的发展 CPU的英文全称是Central Processing Unit，意思是中央处理单元，我们通常也称之为中央处理器。CPU是电脑中最重要的核心组件。通常，一块CPU都要包含运算/逻辑单元、控制单元和寄存器这三部分，这些单元都被集成在一块面积不大的硅晶片中。 要了解CPU，首先要了解一些CPU方面的术语，拿这颗Intel新推出的P4 （图1）来看，它的一些参数已经在金属外壳上刻有了，1M/800分别代表CPU的主频、二级缓存和前端总线频率。 主频就是这颗CPU的工作频率，一般来说主频越高CPU的速度越快，性能也就越强，主频、倍频和外频之间有一个换算关系：主频＝外频×倍频。这颗CPU的外频是200MHz，于是我们可以推算出它的倍频应该是14。缓存是很重要的一个指标，Int el通常按照二级缓存的多少来划分Pentium和Celeron，通常两者之间有一倍的差距。前端总线（FSB）在Intel P4系列CPU 中和外频之间也有个换算关系：前端总线频率（FSB）＝外频×4，所以通过这里给出的800MHz，我们可以推算出外频为200MH z。 目前，市面上的CPU主要是Intel和AMD两家公司的，下面我们从这两个公司的发展旅程来看看CPU的发展。 CPU双雄：Intel & AMD 一、早期的CPU 早期我们接触的电脑，大部分使用的是Intel的处理器，386、486其实说的就是CPU的型号。例如486是指CPU为Intel 80486（图2）处理器的电脑，Intel的处理器价格昂贵，并不是每个人都能够买得起的，当时一台普通的486电脑售价接近1 0000RMB。这个时候的AMD公司一直都在努力仿照Intel的CPU，推出一系列与之兼容的处理器，而且采取和Intel同样的命名方式，也取名叫386、486。 二、Pentium与K5出现 1993年3月，Intel发布了继80486之后的又一款CPU，并正式取名为Pentium（奔腾），俗称“586”。最初有Pentium
中央处理器cpu主要由什么组成
中央处理器cpu主要由什么组成 CPU作为电脑的核心组成部份，它的好坏直接影响到电脑的性能。下面是小编带来的关于中央处理器cpu主要由什么组成的内容，欢迎阅读! 中央处理器cpu主要由什么组成? 运算器和控制器是计算机的核心部件，这两部分合称中央处理单元(Centre Process Unit，简称CPU)，如果将CPU集成在一块芯片上作为一个独立的部件，该部件称为微处理器(Microprocessor，简称MP)。 运算器进行各种算术运算和逻辑运算;控制器是计算机的指挥系统; 1、运算器 运算器是计算机中进行算术运算和逻辑运算的部件，通常由算术逻辑运算部件(ALU)、累加器及通用寄存器组成。
2、控制器 控制器用以控制和协调计算机各部件自动、连续地执行各条指令，通常由指令部件、时序部件及操作控制部件组成。 CPU 的主要性能指标是主频和字长。 字长表示CPU每次计算数据的能力。如80486及Pentium 系列的CPU一次可以处理32位二进制数据。 时钟频率主要以MHz为单位来度量，通常时钟频率越高，其处理速度也越快。 相关阅读推荐： Intel和AMD双双意识到到目前为止测温问题解决的并不好，于是用到了一个新的方式。这个方式仍然包括热敏二极管，但是热敏二极管是一个模拟器件，所以读数必须被转换成数字数据。这个工作由ADC(模数转换器)来完成。
一个热敏二极管加上一个模数转换器就构成一个被称为DTS(数字温度传感器)的部件。理论上来说这个DTS的工作方式十分简单：一个CPU核心上的电路从热敏二极管上采样然后把数字数据输出到CPU一个特定的寄存器中，从而任何程序都可以随意读取该数据。这种方式的长处就是所有工作都在CPU内部即时完成，和易于被干扰和衰弱的模拟信号相比，数字信号传输的时候不会损失精确性。 这个系统另一个优点就是你可以在一块芯片上集成若干个传感器。Intel和AMD都在CPU的每一个核心上集成了一个DTS，这意味着你可以看到你每一个核心的温度。例如当你在双核CPU上运行程序并把该程序的相关性设定到某一个核心的时候，你会看到只有一个核心会升温并且会升得非常之快。当然另一个核心温度也会上升，毕竟两个核心共处在一个硅片上，只是不会上升到全力工作的核心那么高罢了。 看了中央处理器cpu主要由什么组成文章内容的人还看： 1.cpu由什么和什么组成 2.计算机cpu由什么组成
计算机专业基础综合计算机组成原理(中央处理器)历年真题试卷汇编1
计算机专业基础综合计算机组成原理（中央处理器）历年真题试 卷汇编1 (总分：66.00，做题时间：90分钟) 一、单项选择题(总题数：26，分数：52.00) 1.CPU的功能包括____。【华中科技大学2007年】 A.指令控制、操作控制、时间控制、数据加工√ B.命令控制、数据控制、时间控制、程序控制 C.数据控制、操作控制、时间控制、数据加工 D.指令控制、数据控制、时间控制、程序控制 考查CPU的功能。CPU的功能主要有指令控制、操作控制、时间控制、数据加工。 2.在CPU的设汁中，不需要____。【武汉大学2006年】 A.指令寄存器 B.地址译码器√ C.数据寄存器 D.地址寄存器 考查CPU中包含的寄存器。CPU的结构中没有地址译码器。 3.下列部件不属于控制器的是____。【沈阳航空工业学院2005年】 A.指令寄存器 B.程序计数器 C.程序状态字√ D.时序电路 考查控制器中包含的寄存器。控制器由程序计数器(PC)、指令寄存器(IR)、存储器地址寄存器(MAR)、存储器数据寄存器(MDR)、指令译码器、时序电路和微操作信号发生器组成。程序状态字(PSW)属于运算器的组成部分。 4.通用寄存器是____。【北京邮电大学2003年】 A.可存放指令的寄存器 B.可存放程序状态字的寄存器 C.本身具有计数逻辑与移位逻辑的寄存器 D.可编程指定多种功能的寄存器√ 考查通用寄存器。存放指令的寄存器是指令寄存器(IR)，存放程序状态字的寄存器是程序状态字寄存器(PSW)，通用寄存器并不一定本身具有计数和移位功能。 5.CPU中保存当前正在执行指令的寄存器是____。【华中科技大学2007年】 A.指令寄存器√ B.指令译码器 C.数据寄存器 D.地址寄存器 考查指令寄存器。指令寄存器用来存放当前正在执行的指令。 6.条件转移指令执行时所依据的条件来自____。【北京航空航天大学2002年】 A.指令寄存器 B.标志寄存器√ C.程序计数器 D.地址寄存器 考查程序状态标志寄存器(PSW)。指令寄存器IR用于存放当前正在执行的指令，程序计数器PC用于指示下一条指令的地址，地址寄存器用于暂存指令或数据的地址，程序状态寄存器PSW用于保存系统的运行状态，条件转移指令执行时，需对PSW的内容进行测试，判断是否满足转移条件。
中央处理器(教案)
第五章中央处理器（教案） a)学习目的与要求 学习目的：了解掌握计算机中央处理器的组成原理与控制方式 学习要求：了解CPU的总体结构，掌握指令的执行过程，时序产生器的工作与控制原理，微程序控制技术，各种控制器的结构和工作原理。 本章主要内容： ?CPU的总体结构 ?指令的执行与时序产生器 ?微程序设计技术和微程序控制器 ?硬布线控制器与门阵列控制器 ?CPU的新技术 b)应掌握的知识点 i. CPU的总体结构 CPU由控制器和运算器两个主要部件组成。控制器负责协调和指挥整个计算机系统的操作，控制计算机的各个部件执行程序的指令序列。由程序计数器、指令寄存器、指令译码器、时序产生器和操作控制器等组成；运算器接受控制器的命令并负责完成对操作数据的加工处理任务，由算术逻辑单元(ALU)、累加寄存器、数据缓冲寄存器和状态标志寄存器组成。 CPU主要完成以下几方面的功能：（１）控制指令执行顺序；（２）控制指令操作；（３）控制操作时间；（４）执行算术、逻辑运算。 CPU中完成取指令和执行指令全过程的部件是操作控制器，其主要功能是根据指令操作码和时序信号的要求，产生各种操作控制信号，以便正确地建立数据通路。 操作控制器有组合．逻辑控制器和微程序控制器两种，二者和差别是它们中的“控制信号形成部件”不同，反映了不同的设计原理和方法。根据设计方法不同可分为：①硬布线控制器；②微程序控制器；③门阵列控制器。 CPU中除了操作控制器外，还必须有时序产生器。时序产生器是对各种操作实施时间上的严格控制的部件。 CPU的组成如图5.1所示。
算术逻辑单元 CPU c c c ALU 取指 控制 执行 控制 时钟 状态反馈操作控制器 时序产生器 状态条件寄存器 累加器 c AC 指令 译码器 程序 计数器PC c c 指令寄存器 c IR c 地址寄存器AR 缓冲 寄存器 DR 存储器 输入/ 输出 数据总线 DBUS 地址总线 ABUS 图5.1 CPU主要组成部分逻辑结构图 ii. 指令的执行与时序产生器 1.指令周期 程序运行的过程是逐条执行指令的过程，而一条指令的执行又分为取指令、取操作数和执行指令等时间段，这些时间段在计算机中称为周期。 取出指令并执行该指令所需的时间称为指令周期。如图5.2所示。 1.取指令 1.取操作数 2.指令译码 2.完成操作 3.PC+! 3.结果回写 4.送操作数地址 4.AC送存储器 图5.2 指令周期、取指周期、执行周期和微操作 指令周期常常用若干个CPU周期数来表示。由于CPU内部的操作速度较快，而CPU 访问一次主存储器所花的时间比较长，故通常是用主存储器中读取一个指令字的最短时间来规定CPU周期。CPU周期也称为机器周期。这就是说，一条指令的取出阶段，简称取指，需要一个CPU周期时间。而一个CPU周期又包含有若干个时钟周期，时钟周期通常又称为节拍脉冲或T周期，是处理操作的最基本时间单位，它由机器的主频决定。一个CPU周期的时间宽度就由若干个时钟周期的总和决定。 几种典型指令的指令周期： （１）非访问内存的指令(如CLA)需要两个CPU周期。如图5.3所示。其中，取指令阶段需要一个CPU周期，执行指令阶段需要一个CPU周期。在第一个CPU周期，从内存
中央处理器
CHAPTER 8 Computer ARITHMETIC (第8章计算机算法) 第三部分中央处理器 本部分介绍指令和数据类型这样的体系结构问题，考察计算机流水线的组织结构问题。 第8章计算机算法 考察ALU的功能，聚焦于实现算术运算的技术和数的表示方法。处理器支持两类算术运算：定点数和浮点数，讨论IEEE 754浮点标准。 第9章指令集：特征和功能 讨论指令集设计的功能方面。①功能类型②操作数类型③操作类型 第10章指令集：寻址方式和指令格式 讨论指令集的词义学问题，讨论指令集的语法学问题，考察指定存储器地址的方式，指令的整体格式。 第11章 CPU结构和功能 介绍寄存器的使用，CPU结构和功能的综述，重申整体组织讨论寄存器集的的具体组织。描述处理器执行机器指令的功能，考察指令周期，探讨使用流水技术改善性能。 第12章精简指令集计算机 介绍RISC概念相关方法，使用RISC设计的动力，考察RISC指令集设计和RISC CPU 体系结构。 第13章超标量处理器 考察超标量技术
第8章 计算机算法 ● 计算机关注数字表示方式和基本算术运算的算法;适用于整数运算和浮点运算 ● 大多数处理器都实现了IEEE 754标准，用于浮点表示和浮点运算 本章重点放在ALU 的计算机算法。 8.1 The Arithmetic and Logic Unit(ALU) (算术和逻辑单元) 某种意义上当考察ALU 时，我们已到达计算机的核心或本质。 算逻单元及计算机所有电子部件都是基于简单数字逻辑装置的使用，这些装置保存二进制数字和完成简单的布尔逻辑运算。 CP200+EP275图8.1指出ALU 与CPU 互连，数据以寄存器提交给ALU ，运算结果也存于寄存器；ALU 亦将设置标志作为运算结果；标志值也存于CPU 内的寄存器中。 8.2 Integer Representation ( 整数表示) 二进制数值系统中，仅用数字0和1、负号和小数点表示任何一个数。对于计算机存储和处理，负号和小数点是不方便的。 通常，若一个n 位二进制数字序列a n-1 a n-2…a 1a 0表示一个无符号整数A=∑-=1 02n i i ai 。 8.2.1 Sign-Magnitude Representation (符号-幅值表示法) 采用一个符号位的最简单的表示法是符号—幅值表示法。以一个n 位字为例，最左位为符号位，其余n-1位为整数的幅值（绝对值） 若定点小数的原码形式为X 0.X 1X 2X 3┅X n-1X n ，则原码定义为： 若定点整数的原码形式为X 0X 1X 2X 3┅X n-1X n ，则原码定义为： 符号-幅值表示法缺点：①加减运算时既要考虑数的符号，又要考虑幅值；②0有两种表示。因此符号-幅值表示法很少用于ALU 中的整数表示，常用的方案是2的补码。 8.2.2 Two ’s Complement Representation ( 2的补码表示法) 2的补码表示法使用最高位作为符号位，表8.1说明2的补码表示法和算术的关键特征。 以2的补码形式来表示一个n 位整数A 。 数零被标识为正的，正整数可表示的范围是由0到2n-1 -1。 ∑2-n 0.i i i 1-n 1-n a 2a 2 -A =+= （8-2）