KK74HC174AD中文资料

TECHNICAL DATA

KK 74HC174A

Hex D Flip-Flop with

Common Clock and Reset

High-Performance Silicon-Gate CMOS

The KK 74HC174A is identical in pinout to the LS/ALS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low.

? Outputs Directly Interface to CMOS, NMOS, and TTL

? Operating Voltage Range: 2.0 to 6.0 V

? Low Input Current: 1.0 μA

? High Noise Immunity Characteristic of CMOS Devices

X = Don’t care L = LOW voltage level H = HIGH voltage level

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16=V CC PIN 8 = GND

MAXIMUM RATINGS*

Symbol Parameter Value

Unit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V

V IN DC Input Voltage (Referenced to GND) -1.5 to V CC +1.5 V

V OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 V

I IN DC Input Current, per Pin ±20 mA

I OUT DC Output Current, per Pin ±25 mA

I CC DC Supply Current, V CC and GND Pins ±50 mA

P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750

500

mW

Tstg Storage Temperature -65 to +150 °C

T L Lead Temperature, 1,5 mm from Case for 4 Seconds

(Plastic DIP or SOIC Package)

260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min

Max

Unit V CC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC V

T A Operating Temperature, All Package Types -55 +125 °C

t r, t f Input Rise and Fall Time (Figure 1) V CC =2.0 V

V CC =4.5 V

V CC =6.0 V 0

1000

500

400

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND≤(V IN or V OUT)≤V CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

V CC Guaranteed Limit

Symbol Parameter Test

Conditions V

-55°C

to

25°C ≤85

°C

≤125

°C

Unit

V IH Minimum High-

Level Input Voltage V OUT≥ V CC-0.1 V

or ≤0.1 V

?I OUT?≤ 20 μA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V IL Maximum Low -

Level Input Voltage V OUT≤0.1 V

or ≥V CC-0.1 V

?I OUT?≤ 20 μA

2.0

4.5

6.0

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

V

V OH Minimum High-

Level Output Voltage V IN=V IH or V IL

?I OUT?≤ 20 μA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

V IN=V IH or V IL

?I OUT?≤ 4.0 mA

?I OUT?≤ 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

V OL Maximum Low-

Level Output Voltage V IN= V IL or V IH

?I OUT?≤ 20 μA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

V IN= V IL or V IH

?I OUT?≤ 4.0 mA

?I OUT?≤ 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.4

0.4

I IN Maximum Input

Leakage Current

V IN=V CC or GND 6.0±0.1±1.0 ±1.0 μA

I CC Maximum Quiescent

Supply Current

(per Package) V IN=V CC or GND

I OUT=0μA

6.0 4.0 40 160 μA

AC ELECTRICAL CHARACTERISTICS (C L=50pF, Input t r=t f=6.0 ns, V IL= 0 V, V IH=Vcc)

V CC Guaranteed Limit

Symbol Parameter V

-55°C

to

25°C

≤85°C ≤125°C Unit

f max Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4) 2.0

4.5

6.0

6.0

30

35

4.8

24

28

4.0

20

24

MHz

t PLH, t PHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 2.0

4.5

6.0

110

22

19

140

28

24

165

33

28

ns

t PHL Maximum Propagation Delay , Reset to Q (Figures 2 and 4) 2.0

4.5

6.0

110

21

19

140

28

24

160

32

27

ns

t TLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

C IN Maximum Input Capacitance - 10 10 10 pF

Power Dissipation Capacitance (Per Enabled

Output)

Typical @25°C,V CC=5.0 V

C P

D Used to determine the no-load dynamic power

consumption: P D=C PD V CC2f+I CC V CC

62 pF TIMING REQUIREMENTS (C L=50pF,Input t r=t f=6.0 ns, V IL= 0 V, V IH=Vcc)

V CC Guaranteed Limit

Symbol Parameter V

-55 °C to

25°C

≤85°C ≤125°C Unit

t SU Minimum Setup Time, Data to Clock (Figure 3) 2.0

4.5

6.0

50

10

9

65

13

11

75

15

13

ns

t h Minimum Hold Time, Clock to Data (Figure 3) 2.0

4.5

6.0

5

5

5

5

5

5

5

5

5

ns

t rec Minimum Recovery Time, Reset Inactive to Clock

(Figure 2) 2.0

4.5

6.0

5

5

5

5

5

5

5

5

5

ns

t w Minimum Pulse Width, Clock (Figure 1) 2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

t w Minimum Pulse Width, Reset (Figure 2) 2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

t r, t f Maximum Input Rise and Fall Times (Figure 1) 2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

ns

RESET

Q

CC CC CLOCK

CLOCK

Q

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

DATA

CLOCK

DEVICE UNDER TEST

OUTPUT

C L

*

TEST POINT

Figure 3. Switching Waveforms

Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM