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AD5254BRU50-RL7中文资料

Quad 64-/256-Position I2C Nonvolatile

Memory Digital Potentiometers

AD5253/AD5254 Rev.0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: https://www.wendangku.net/doc/5511335294.html, Fax: 781.326.8703? 2004 Analog Devices, Inc. All rights reserved.

FEATURES

AD5253: Quad 64-position resolution

AD5254: Quad 256-position resolution

1 k?, 10 k?, 50 k?, 100 k?

Nonvolatile memory1 stores wiper settings with write protection

Power-on refreshed to EEMEM settings in 300 μs typ EEMEM rewrite time = 540 μs typ

Resistance tolerance stored in nonvolatile memory

12 extra bytes in EEMEM for user-defined information

I2C? compatible serial interface

Direct read/write accesses of RDAC2 and EEMEM registers Predefined linear increment/decrement commands Predefined ±6 dB step change commands

Synchronous or asynchronous quad channel update

Wiper setting readback

4 MHz bandwidth—1 k? version

Single supply 2.7 V to 5.5 V

Dual supply ±2.25 V to ±2.75 V

2 slave address decoding bits allow operation of 4 devices 100-year typical data retention, T A = 55°C

Operating temperature: –40°C to +85°C APPLICATIONS

Mechanical potentiometer replacement

Low resolution DAC replacement

RGB LED backlight control

White LED brightness adjustment

RF base station power amp bias control

Programmable gain and offset control

Programmable attenuators

Programmable voltage-to-current conversion Programmable power supply

Programmable filters

Sensor calibrations

GENERAL DESCRIPTION

The AD5253/AD5254 are quad channel, I2C, nonvolatile mem-ory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjust-ment functions as mechanical potentiometers, trimmers, and variable resistors.

The AD5253/AD5254’s versatile programmability allows multi-ple modes of operation, including read/write accesses in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined informa-tion, such as memory data for other components, look-up table, or system identification information.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

The AD5253/AD5254 allow the host I2C controllers to write any of the 64-/256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored, they are restored automatically to the RDAC registers at system power-on; the settings can also be restored dynamically.

The AD5253/AD5254 provide additional increment, decrement, +6 dB step change, and –6 dB step change in synchronous or asynchronous channel update modes. The increment and decrement functions allow stepwise linear adjustments, while ±6 dB step changes are equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope nonlinear adjustment applications such as white LED brightness and audio volume control.

The AD5253/AD5254 have a patented resistance tolerance storing function that allows the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications.

The AD5253/AD5254 are available in TSSOP-20 packages in

1 k?, 10 k?, 50 k?, and 100 k? options. All parts are guaranteed to operate over the –40°C to +85°C extended industrial temperature range.

1The terms nonvolatile memory and EEMEM are used interchangeably.

2The terms digital potentiometer and RDAC are used interchangeably.

AD5253/AD5254

Rev. 0 | Page 2 of 28

TABLE OF CONTENTS

Electrical Characteristics.................................................................3 1 k? Version..................................................................................3 10 k?, 50 k?, 100 k? Versions...................................................5 Interface Timing Characteristics (All Parts).............................7 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Functional Descriptions..........................9 Typical Performance Characteristics...........................................10 I 2C Interface.....................................................................................14 I 2C Interface General Description............................................14 I 2C Interface Detail Description...............................................15 I 2C Compatible 2-Wire Serial Bus............................................19 Theory of Operation......................................................................20 Linear Increment and Decrement Commands......................20 ±6 dB Adjustments (Doubling/Halving Wiper Setting)........20 Digital Input/Output Configuration........................................21 Multiple Devices On One Bus..................................................21 Terminal Voltage Operation Range.........................................22 Power-Up and Power-Down Sequences..................................22 Layout and Power Supply Biasing............................................22 Digital Potentiometer Operation.............................................23 Programmable Rheostat Operation.........................................23 Programmable Potentiometer Operation...............................24 Applications.....................................................................................25 RGB LED LCD Backlight Controller.......................................25 Outline Dimensions.......................................................................27 Ordering Guide.. (27)

REVISION HISTORY

Revision 0: Initial Version

AD5253/AD5254

ELECTRICAL CHARACTERISTICS

1 k? VERSION

V DD = +3 V ± 10% or +5 V ± 10%, V SS = 0 V or V DD/V SS = ±2.5 V ± 10%, V A = +V DD, V B = 0 V, –40°C < T A < +85°C, unless otherwise noted.

Rev. 0 | Page 3 of 28

AD5253/AD5254

Rev. 0 | Page 4 of 28

AD5253/AD5254

10 k?, 50 k?, 100 k? VERSIONS

V DD = +3 V± 10% or +5 V± 10%, V SS = 0 V or V DD/V SS = ±2.5 V ± 10%, V A = +V DD, V B = 0 V, –40°C < T A < +85°C, unless otherwise noted.

Rev. 0 | Page 5 of 28

AD5253/AD5254

Rev. 0 | Page 6 of 28

AD5253/AD5254

Rev. 0 | Page 7 of 28

INTERFACE TIMING CHARACTERISTICS (ALL PARTS)

Guaranteed by design, not subject to production test. See Figure 23 for location of measured values. All input control voltages are specified with t R = t F = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V . Switching characteristics are measured using both V DD = 3 V and 5 V . When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I 2C interface at these pins conducts current of about 0.8 mA at V DD = 5.5 V and 0.2 mA at V DD = 2.7 V . Table 3.

Parameter Symbol Conditions Min Typ 1 Max Unit SCL Clock Frequency f SCL 400 kHz t BUF Bus Free Time between STOP and START t 1 1.3 μs

t HD;STA Hold Time (Repeated START) t 2After this period, the first clock pulse is

generated

0.6 μs t LOW Low Period of SCL Clock t 3 1.3 μs t HIGH High Period of SCL Clock t 4 0.6 μs t SU;STA Setup Time for START Condition t 5 0.6 μs t HD;DAT Data Hold Time t 6 0 0.9 μs t SU;DAT Data Setup Time t 7 100 ns t F Fall Time of Both SDA and SCL Signals t 8 300 ns t R Rise Time of Both SDA and SCL Signals t 9 300 ns t SU;STO Setup Time for STOP Condition t 10 0.6 μs EEMEM Data Storing Time t EEMEM_STORE 26 ms

EEMEM Data Restoring Time at Power On 9

t EEMEM_RESTORE1V DD rise time dependent. Measure without decoupling capacitors at V DD and V SS .

300 μs

EEMEM Data Restoring Time upon Restore

Command or RESET Operation 9

t EEMEM_RESTORE2V DD = 5 V 300 μs EEMEM Data Rewritable Time 10 t EEMEM_REWRITE 540 μs FLASH/EE MEMORY RELIABILITY

Endurance 11

100 kCycles Data Retention 12 100 Years

1 Typical values represent average readings at 25°C and V DD = 5 V.

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 k? version at V DD = 2.7V, I W = V DD /R for both V DD = 3 V or V DD = 5 V. 3

INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V B = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 4

Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 5

Guaranteed by design and not subject to production test. 6

cmd 0 NOP should be activated after cmd 1 in order to minimize I DD_RESTORE current consumption. 7

P DISS is calculated from (I DD × V DD = 5 V). 8

All dynamic characteristics use V DD = 5 V. 9

During power-up, all outputs preset to midscale before restoring EEMEM contents. RDAC0 has the shortest whereas RDAC3 has the longest EEMEM restore time. 10

Delay time after power-on or RESET before new EEMEM data to be written. 11

Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles. 12

Retention lifetime equivalent at junction temperature (T J ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates with junction temperature.

AD5253/AD5254

Rev. 0 | Page 8 of 28

ABSOLUTE MAXIMUM RATINGS

Table 4. T A = 25°C, unless otherwise noted

Parameter Rating V DD to GND ?0.3 V, +7 V V SS to GND +0.3 V, ?7 V V DD to V SS 7 V V A , V B , V W to GND V SS , V DD Maximum Current I WB , I WA Pulsed ±20 mA

I WB Continuous (R WB ≤ 1 k?, A Open)1

±5 mA I WA Continuous (R WA ≤ 1 k?, B Open)1 ±5 mA

I AB Continuous (R AB = 1 k?/10 k?/50 k?/100 k?)1

±5 mA/±500 μA/±100 μA/±50 μA Digital Inputs and Output Voltage to GND 0 V, 7 V Operating Temperature Range ?40°C to +85°C

Maximum Junction Temperature (T J MAX ) 150°C Storage Temperature

?65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C TSSOP-20 Thermal Resistance 2 θJA 143°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. V DD = 5V. 2

Package power dissipation = (T JMAX ? T A )/θJA .

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

AD5253/AD5254

Rev. 0 | Page 9 of 28

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

AD5253/AD5254

TOP VIEW

(Not to Scale)W01B02A03AD045W11B12A13SDA 4V SS 5

V DD W3B3

A3AD1

987

6DGND SCL W2B2

109876

03842-0-002

Figure 2. AD5253/AD5254 Pin Configuration

AD5253/AD5254

Rev. 0 | Page 10 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

R -I N L (L S B )

CODE (Decimal)

03824-0-015

–1.0

–0.8

–0.6–0.4–0.200.20.40.60.81.00

128

160

192

224

256

Figure 3. R-INL vs. Code

R D N L (L S B )

CODE (Decimal)

824-0-016

–1.0

–0.8–0.6–0.4–0.200.20.40.60.81.00

128

160

192

224

256

Figure 4. R-DNL vs. Code

I N L (L S B )

CODE (Decimal)

03824-0-017

–1.0–0.8

–0.6–0.4–0.200.20.40.60.81.00326496128160192224256

Figure 5. INL vs. Code I N L (L S B )

CODE (Decimal)

03824-0-01

8–1.0

–0.8

–0.6–0.4–0.200.2

0.40.60.8

1.00

128

160

192

224

256

Figure 6. DNL vs. Code

S U P P L Y C U R R E N T (μA )

TEMPERATURE (°C)

03824-0-019

–10

–8

–6–4–20246810

–40

–20020406080100120

Figure 7. Supply Current vs. Temperature

DIGITAL INPUT VOLTAGE (V)

03824-0-020

0.0001

0.01

0.001

0.1

0123456

I D D (m A )

Figure 8. Supply Current vs. Digital Input Voltage. T A = 25°C

AD5253/AD5254

Rev. 0 | Page 11 of 28

R W B (?)

V BIAS (V)

03824-0-021

406080100120140160200240

1802201023456

Figure 9. Wiper Resistance vs. V BIAS

TEMPERATURE (°C)

03824-0-022

–6–4

–2

–40

–20020406080100120

?R W B (%)

Figure 10. Change of R AB vs. Temperature

CODE (Decimal)

03824-0-023

05060702010

304080900

128

160

192

224

256

R H E O S T A T M O

D E T E M P C O (p p m /°C )

Figure 11. Rheostat Mode Tempco (?R WB /R WB )/?T × 106 vs. Code

CODE (Decimal)

03824-0-024

P O T E N T I O M E T E R M O D E T E M P C O (p p m /°C )

Figure 12. Potentiometer Mode Tempco (?V WB /V WB )/?T × 106 vs. Code

–60

–48

–24–120–36–54–30–18

–6

–42G A I N

(d B )

10k

100

100k

10M

FREQUENCY (Hz)

03824-0-025

Figure 13. Gain vs. Frequency vs. Code, R AB = 1 k?, T A = 25°C

–60

–48–24–120

–36–54–30–18–6–42G A I N (d B )

1k 10k 10

100

100k 1M 10M

FREQUENCY (Hz)

03824-0-026

Figure 14. Gain vs. Frequency vs. Code, R AB = 10 k?, T A = 25°C

AD5253/AD5254

Rev. 0 | Page 12 of 28

–60

–48–24–120–36–54–30–18

–6–42G A I N (d B )

10k 10

100

100k 1M 10M FREQUENCY (Hz)

03824-0-027

Figure 15. Gain vs. Frequency vs. Code, R AB = 50 k?, T A = 25°C

–60

–48–24–120–36–54

–30–18

–6–42G A I N (d B )

10k 10

100

100k 1M 10M

FREQUENCY (Hz)

03824-0-028

Figure 16. Gain vs. Frequency vs. Code, R AB = 100 k?, T A = 25°C

?R A B (?)

CODE (Decimal)

03824-0-029

–100

–80

–60–40–20

0204060801000

128

160

192

224

256

Figure 17. ?R AB vs. Code, T A = 25°C

CLOCK FREQUENCY (Hz)

03824-0-030

0.6

0.4

0.20.81.0

1.2

100101k 10k 100k 1M 10M

I D D (m A )

Figure 18. Supply Current vs. Digital Input Clock Frequency

03824-0-031

DIGITAL FEEDTHROUGH

CLK VDD = 5V

V W

MID-SCALE TRANSITION

7FH ≥ 80H

Figure 19. Clock Feedthrough and Midscale Transition Glitch

03824-0-046

VWB0(0xFF STORED IN EEMEM)VWB3(0xFF STORED IN EEMEM)

VDD = VA0 = VA3 = 3.3V GND = VB0 = VB3

MIDSCALE PRESET

RESTORE RDAC0SETTING TO 0xFF

RESTORE RDAC3SETTING TO 0xFF

VDD (NO DE-COUPLING CAPS)MIDSCALE PRESET

Figure 20. t EEMEM_RESTORE of RDAC0 and RDAC3

AD5253/AD5254

Rev. 0 | Page 13 of 28

CODE (Decimal)

03824-0-033

0321

816243240485664

T H E O R E T I C A L I W B _M A X (m A )

Figure 21. I WB_MAX vs. Code (AD5253) CODE (Decimal)

03824-0-034

128

160

192

224

256

T H E O R E T I C A L I W B _M A X (m A

)

Figure 22. I WB_MAX vs. Code (AD5254)

AD5253/AD5254

Rev. 0 | Page 14 of 28

I 2C INTERFACE

SCL

SDA

Figure 23. I 2C Interface Timing Diagram

I 2C INTERFACE GENERAL DESCRIPTION

From Master to Slave

From Slave to Master

S = Start Condition. P = Stop Condition.

A = Acknowledge (SDA Low).

A = Not Acknowledge (SDA High).

R/W = Read Enable at High; Write Enable at Low.

0 WRITE

(N BYTES + ACKNOWLEDGE)

038

Figure 24. I 2C—Master Writing Data to Slave

1 READ

(N BYTES + ACKNOWLEDGE)

Figure 25. I 2C—Master Reading Data From Slave

DIRECTION OF TRANSFER MAY

CHANGE AT THIS POINT

Figure 26. I 2C—Combined Write/Read

AD5253/AD5254

Rev. 0 | Page 15 of 28

I 2C INTERFACE DETAIL DESCRIPTION

From Master to Slave

From Slave to Master

S = Start Condition. P = Stop Condition.

A = Acknowledge (SDA Low).

AD1, AD0 = I 2C Device Address Bits. Must match with the logic states at Pins AD1, AD0. R/W = Read Enable Bit, Logic High/Write Enable Bit, Logic Low.

CMD/REG = Command Enable Bit, Logic High/Register Access Bit, Logic Low. EE/RDAC = EEMEM Register, Logic High/RDAC Register, Logic Low. A4, A3, A2, A1, A0 = RDAC/EEMEM Register Addresses.

03842-0-007

(1 BYTE +ACKNOWLEDGE)

0 REG

Figure 27. Single Write Mode

03842-0-00

(N BYTE +ACKNOWLEDGE)

0 REG

Figure 28. Consecutive Write Mode

Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)

A4 A3 A2 A1 A0 RDAC Data Byte Description

0 0 0 0 0 RDAC0 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 0 0 1 RDAC1 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 0 1 0 RDAC2 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 0 1 1 RDAC3 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 1 0 0 Reserved : : : : :

0 1 1 1 1 Reserved

AD5253/AD5254

Rev. 0 | Page 16 of 28

RDAC/EEMEM Write

Setting the wiper position requires an RDAC write operation. The single write operation is shown in Figure 27, and the consecutive write operation is shown in Figure 28. In

consecutive write operation, if the RDAC is selected and the address starts at 0, the first data byte goes to RDAC0, the second data byte goes to RDAC1, the third data byte goes to RDAC2, and the fourth data byte goes to RDAC3. This operation can be continued up to eight addresses with four unused addresses; it then loops back to RDAC0. If the address starts at any of the eight valid addresses, N, the data first goes to RDAC_N, RDAC_N + 1, and so on; it loops back to RDAC0 after the eighth address. The RDAC address is shown in Table 6. While the RDAC wiper setting is controlled by a specific RDAC register, each RDAC register corresponds to a specific EEMEM memory location, which provides nonvolatile wiper storage functionality. The addresses are shown in Table 7. The single and consecutive write operations also apply to EEMEM write operations.

There are 12 nonvolatile memory locations, EEMEM4 to

EEMEM15, where users can store 12 bytes of information such as memory data for other components, look-up table, or system identification information.

In a write operation to the EEMEM registers, the device disables the I 2C interface during the internal write cycle. Acknowledge polling, which is discussed later in the data sheet, is required to determine the completion of the write cycle.

RDAC/EEMEM Read

The AD5253/AD5254 provide two different RDAC or EEMEM

read operations. For example, Figure 29 shows the method of reading the RDAC0 to RDAC3 contents without specifying the address, assuming address RDAC0 was already selected from the previous operation. If RDAC_N, other than address 0, is selected previously, readback starts with address N, followed by N + 1, and so on.

Figure 30 illustrates the random RDAC or EEMEM read opera-tion. This operation allows users to specify which RDAC or EEMEM register is read by first issuing a dummy write command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location.

Table 7. Addresses for Writing (Storing) RDAC Settings and User-Defined Data to EEMEM Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 1)

A4 A3 A2 A1 A0 Data Byte Description 0 0 0 0 0 Store RDAC0 Setting to EEMEM010 0 0 0 1 Store RDAC1 Setting to EEMEM11 0 0 0 1 0 Store RDAC2 Setting to EEMEM21 0 0 0 1 1 Store RDAC3 Setting to EEMEM31 0 0 1 0 0 Store User Data to EEMEM4 0 0 1 0 1 Store User Data to EEMEM5 0 0 1 1 0 Store User Data to EEMEM6 0 0 1 1 1 Store User Data to EEMEM7 0 1 0 0 0 Store User Data to EEMEM8 0 1 0 0 1 Store User Data to EEMEM9 0 1 0 1 0 Store User Data to EEMEM10 0 1 0 1 1 Store User Data to EEMEM11 0 1 1 0 0 Store User Data to EEMEM12 0 1 1 0 1 Store User Data to EEMEM13 0 1 1 1 0 Store User Data to EEMEM14 0 1 1 1 1 Store User Data to EEMEM15

Table 8. Addresses for Reading (Restoring) RDAC Settings and User Data from EEMEM (R/W = 1, CMD/REG = 0, EE/RDAC = 1)

A4 A3 A2 A1 A0 Data Byte Description 0 0 0 0 0 Read RDAC0 setting from EEMEM0 0 0 0 0 1 Read RDAC1 setting from EEMEM1 0 0 0 1 0 Read RDAC2 setting from EEMEM2 0 0 0 1 1 Read RDAC3 setting from EEMEM3 0 0 1 0 0 Read User Data from EEMEM4 0 0 1 0 1 Read User Data from EEMEM5 0 0 1 1 0 Read User Data from EEMEM6 0 0 1 1 1 Read User Data from EEMEM7 0 1 0 0 0 Read User Data from EEMEM8 0 1 0 0 1 Read User Data from EEMEM9 0 1 0 1 0 Read User Data from EEMEM10 0 1 0 1 1 Read User Data from EEMEM11 0 1 1 0 0 Read User Data from EEMEM12 0 1 1 0 1 Read User Data from EEMEM13 0 1 1 1 0 Read User Data from EEMEM14 0 1 1 1 1 Read User Data from EEMEM15

User can store any 64 RDAC settings for AD5253 or 256 RDAC settings for AD5254, not limited to current RDAC wiper setting, directly to EEMEM.

AD5253/AD5254

Rev. 0 | Page 17 of 28

1 READ

842-0-009

Figure 29. RDAC Current Read. Restricted to Previously Selected Address Stored in the Register.

0 WRITE

038

REPEATED START 1 READ

Figure 30. RDAC or EEMEM Random Read

0 WRITE 03842-0-011

1 CMD

RDAC SLAVE ADDRESS

Figure 31. RDAC Quick Command Write (Dummy Write)

From Master to Slave

From Slave to Master

S = Start Condition P = Stop Condition

A = Acknowledge (SDA Low)

A = Not Acknowledge (SDA High)

AD1, AD0 = I 2C Device Address Bits. Must match with the logic states at Pins AD1, AD0. R/W = Read Enable Bit, Logic High/Write Enable Bit, Logic Low

CMD/REG = Command Enable Bit, Logic High/Register Access Bit, Logic Low C3, C2, C1, C0 = Command Bits

A2, A1, A0 = RDAC/EEMEM Register Addresses

Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0)

C3 C2 C1 C0 Command Description 0 0 0 0 NOP 0 0 0 1 Restore EEMEM (A1, A0) to RDAC (A1, A0)10 0 1 0 Store RDAC (A1, A0) to EEMEM (A1, A0) 0 0 1 1 Decrement RDAC (A1, A0) 6 dB 0 1 0 0 Decrement All RDACs 6 dB 0 1 0 1 Decrement RDAC (A1, A0) One Step 0 1 1 0 Decrement All RDACs One Step 0 1 1 1 Reset: Restore EEMEMs to All RDACs 1 0 0 0 Increment RDACs (A1, A0) 6 dB 1 0 0 1 Increment All RDACs 6 dB 1 0 1 0 Increment RDACs (A1, A0) One Step 1 0 1 1 Increment All RDACs One Step 1 1 0 0 Reserved : : : :

1 1 1 1 Reserved

RDAC/EEMEM Quick Commands

AD5253/AD5254 feature 12 quick commands that facilitate easy manipulation of RDAC wiper settings as well as provide RDAC-to-EEMEM storing and restoring functions. The command format is shown in Figure 31, and the command descriptions are shown in Table 9.

When using a quick command, issuing a third byte is not needed but is allowed. The quick commands Reset and Store RDAC to EEMEM require acknowledge polling to determine whether the command has finished executing.

This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to the idle state.

AD5253/AD5254

Rev. 0 | Page 18 of 28

Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)

A4 A3 A2 A1 A0 Data Byte Description 1 1 0 0 0 Sign and 7-Bit Integer Values of RDAC0 Tolerance (Read Only) 1 1 0 0 1 8-Bit Decimal Value of RDAC0 Tolerance (Read Only) 1 1 0 1 0 Sign and 7-Bit Integer Values of RDAC1 Tolerance (Read Only) 1 1 0 1 1 8-Bit Decimal Value of RDAC1 Tolerance (Read Only) 1 1 1 0 0 Sign and 7-Bit Integer Values of RDAC2 Tolerance (Read Only) 1 1 1 0 1 8-Bit Decimal Value of RDAC2 Tolerance (Read Only) 1 1 1 1 0 Sign and 7-Bit Integer Values of RDAC3 Tolerance (Read Only) 1 1 1 1 1 8-Bit Decimal Value of RDAC3 Tolerance (Read Only)

03842-0-012

D7D6D5D4D3D2D1D0SIGN

SIGN

7 BITS FOR INTEGER NUMBER 26

D7D6D5D4D3D2D1D08 BITS FOR DECIMAL NUMBER

2–8

2–1

2–2

2–3

2–4

2–5

2–6

2–7

Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. Unit is %. Only Data Bytes Are Shown.

R AB Tolerance Stored in Read-Only Memory

AD5253/AD5254 feature patented R AB tolerances storage in the nonvolatile memory. The tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. The knowledge of the stored tolerance, which is the average of R AB overall codes (Figure 29), allows users to predict R AB accurately. This feature is valuable for precision, rheostat mode, or open-loop applications where knowledge of absolute resistance is critical.

The stored tolerances reside in the read-only memory, and are expressed in percent. The tolerance is coded in sign magnitude binary, 16 bits long, and is stored in two memory locations (see Table 10). The data format of the tolerance is the sign magni-tude binary format; an example is shown in Figure 32. In the first memory location of the eight data bits, the MSB is designated for the sign (0 = + and 1= –) and the 7 LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. As shown in Table 8 and Figure 32, for example, if the rated R AB = 10 k? and the data readback from address 11000 shows 0001 1100 and address 11001 shows 0000 1111, then RDAC0 tolerance can be calculated as:

MSB: 0 = +

Next 7 MSB: 001 1100 = 28

8 LSB: 0000 1111 = 15 × 2–8 = 0.06 Tolerance = +28.06% and therefore R AB_ACTUAL = 12.806 k? EEMEM Write-Acknowledge Polling

After each write operation to the EEMEM registers, an internal write cycle begins. The I 2C interface of the device is disabled. In order to determine if the internal write cycle is complete and the I 2C interface is enabled, interface polling can be executed. I 2C interface polling can be conducted by sending a start condi-tion followed by the slave address + the write bit. If the I 2C

interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Other-wise, I 2C interface polling can be repeated until it succeeds. Commands 2 and 7 also require acknowledge polling.

EEMEM Write Protection

Setting the WP pin to a logic LOW after EEMEM programming protects the memory and RDAC registers from future write operations. In this mode, the EEMEM and RDAC read

operations operate as normal. When write protection is enabled, commands 1 (restore from EEMEM to RDAC) and 7 (reset) function normally to allow RDAC settings to be refreshed from the EEMEM to the RDAC registers.

AD5253/AD5254

Rev. 0 | Page 19 of 28

I 2C COMPATIBLE 2-WIRE SERIAL BUS

FRAME 1

SLAVE ADDRESS BYTE

AD525x

STOP BY MASTER

03824-0-013

Figure 33. General I 2C Write Pattern

03824-0-014

ACK.BY AD525x

NO ACK.BY MASTER

STOP BY MASTER

STARTBY MASTER

Figure 34. General I 2

C Read Pattern

The first byte of the AD5253/AD5254 is a slave address byte (see Figure 24 and Figure 25). It has a 7-bit slave address and an R/W bit. The 5 MSB of the slave address are 01011, and the following 2 LSB are determined by the states of the AD1 and AD0 pins. AD1 and AD0 allow the user to place up to four AD5253/AD5254s on one bus. The 2-wire I 2C serial bus protocol operates as follows:

AD5253/AD5254 can be controlled via an I 2C compatible serial bus, and are connected to this bus as slave device. The 2-wire I 2C serial bus protocol follows (see Figure 33 and Figure 34): 1. The master initiates a data transfer by establishing a start

condition, such that SDA goes from high to low while SCL is high (Figure 33). The following byte is the slave address byte, which consists of the 5 MSB of a slave address defined as 01011. The next two bits are AD1 and AD0, I 2C device address bits. Depending on the states of their AD1 and AD0 bits, four AD5253/AD5254s can be addressed on the same bus. The last LSB, the R/W bit, determines whether data is read from or written to the slave device.

The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called an acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. In the write mode (except when restoring EEMEM to the

RDAC register), there is an instruction byte that follows the slave address byte. The MSB of the instruction byte labeled CMD/REG . MSB = 1 enables CMD, the command

instruction byte; MSB = 0 enables general register writing. The third MSB in the instruction byte, labeled EE/RDAC , is true only when MSB = 0 or in general writing mode. EE enables the EEMEM register and REG enables the RDAC

register. The 5 LSB, A4 to A0, designed the addresses of the EEMEM and RDAC registers; see Figure 27 and Figure 28. When MSB = 1 or when in CMD mode, the four bits following MSB are C3 to C1, which correspond to 12 predefined EEMEM controls and quick commands; there are also four factory reserved commands. The 3 LSB—A2, A1, and A0—are 4-channel RDAC addresses (see

Figure 31). After acknowledging the instruction byte, the last byte in the write mode is the data byte. Data is

transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (Figure 33).

3. In current read mode, the RDAC0 data byte immediately

follows the acknowledgment of the slave address byte. After an acknowledgement, RDAC1 follows, then RDAC2, and so on (there is a slight difference in write mode, where the last eight data bits representing RDAC3 data are followed by a no acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 34). Another reading method, random read method, is shown in Figure 30. 4. When all data bits have been read or written, a stop

condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop

condition (Figure 33). In read mode, the master issues a no acknowledge for the ninth clock pulse, i.e., the SDA line remains high. The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (Figure 34).

AD5253/AD5254

Rev. 0 | Page 20 of 28

THEORY OF OPERATION

The AD5253/AD5254 are quad-channel digital potentiometers in 1 k?, 10 k?, 50 k?, or 100 k? that allow 64/256 linear resis-tance step adjustments. The AD5253/AD5254 employ double-gate CMOS EEPROM technology that allows resistance settings and user-defined data stored in the EEMEM registers. The

EEMEM is nonvolatile such that settings remain when power is removed. The RDAC wiper settings are restored from the nonvolatile memory settings during device power-up and can also be restored at any time during operation.

The AD5253/AD5254 resistor wiper positions are determined by the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the device’s serial I 2C interface. The format of the data-words and the commands to program the RDAC registers are discussed in the I 2C Interface section.

The four RDAC registers have corresponding EEMEM memory locations that provide nonvolatile storage of resistor wiper position settings. The AD5253/AD5254 provide commands to store the RDAC register contents to their respective EEMEM memory locations. During subsequent power-on sequences, the RDAC registers are automatically loaded with the stored value. Whenever the EEMEM write operation is enabled, the device activates the internal charge pump and raises the EEMEM cell gate bias voltage to a high level; this essentially erases the

current content in the EEMEM register and allows subsequent storage of the new content. Saving data to an EEMEM register consumes about 35 mA of current and lasts approximately 26 ms. Because of charge pump operation, all RDAC channels may experience noise coupling during the EEMEM writing operation.

The EEMEM restore time in power-up or during operation is about 300 μs. Note that the power-up EEMEM refresh time depends on how fast V DD reaches its final value. As a result, any supply voltage decoupling capacitors limit the EEMEM restore time during power-up. Figure 20 shows the power-up profile where V DD , without any decoupling capacitors connected to it, is applied with a digital signal. The device initially resets the RDACs to midscale before restoring the EEMEM contents. In addition, users should issue a NOP command 0 immediately after using command 1 to restore the EEMEM setting to RDAC, thereby minimizing supply current dissipation. Reading user data directly from EEMEM does not require a similar NOP command execution.

In addition to the movement of data between RDAC registers and EEMEM memory, the AD5253/AD5254 provide other shortcut commands that facilitate the user’s programming needs, as shown in Table 11.

Table 11. AD5253/AD5254 Quick Commands

Commmand Description 0 NOP. 1 Restore EEMEM Content to RDAC. User should

issue NOP immediately after this command to conserve power.

2 Store RDAC Register Setting to EEMEM.

3 Decrement RDAC 6 dB (Shift Data Bits Right).

4 Decrement All RDACs 6 dB (Shift All Data Bits

Right).

5 Decrement RDAC One Step.

6 Decrement All RDACs One Step.

7 Reset EEMEM Contents to All RDACs.

8 Increment RDAC 6 dB (Shift Data Bits Left).

9 Increment All RDACs 6 dB (Shift All Data Bits

Left).

10 Increment RDAC One Step. 11 Increment All RDACs One Step. 12–15 Reserved.

LINEAR INCREMENT AND DECREMENT COMMANDS

The increment and decrement commands (#10, #11, #5, #6) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the

controller to send just an increment or decrement command to the AD5253/AD5254. The adjustments can be directed to a single RDAC or to all four RDACs.

±6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)

The AD5253/AD5254 accommodate ±6 dB adjustments of the RDAC wiper positions by shifting the register contents to left/ right for increment/decrement operations, respectively. Com-mands 3, 4, 8, and 9 can be used to increment or decrement the wiper positions in 6 dB steps synchronously or asynchronously. Incrementing the wiper position by +6 dB is essentially

doubling the RDAC register value, while decrementing by –6 dB is halving the register content. Internally, the AD5253/AD5254 use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. The maximum number of adjustments is nine and eight steps for increment from zero scale and decrement from full scale, respectively. These

functions are useful for various audio/video level adjustments, especially white LED brightness settings where the visual responses of humans are more sensitive to large rather small adjustments.