如何读单片机的时序图

U A H

CPE/EE 421Microcomputers

WEEK #10

2

U A H Interpreting the Timing Diagram

The 68000 Read Cycle

Alan Clements

3

U A H

Actual behavior of a D flip-flop

Timing Diagram of a Simple Flip-Flop

Idealized form of the timing diagram

Data hold time

Data setup time

Max time for output to become valid after clock

Alan Clements

4

U A H An alternative form of the timing diagram

General form of the timing diagram

In state S1 a new address becomes

We are interested in the relationship

The earliest time at which the memory can begin to access data is measured from the point

Data must be valid

seconds before

Alan Clements

35

U A H

Timing Example

?68000 clock 8 MHz t CYC = 125 ns ?68000 CPU t CLAV = 70 ns ?68000 CPU t DICL = 15 ns ?What is the minimum t acc ??3t CYC =t CLAV +t acc +t DICL ?375 = 70 +t acc + 15?

t acc = 290 ns