文档库

最新最全的文档下载
当前位置:文档库 > CFP-MSA_CFP4_HW-Spec-rev0.1

CFP-MSA_CFP4_HW-Spec-rev0.1

CFP-MSA_CFP4_HW-Spec-rev0.1

CFP MSA

CFP4 Hardware Specification

Revision 0.1

2March 2014

CFP-MSA_CFP4_HW-Spec-rev0.1

Description:

This CFP Multi-Source Agreement (MSA) defines the CFP4 form factor of an optical transceiver to support 40Gbit/s and 100Gbit/s interfaces for Ethernet, Telecommunication and other applications. The members of the CFP MSA have authored this document to provide an industry standard form factor for new and emerging high speed communications interfaces. Specifications provided in this document are given as a “delta” to the CFP MSA Hardware Specification Rev.1.4, June 7, 2010 or the CFP MSA CFP2 Hardware Specification Rev. 1.0, July 31, 2013.

CFP-MSA_CFP4_HW-Spec-rev0.1

CFP-MSA_CFP4_HW-Spec-rev0.1

CONTENTS

REVISION HISTORY (4)

TABLE LIST (5)

FIGURE LIST (6)

REFERENCE DOCUMENTS (7)

1 GENERAL (8)

1.1SCOPE (8)

1.2CFP4FUNCTIONAL BLOCK DIAGRAM (8)

1.3FUNCTIONAL DESCRIPTION (9)

1.3.1 Hot Pluggable (9)

2 CFP4 HARDWARE SIGNALING PINS (9)

2.1H ARDWARE C ONTROL P INS (9)

2.2H ARDWARE C ONTROL P INS:F UNCTIONAL D ESCRIPTION (9)

2.2.1 Programmable Control (PRG_CNTL) (10)

2.2.1.1 Programmable Control 1 Pin (10)

2.2.1.2 Programmable Control 2 Pin (10)

2.2.1.3 Programmable Control 3 Pin (10)

2.2.1.4 Hardware Interlock (10)

2.2.2 TX Disable Pin (10)

2.3H ARDWARE A LARM P INS (10)

2.4H ARDWARE A LARM P INS:F UNCTIONAL D ESCRIPTION (11)

2.4.1 Programmable Alarm (PRG_ALRM) (11)

2.4.1.1 Programmable Alarm 1 Pin (11)

2.4.1.2 Programmable Alarm 2 Pin (11)

2.4.1.3 Programmable Alarm 3 Pin (11)

2.4.3 Receiver Loss of Signal Pin (11)

2.5M ANAGEMENT I NTERFACE P INS (11)

2.6CFP4M ANAGEMENT I NTERFACE H ARDWARE D ESCRIPTION (12)

2.7H ARDWARE S IGNALING P IN E LECTRICAL S PECIFICATIONS (12)

2.7.1 Control & Alarm Pins: 3.3V LVCMOS Electrical Characteristics (12)

2.7.2 MDIO Interface Pins: 1.2V LVCMOS Electrical Characteristics (13)

2.8H ARDWARE S IGNALING P IN T IMING R EQUIREMENTS (14)

3 MODULE MANAGEMENT INTERFACE DESCRIPTION (15)

4 PERFORMANCE SPECIFICATIONS (15)

4.1OPERATING ENVIRONMENT (15)

4.2POWER SUPPLIES AND POWER DISSIPATION (15)

4.2.1 Voltage power supply and power dissipation (15)

4.2.2 Inrush current (15)

4.2.3 Turn-off current (15)

4.2.4 Power Supply Noise Susceptibility (15)

4.2.5 Grounding (16)

4.3OPTICAL CHARACTERISTICS (16)

4.3.1 Optical Specifications (16)

4.4HIGH SPEED ELECTRICAL CHARACTERISTICS (16)

4.4.1 25 Gbit/s Transmitter Data (and Clock) (17)

4.4.2 25 Gbit/s Receiver Data (and Clock) (17)

4.4.3 10 Gbit/s Transmitter Data (and Clock) (17)

4.4.4 10 Gbit/s Receiver Data (and Clock) (17)

4.4.5 Loopback (Optional) (17)

4.4.6 Reference Clock (Optional) (19)

4.4.7 Transmitter Monitor Clock (Optional) (19)

4.4.8 Receiver Monitor Clock (Optional) (19)

4.4.9 Monitor Clock (Optional) (20)

5 MECHANICAL SPECIFICATIONS (21)

5.1M ECHANICAL O VERVIEW (21)

5.2E LECTRICAL C ONNECTOR (22)

5.2.1 Module Plug Connector (22)

5.2.2 Host Connector (23)

5.2.3 Connector Pin Contact Mating (24)

5.3CFP4M ODULE D IMENSIONS (25)

5.3.1 CFP4 Mechanical Surface Characteristics (26)

5.3.2 CFP4 Insertion & Extraction (26)

5.4H OST S YSTEM D IMENSIONS (26)

5.5R IDING H EAT S INK (27)

5.6O PTICAL C ONNECTORS (28)

5.6.1 Optional Optical LC Connector Position for Telecom Applications (28)

5.7E LECTRICAL C ONNECTORS (29)

5.8P IN A SSIGNMENT (29)

5.9CFP4B AIL L ATCH C OLOR C ODING AND L ABELING (33)

6 REGULATORY COMPLIANCE (34)

CFP-MSA_CFP4_HW-Spec-rev0.1

TABLE LIST

Table 1-1: Control Pins (9)

Table 1-2: Hardware Alarm Pins (11)

Table 1-3: Management Interface Pins (MDIO) (12)

Table 4-1: Voltage Power Supply (16)

Table 4-2: Optional Reference Clock Characteristics (19)

Table 4-3: Optional Monitor Clock Characteristics (20)

Table 4-4: CFP4 Module Clocking Signals (20)

Table 5-1: CFP4 Mechanical Characteristics (26)

Table 5-2: CFP4 Module Insertion, Extraction Forces (26)

Table 5-3: Optical Connectors (28)

Table 5-4: CFP4 Host Connector Assembly (29)

Table 5-5: CFP4 4x25Gbpt/s Pin Map (31)

Table 5-6: CFP4 Bottom Row Piin Description for 4x25 Gbit/s Applications (32)

Table 5-7: CFP4 Bail Latch Color Coding (33)

FIGURE LIST

Figure 1-1: CFP4 Functional Block Diagram (8)

Figure 2-1: Reference +3.3V LVCMOS Output Termination (12)

Figure 2-2: Reference 3.3V LVCMOS Input Termination (13)

Figure 2-3: Reference MDIO Interface Termination (14)

Figure 4-1: High Speed I/O for Data and Clocks (17)

Figure 4-2: CFP4 Module Optional Loopback Orientation (18)

Figure 4-3: Example of Clocking for 4 x 25 Gbit/s CFP4 Applications (21)

Figure 4-4: Example of Clocking for 4 x 10 Gbit/s CFP4 Applications (21)

Figure 5-1: CFP4 Module & CFP4 Module Mated in Host Quad Port System (22)

Figure 5-2: Host Cage System and Mounting Method Overview (22)

Figure 5-3: CFP4 Module Plug Connector Assembly (23)

Figure 5-4: CFP4 Quad Port Host Connector Cover Assembly (23)

Figure 5-5: CFP4 Host Connector Assembly (24)

Figure 5-6: CFP4 Pin Map Connector Engagement (24)

Figure 5-7: CFP4 Module Dimension Overview (25)

Figure 5-8: Riding Heat Sink (27)

Figure 5-9: Host Cage Top Surface Opening (27)

Figure 5-10: CFP4 Connector Pin Map Orientation (30)

Figure 5-11: CFP4 Module Label Recess (33)

REFERENCE DOCUMENTS

[1] CFP MSA Hardware Specification, Revision 1.4, June 7, 2010.

[2] CFP MSA CFP2 Hardware Specification, Revision 1.0, July 31, 2013.

[3] CFP MSA Management Interface Specification, Version 2.2, July 01, 2013.

[4] IEEE P802.3bm, 40Gbit/s and 100Gbit/s Operation Over Fiber Optic Cables Task Force,

http://www.wendangku.net/doc/5a9de02a8bd63186bdebbc4d.html/3/bm/index.html

[5] IEEE Std 802.3TM-2012, Annexes 83A, 83B, and 86A.

[6] IEEE Std 802.3TM-2012, Cl. 45, Management Data Input/Output (MDIO) Interface.

[7] ITU-T Recommendation G.709 (2012) Interfaces for the Optical Transport Network (OTN).

[8] ITU-T Recommendation G.707 (2007) Network node interface for the synchronous digital hierarchy (SDH).

[9] OIF-CEI-3.0, http://www.wendangku.net/doc/5a9de02a8bd63186bdebbc4d.html/public/documents/OIF_CEI_03.0.pdf

[10] SFF Committee INF-8077i 10 Gigabit Small Form Factor Pluggable Module

[11] SFF Committee SFF-8431 Specifications for Enhanced Small Form Factor Pluggable Module SFP+

1 GENERAL

1.1 SCOPE

This CFP Multi-Source Agreement (MSA) defines the CFP4 form factor of an optical transceiver which can support 40Gbit/s and 100Gbit/s interfaces for Ethernet, ITU-T OTN and other applications. Specifications provided in this document are given as a “delta” to the CFP MSA Hardware Specification Rev.1.4 or the CFP2 Hardware Specification Rev. 1.0.

The CFP4 electrical interface will vary by application, but the nominal signaling lane rate is 25Gbit/s per lane and documentation is provided in OIF CEI-28G-VSR, CAUI-4, and OTL4.4 electrical interface specifications. The CFP4 electrical interface can also optionally support a nominal signaling lane rate of 10Gbit/s and documentation is provided in XLAUI, XLPPI, OTL3.4 and STL256.4. The CFP4 module may be used to support single mode and multimode fiber optics.

The CFP4 modules and the host system are hot-pluggable. The module or the host system shall not be damaged by insertion or removal of the module.

CFP MSA is an acronym for 100G1 Form factor Pluggable Multi-Source Agreement.

1.2 CFP4 FUNCTIONAL BLOCK DIAGRAM

CFP-MSA_CFP4_HW-Spec-rev0.1

Figure 1-1: CFP4 Functional Block Diagram

1 C = 100 in Roman numerals; Centum

1.3 FUNCTIONAL DESCRIPTION

The CFP4 module is a hot pluggable form factor designed for optical networking applications. The module size has been chosen to accommodate a wide range of power dissipations and applications. The module electrical interface has been generically specified to allow for supplier-specific customization around various “4 x 25Gbit/s” and 4 x 10Gbit/s interfaces.

1.3.1 Hot Pluggable

A CFP4 module is defined to be hot pluggable. Hot Pluggable is defined as permitting module plugging and unplugging with Vcc applied, with no module damage and predictable module behavior as per the State Transition Diagram. As shown in Figure 5-6: Pin Map Connector Engagement, the Module Absent

(MOD_ABS) pin and Module Low Power (MOD_LOPWR) pin are physically guaranteed to be one of the last pins to mate.

2 CFP4 HARDWARE SIGNALING PINS

The control and status reporting functions between a host and a CFP4 module use non-data control and status reporting pins on the 56-pin connector. The control and status reporting pins work together with the MDIO interface to form a complete HOST-CFP4 management interface. The status reporting pins provide status reporting. There are three (3) Hardware Control pins, two (2) Hardware Alarm pins, and six (6) pins dedicated to the MDIO interface. Specification of the CFP4 hardware signaling pins are given in Ref.[1] with the following changes listed in this document.

2.1 Hardware Control Pins

The CFP4 Module supports real-time control functions via hardware pins, listed in

Table 1-1. Specifications of the CFP4 hardware control pins are given in Ref.[1], with the following changes listed below.

Table 1-1: Control Pins

CFP-MSA_CFP4_HW-Spec-rev0.1

enabled

2 Per CFP MSA Management Interface Specification[3] when PRG_CNTL is configured for this pin.

3Pull-Up resistor (4.7 kOhm to 10 kOhm) is located within the CFP4 module

4Pull-Down resistor (4.7 kOhm to 10 kOhm) is located within the CFP4 module

2.2 Hardware Control Pins: Functional Description

2.2.1 Programmable Control (PRG_CNTL)

This control pin allows for the system to program certain controls via a Hardware pin. TX Disable Pin

(TX_DIS) is optionally configurable as Programmable Control 1 Pin after Reset. When Programmable Control 1 is configured, the default setting for Control 1 is control of the TX_DIS.

2.2.1.1 Programmable Control 1 Pin

Programmable Control 1 Pin is an input pin from the Host, operating with programmable logic. This pin is pulled up in the CFP4 module. It can be re-programmed over MDIO registers to another MDIO control register while the module is in any steady state except Reset. The CFP MSA specifies that the default function be TX Disable (TX_DIS) with active-high logic. If the other function besides TX_DIS is configured for this pin, there is no way to assert TX disable via a hardware pin.

2.2.1.2 Programmable Control 2 Pin

Not supported in CFP4 module

2.2.1.3 Programmable Control 3 Pin

Not supported in CFP4 module

2.2.1.4 Hardware Interlock

Not supported in CFP4 module

2.2.2 TX Disable Pin

TX Disable Pin (TX_DIS) is an input pin from the Host, operating with active-high logic. This pin is pulled up in the CFP4. When TX_DIS is asserted, all of the optical outputs inside a CFP4 module shall be turned off. When this pin is de-asserted, transmitters in a CFP4 module shall be turned on according to a predefined TX turned-on process which is defined by the state diagram shown in the “CFP MSA Management Interface Specification”. A maximum time is defined for the transmitter turn-on process. This time is vendor and/or technology specific and the value is stored in a MDIO register.

This pin can be optionally configured as Programmable Control 1 Pin after Reset. One MDIO register which defines if the module supports this optional configuration or not is prepared in NVR region.

Please refer to Ref.[3] for more details.

2.3 Hardware Alarm Pins

The CFP4 Module supports alarm hardware pins as listed in Table 1-2. Specifications of the CFP4 hardware alarm pins are given in Ref.[1].

Table 1-2: Hardware Alarm Pins

CFP-MSA_CFP4_HW-Spec-rev0.1

1 When Programmable Alarm is configured, MSA Default is HIPWR_ON.

2Active High per CFP MSA MIS Ref. [3] when PRG_ALRM is configured for this pin.

3 Pull-Down resistor (<100Ohm) is located within the CFP

4 module. Pull-up should be located on the host.

2.4 Hardware Alarm Pins: Functional Description

2.4.1 Programmable Alarm (PRG_ALRM)

This alarm pin allows for the system to program module supported alarms to Hardware pin. The intention is to allow for maximum design and debug flexibility.

2.4.1.1 Programmable Alarm 1 Pin

Programmable Alarm 1 Pin (PRG_ALRM1) is an output pin to the Host, operating with programmable logic. This pin can be re-programmed over MDIO registers to another MDIO alarm register while the module is in any steady state except Reset. CFP-MSA specifies the default function to be Receiver Loss of Signal (RX_LOS) indicator with active-high logic.

2.4.1.2 Programmable Alarm 2 Pin

Not supported in CFP4 module

2.4.1.3 Programmable Alarm 3 Pin

Not supported in CFP4 module

2.4.3 Receiver Loss of Signal Pin

The Receiver Loss of Signal Pin (RX_LOS) is an output pin to the Host, operating with active-high logic. When asserted, it indicates received optical power in the CFP4 module is lower than the expected value. The optical power at which RX_LOS is asserted may be specified by other governing documents and the CFP4 module vendor as the alarm threshold level is application specific. The RX_LOS is the logic OR of the LOS signals from all the input receiving channels in a CFP4 module.

This pin can be optionally configured as Programmable Alarm 1 Pin after Reset. One MDIO register which defines if the module supports this optional configuration or not is prepared in NVR region.

Please refer to Ref.[3] for more details.

2.5 Management Interface Pins

The CFP4 Module supports alarm, control and monitor functions via an MDIO bus. Upon module initialization, these functions are available. CFP4 MDIO electrical interface consists of 6pins including 2pins for MDC and MDIO, 3 Physical Port Address pins and th Global Alarm pin. MDC is the MDIO Clock line driven by the host and MDIO is the bidirectional data line driven by both the host and module depending upon the data directions. The CFP4 MDIO pins are listed in Table 1-3. Specifications of the CFP4 hardware management interface pins are given in Ref.[2] with the following changes listed below.

Table 1-3: Management Interface Pins (MDIO)

CFP-MSA_CFP4_HW-Spec-rev0.1

2.6 CFP4 Management Interface Hardware Description

Per specifications given in Ref.[2] .

2.7 Hardware Signaling Pin Electrical Specifications

2.7.1 Control & Alarm Pins:

3.3V LVCMOS Electrical Characteristics

The hardware control and alarm pins specified as 3.3V LVCMOS functionally described above shall meet the characteristics described in Ref.[1]. Reference figures are provided regarding pin termination; see Figure 2-1 and 2-2.

Figure 2-1: Reference +3.3V LVCMOS Output Termination

CFP-MSA_CFP4_HW-Spec-rev0.1

+3.3V

4.7k ~ 10k ohm

+3.3V

4.7k ~ 10k ohm

Figure 2-2: Reference 3.3V LVCMOS Input Termination

CFP-MSA_CFP4_HW-Spec-rev0.1

2.7.2 MDIO Interface Pins: 1.2V LVCMOS Electrical Characteristics

The MDIO interface pins specified as 1.2V LVCMOS functionally described above shall meet the characteristics described in Ref.[1]. Reference figure is provided regarding pin termination; see Fig.2-3.

Figure 2-3: Reference MDIO Interface Termination 2

CFP-MSA_CFP4_HW-Spec-rev0.1

2.8 Hardware Signaling Pin Timing Requirements

Per specifications given in Ref.[2]

2

The MSA recommends host termination resistor value of 560 Ohms, which provides the best balance of performance

for both open-drain and active tri-state driver in the module. Host termination resistor values below 560Ohms are allowed, to a minimum of 250 Ohms, but this degrades active driver performance. Host termination resistor values above 560 Ohms are allowed but this degrades open-drain driver performance.

The above drawings, with maximum host load capacitance of 200pF, also define the measurement set-up for module MDC timing verification. The capacitor in the drawing indicates the stray capacitance on the line. Don’t put any physical capacitor on the line.

. 2 V

. 2 V

250 ohm

< = 200 p F

250 o hm

< = 200 p F

3 MODULE MANAGEMENT INTERFACE DESCRIPTION

The CFP4 module utilizes MDIO IEEE Std 802.3TM-2012 clause 45 [8] for its management interface. The CFP4 MDIO implementation is defined in a separate document entitled, “CFP MSA Management Interface Specification” [3]. When multiple CFP4 modules are connected via a single bus, a particular CFP4 module can be selected by using the Physical Port Address pins.

4 PERFORMANCE SPECIFICATIONS

4.1 OPERATING ENVIRONMENT

Per specifications given in Ref. [1]

4.2 POWER SUPPLIES AND POWER DISSIPATION

4.2.1 Voltage power supply and power dissipation

The CFP4 module power supply and maximum power dissipation specifications are defined in Table 4-1.

4.2.2 Inrush current

The inrush current on the 3.3V power supply shall be limited by the CFP4 module to assure a maximum rate of change defined in Table 4-1.

4.2.3 Turn-off current

The CFP4 module shall limit the turn-off current to assure a maximum rate of change per Table 4-1.

4.2.4 Power Supply Noise Susceptibility

A host system will supply stable power to the module and guarantee that noise & ripple on the power supply does not exceed that defined in Table 4-1. A possible example of a power supply filtering circuit that might be used on the host system is a PI C-L-C filter. A module will meet all electrical requirements and remain fully operational in the presence of noise on the 3.3V power supply which is less than that defined in the table 4-1. The component values of power supply noise filtering circuit, such as the capacitor and inductor, must be selected such that maximum Inrush and Turn-off current does not cause voltage transients which exceed the absolute maximum power supply voltage, all specified in Table 4-1.

Table 4-1: Voltage Power Supply

CFP-MSA_CFP4_HW-Spec-rev0.1

1Maximum current per pin shall not exceed 500mA. Those power classes for which the maximum current per pin exceeds 500mA will require agreement from an electrical connector supplie r.

2 For modules which present a small capacitive load to the host during hot plug (C <= 500nF), the portion of the inrush current due to charging the capacitor can be excluded from the total inrush current which must meet the maximum limit specification.

4.2.5 Grounding

Per specifications given in Ref. [1].

4.3 OPTICAL CHARACTERISTICS

4.3.1 Optical Specifications

The CFP4 module will comply with standardized optical specifications such as the optical reaches specified in IEEE for datacom applications or in ITU-T for telecom applications. Some of the relevant reference documents are: IEEE Std. 802.3TM-2012, Telcordia GR-253, ITU-T G.691, ITU-T G.692, ITU-T G.693, and ITU-T G.959, ITU-T G.709.

4.4 HIGH SPEED ELECTRICAL CHARACTERISTICS

The CFP4 Module high speed electrical interface supports the following configurations:

1) 4 tx lanes + 4 rx lanes, each at 25 Gbit/s;

2) 4 tx lanes + 4 rx lanes, each at 10 Gbit/s;

The high speed electrical interface shall be AC-coupled within the CFP4 module as is shown in Figure 4-1.

Figure 4-1: High Speed I/O for Data and Clocks

CFP-MSA_CFP4_HW-Spec-rev0.1

4.4.1 25 Gbit/s Transmitter Data (and Clock)

Per specifications given in Ref. [2].

4.4.2 25 Gbit/s Receiver Data (and Clock)

Per specifications given in Ref. [2].

4.4.3 10 Gbit/s Transmitter Data (and Clock)

The 10 Gbit/s Transmitter Data is defined in IEEE Std. 802.3TM-2012 Annex 83A for XLPPI and Annex 83B for XLAUI, or XFI in SFF INF-8077i and SFI in SFF SFF-8431. Figure 4-1 shows the recommended termination for these circuits. Alternate signaling logic are OTL3.4 which are specified in ITU-T Recommendation G.709. Lane orientation and designation is specified in the pin-map tables given in Section 5.

4.4.4 10 Gbit/s Receiver Data (and Clock)

The 10 Gbit/s Transmitter Data is defined in IEEE Std. 802.3TM-2012 Annex 83A for XLPPI and Annex 83B for XLAUI, or XFI in SFF INF-8077i and SFI in SFF SFF-8431. Figure 4-1 shows the recommended termination for these circuits. Alternate signaling logic are OTL3.4 which are specified in ITU-T Recommendation G.709. Lane orientation and designation is specified in the pin-map tables given in Section 5.

4.4.5 Loopback (Optional)

The CFP4 module may optionally support loopback functionality. Loopback commands are accessed via the MDIO management interface. Recommended loopback orientation implementation is TX0 to RX0. The host loopback and the network loopback are oriented per Figure 4-2 shown below. The capability to support the loopback functionality is dependent upon the interface IC technology, labeled as “Interface IC(s)” block in the figure. The CFP MSA module vendor will specify which loopback functionality, if any, is supported. For details on controlling the loopback mode, please refer to Ref. [3].

Figure 4-2: CFP4 Module Optional Loopback Orientation

CFP-MSA_CFP4_HW-Spec-rev0.1

4.4.6 Reference Clock (Optional)

For 4 x 25 Gbit/s host electrical interface applications, the host may supply a reference clock (REFCLK) at 1/160 electrical lane rate. The CFP4 module may use the 1/160 reference clock for transmitter path retiming, for example for Datacom applications.

The host may optionally supply a reference clock (REFCLK) at 1/40 electrical lane rate for 4 x 25 Gbit/s applications. The CFP4 module may optionally use the 1/40 reference clock for transmitter path retiming, for example for Telecom applications.

For 4 x 10 Gbit/s host electrical interface applications, the host may supply a reference clock (REFCLK) at 1/64 electrical lane rate. The CFP4 module may use the 1/64 reference clock for transmitter path retiming, for example for Datacom applications.

The host may optionally supply a reference clock (REFCLK) at 1/16 electrical lane rate for 4 x 10 Gbit/s applications. The CFP4 module may optionally use the 1/16 reference clock for transmitter path retiming, for example for Telecom applications.

When provided, the REFCLK shall be CML differential AC-coupled and terminated within the CFP4 module as shown in Figure 4-1. There is no required phase relationship between the data lanes and the reference clock, but the clock frequency shall not deviate more than specified in Table 4-2. For detailed clock characteristics please refer to the below table.

Table 4-2: Optional Reference Clock Characteristics

CFP-MSA_CFP4_HW-Spec-rev0.1

1 The spectrum of the jitter within this frequency band is undefined. The CFP4 shall meet performance requirements with worst case condition of a single jitter tone of 10ps RMS at any frequency between 10 KHz and 10 MHz.

2 For Telecom applications better jitter may be required.

An example of CFP4 clocking for 4 x 25 Gbit/s applications is shown in Figure 4-3. An example of CFP4 clocking for 4 x 10 Gbit/s applications is shown in Figure 4-4.

4.4.7 Transmitter Monitor Clock (Optional)

Not specified in this document.

4.4.8 Receiver Monitor Clock (Optional)

Not specified in this document.

TOP相关主题