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MC33151

MC34151, MC33151High Speed Dual MOSFET Drivers

The MC34151/MC33151 are dual inverting high speed drivers specifically designed for applications that require low current digital circuitry to drive large capacitive loads with high slew rates. These devices feature low input current making them CMOS and LSTTL logic compatible, input hysteresis for fast output switching that is independent of input transition time, and two high current totem pole outputs ideally suited for driving power MOSFETs. Also included is an undervoltage lockout with hysteresis to prevent erratic system operation at low supply voltages.

Typical applications include switching power supplies, dc to dc converters, capacitor charge pump voltage doublers/inverters, and motor controllers.

These devices are available in dual?in?line and surface mount packages.

Features

?Pb?Free Packages are Available

?Two Independent Channels with 1.5 A Totem Pole Output ?Output Rise and Fall Times of 15 ns with 1000 pF Load ?CMOS/LSTTL Compatible Inputs with Hysteresis ?Undervoltage Lockout with Hysteresis ?Low Standby Current

?Efficient High Frequency Operation

?Enhanced System Performance with Common Switching Regulator Control ICs

Pin Out Equivalent to DS0026 and MMH0026

Figure 1. Representative Block Diagram

https://www.wendangku.net/doc/5613500586.html,

See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

MAXIMUM RATINGS

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.

ELECTRICAL CHARACTERISTICS (V CC = 12 V, for typical values T A = 25°C, for min/max values T A is the only operating

ambient temperature range that applies [Note 3], unless otherwise noted.)

CC 2.Maximum package power dissipation limits must be observed.

3.T low =0°C for MC34151

T high =+70°C for MC34151?40°C for MC33151+85°C for MC33151

Figure 2. Switching Characteristics Test Circuit

Figure 3. Switching Waveform Definitions

Figure 4. Logic Input Current versus

Input Voltage

Figure 5. Logic Input Threshold Voltage

versus Temperature

Figure 6. Drive Output Low?to?High Propagation

Delay versus Logic Overdrive Voltage Figure 7. Drive Output High?to?Low Propagation Delay versus Logic Input Overdrive Voltage

V in , INPUT VOLTAGE (V)

, I N P U T C U R R E N T (m A )

i n I

T A , AMBIENT TEMPERATURE (°C)

V t h , I N P U T T H R E S H O L D V O L T A G E (V )

V in , INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)

t P L H (I N /O U T ), D R I V E O U T P U T P R O P A G A T I O N D E L A Y (n s )

V in , INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)

t P H L (I N /O U T )

, D R I V E O U T P U T P R O P A G A T I O N D E L A Y (n s )

5.0 V

Logic Input t r , t f ≤ 10 ns

Drive Output

2.4

2.01.61.20.80.402001601208040

080400

V CC = 12 V V in = 5 V to 0 V C L = 1.0 nF T A = 25°C

Figure 8. Propagation Delay

Figure 9. Drive Output Clamp Voltage

versus Clamp Current

Figure 10. Drive Output Saturation Voltage

versus Load Current Figure 11. Drive Output Saturation Voltage

versus Temperature

Figure 12. Drive Output Rise Time Figure 13. Drive Output Fall Time

90%

10%

50 ns/DIV

90%10%

10 ns/DIV 90%

10%

10 ns/DIV

I O , OUTPUT LOAD CURRENT (A)

V c l a m p , O U T P U T C L A M P V O L T A G E (V )

I O , OUTPUT LOAD CURRENT (A)

V s a t , O U T P U T S A T U R A T I O N V O L T A G E (V )

T A , AMBIENT TEMPERATURE (°C)

Drive Output

Logic Input

V CC = 12 V V in = 5 V to 0 V C L = 1.0 nF T A = 25°C

3.02.01.0

Figure 14. Drive Output Rise and Fall Time

versus Load Capacitance

Figure 15. Supply Current versus Drive Output

Load Capacitance

Figure 16. Supply Current versus Input Frequency Figure 17. Supply Current versus Supply Voltage

C L , OUTPUT LOA

D CAPACITANC

E (nF)

?t , O U T P U T R I S E -F A L L T I M E (n s )

t r C L , OUTPUT LOAD CAPACITANCE (nF)

I C C , S U P P L Y C U R R E N T (m A )

f, INPUT FREQUENCY (Hz)

I C C , S U P P L Y C U R R E N T (m A )

V CC , SUPPLY VOLTAGE (V)

f 806040

80604020

8.0

6.0

4.0

2.0

APPLICATIONS INFORMATION

Description

The MC34151 is a dual inverting high speed driver specifically designed to interface low current digital circuitry with power MOSFETs. This device is constructed with Schottky clamped Bipolar Analog technology which offers a high degree of performance and ruggedness in hostile industrial environments.

Input Stage

The Logic Inputs have 170 mV of hysteresis with the input threshold centered at 1.67 V . The input thresholds are insensitive to V CC making this device directly compatible with CMOS and LSTTL logic families over its entire operating voltage range. Input hysteresis provides fast output switching that is independent of the input signal transition time, preventing output oscillations as the input thresholds are crossed. The inputs are designed to accept a signal amplitude ranging from ground to V CC . This allows the output of one channel to directly drive the input of a second channel for master?slave operation. Each input has a 30 k W pulldown resistor so that an unconnected open input will cause the associated Drive Output to be in a known high state.

Output Stage

Each totem pole Drive Output is capable of sourcing and sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 W at 1.0A. The low ‘on’ resistance allows high output currents to be attained at a lower V CC than with comparative CMOS drivers. Each output has a 100 k W pulldown resistor to keep the MOSFET gate low when V CC is less than 1.4 V . No over current or thermal protection has been designed into the device, so output shorting to V CC or ground must be avoided.

Parasitic inductance in series with the load will cause the driver outputs to ring above V CC during the turn?on transition, and below ground during the turn?off transition.With CMOS drivers, this mode of operation can cause a destructive output latchup condition. The MC34151 is immune to output latchup. The Drive Outputs contain an internal diode to V CC for clamping positive voltage transients. When operating with V CC at 18 V , proper power supply bypassing must be observed to prevent the output ringing from exceeding the maximum 20 V device rating.Negative output transients are clamped by the internal NPN pullup transistor. Since full supply voltage is applied across

the NPN pullup during the negative output transient, power dissipation at high frequencies can become excessive. Figures 20, 21, and 22 show a method of using external Schottky diode clamps to reduce driver power dissipation. Undervoltage Lockout

An undervoltage lockout with hysteresis prevents erratic system operation at low supply voltages. The UVLO forces the Drive Outputs into a low state as V CC rises from 1.4 V to the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V, yielding about 500 mV of hysteresis.

Power Dissipation

Circuit performance and long term reliability are enhanced with reduced die temperature. Die temperature increase is directly related to the power that the integrated circuit must dissipate and the total thermal resistance from the junction to ambient. The formula for calculating the junction temperature with the package in free air is:

T J=T A + P D (R q JA)

where:T J =Junction Temperature

T A =Ambient Temperature

P D =Power Dissipation

R q JA=Thermal Resistance Junction to Ambient There are three basic components that make up total power to be dissipated when driving a capacitive load with respect to ground. They are:

P D=P Q + P C + P T

where:P Q =Quiescent Power Dissipation

P C =Capacitive Load Power Dissipation

P T =Transition Power Dissipation

The quiescent power supply current depends on the supply voltage and duty cycle as shown in Figure 17. The device’s quiescent power dissipation is:

P Q = V CC I CCL (1?D) + I CCH (D)

where:I CCL =Supply Current with Low State Drive

Outputs

I CCH =Supply Current with High State Drive

Outputs

D =Output Duty Cycle

The capacitive load power dissipation is directly related to the load capacitance value, frequency, and Drive Output voltage swing. The capacitive load power dissipation per driver is:

P C=V CC (V OH ? V OL) C L f

where:V OH =High State Drive Output V oltage

V OL =Low State Drive Output V oltage

C L =Load Capacitance

f =frequency

When driving a MOSFET, the calculation of capacitive load power P C is somewhat complicated by the changing gate to source capacitance C GS as the device switches. To aid in this calculation, power MOSFET manufacturers provide gate charge information on their data sheets. Figure 18 shows a curve of gate voltage versus gate charge for the ON Semiconductor MTM15N50. Note that there are three distinct slopes to the curve representing different input capacitance values. To completely switch the MOSFET ‘on’, the gate must be brought to 10 V with respect to the source. The graph shows that a gate charge Q g of 110 nC is required when operating the MOSFET with a drain to source voltage V DS of 400 V.

(

)

Q g, GATE CHARGE (nC)

8.0

4.0

Figure 18. Gate?To?Source Voltage

versus Gate Charge

The capacitive load power dissipation is directly related to the required gate charge, and operating frequency. The capacitive load power dissipation per driver is:

P C(MOSFET) = V C Q g f

The flat region from 10 nC to 55 nC is caused by the drain?to?gate Miller capacitance, occurring while the MOSFET is in the linear region dissipating substantial amounts of power. The high output current capability of the MC34151 is able to quickly deliver the required gate charge for fast power efficient MOSFET switching. By operating the MC34151 at a higher V CC, additional charge can be provided to bring the gate above 10 V. This will reduce the ‘on’ resistance of the MOSFET at the expense of higher driver dissipation at a given operating frequency.

The transition power dissipation is due to extremely short simultaneous conduction of internal circuit nodes when the Drive Outputs change state. The transition power dissipation per driver is approximately:

P T = V CC (1.08 V CC C L f ? 8 y 10?4)

P T must be greater than zero.

Switching time characterization of the MC34151 is performed with fixed capacitive loads. Figure 14 shows that for small capacitance loads, the switching speed is limited by transistor turn?on/off time and the slew rate of the internal nodes. For large capacitance loads, the switching speed is limited by the maximum output current capability of the integrated circuit.

LAYOUT CONSIDERATIONS

High frequency printed circuit layout techniques are imperative to prevent excessive output ringing and overshoot.Do not attempt to construct the driver circuit on wire?wrap or plug?in prototype boards. When driving large capacitive loads, the printed circuit board must contain a low inductance ground plane to minimize the voltage spikes induced by the high ground ripple currents. All high current loops should be kept as short as possible using heavy copper runs to provide a low impedance high frequency path. For

optimum drive performance, it is recommended that the initial circuit design contains dual power supply bypass capacitors connected with short leads as close to the V CC pin and ground as the layout will permit. Suggested capacitors are a low inductance 0.1 m F ceramic in parallel with a 4.7 m F tantalum. Additional bypass capacitors may be required depending upon Drive Output loading and circuit layout.Proper printed circuit board layout is extremely critical and cannot be over emphasized.

The MC34151 greatly enhances the drive capabilities of common switching regulators and CMOS/TTL logic devices.

Figure 19. Enhanced System Performance with

Common Switching Regulators

Figure 20. MOSFET Parasitic Oscillations

Figure 21. Direct Transformer Drive Figure 22. Isolated MOSFET Drive

MOSFET switching speed. Schottky diode D 1 can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground.

Output Schottky diodes are recommended when driving inductive loads at high frequencies. The diodes reduce the driver’s power dissipation by preventing the output pins from being driven above V CC and below ground.

Figure 23. Controlled MOSFET Drive Figure 24. Bipolar Transistor Drive

Figure 25. Dual Charge Pump Converter

The totem?pole outputs can furnish negative base current for enhanced transistor turn?off, with the addition of capacitor C 1.

The capacitor’s equivalent series resistance limits the Drive Output Current to 1.5 A. An additional series resistor may be required when using tantalum or other low ESR capacitors.

In noise sensitive applications, both conducted and radiated EMI can be reduced significantly by controlling the MOSFET’s turn?on and turn?off times.

V I V = 15 V + V O ≈ 2.0 V CC

? V O ≈ ? V CC

Specifications Brochure, BRD8011/D.

PDIP?8P SUFFIX CASE 626?05ISSUE L

NOTES:

1.DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

2.PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).

3.DIMENSIONING AND TOLERANCING PER ANSI Y1

4.5M, 1982.

DIM MIN MAX MIN MAX INCHES

MILLIMETERS A 9.4010.160.3700.400B 6.10 6.600.2400.260C 3.94 4.450.1550.175D 0.380.510.0150.020F 1.02 1.780.0400.070G 2.54 BSC 0.100 BSC H 0.76 1.270.0300.050J 0.200.300.0080.012K 2.92 3.430.1150.135L 7.62 BSC 0.300 BSC M ???10 ???10 N

0.76 1.01

0.0300.040

SOIC?8D SUFFIX CASE 751?07ISSUE AB

ǒmm inches

ǔSCALE 6:1

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6.751?01 THRU 751?06 ARE OBSOLETE. NEW STANDARD IS 751?0

DIM A MIN MAX MIN MAX INCHES

4.80

5.000.1890.197MILLIMETERS B 3.80 4.000.1500.157C 1.35 1.750.0530.069D 0.330.510.0130.020G 1.27 BSC 0.050 BSC H 0.100.250.0040.010J 0.190.250.0070.010K 0.40 1.270.0160.050M 0 8 0 8 N 0.250.500.0100.020S

5.80

6.20

0.2280.244

0.25 (0.010)

Z S

____*For additional information on our Pb?Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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