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UCC27211

UCC27210

UCC27211

https://www.wendangku.net/doc/5513777697.html, SLUSAT7B–NOVEMBER2011–REVISED FEBRUARY2012 120-V Boot,4-A Peak,High Frequency High-Side/Low-Side Driver

Check for Samples:UCC27210,UCC27211

FEATURES APPLICATIONS

?Drives Two N-Channel MOSFETs in?Power Supplies for Telecom,Datacom,and High-Side/Low-Side Configuration with Merchant

Independent Inputs?Half-Bridge and Full-Bridge Converters ?Maximum Boot Voltage120-V DC?Push-Pull Converters

?4-A Sink,4-A Source Output Currents?High Voltage Synchronous-Buck Converters ?0.9-ΩPull-Up/Pull-Down Resistance?Two-Switch Forward Converters

?Input Pins can Tolerate-10V to20V and are?Active-Clamp Forward Converters Independent of Supply Voltage Range?Class-D Audio Amplifiers

?TTL or Pseudo-CMOS Compatible Input

Versions DESCRIPTION

?8-V to17-V VDD Operating Range,(20V ABS The UCC27210and UCC27211Drivers are based on MAX)the popular UCC27200and UCC27201MOSFET

drivers,but offer several significant performance ?7.2-ns Rise and5.5-ns Fall Time with1000-pF

improvements.Peak output pull-up and pull-down Load

current has been increased to4-A source/4-A sink,?Fast Propagation Delay Times(18ns typical)and pull-up/pull-down resistance have been reduced ?2-ns Delay Matching to0.9Ω,thereby allowing for driving large power

MOSFETs with minimized switching losses during the ?Symmetrical Under Voltage Lockout for

transition through the MOSFET’s Miller Plateau.The High-Side and Low-Side Driver

input structure is now able to directly handle-10?All Industry Standard Packages Available VDC,which increases robustness and also allows (SOIC-8,PowerPAD?SOIC-8,4-mm x4-mm direct interface to gate-drive transformers without SON-8and4-mm x4-mm SON-10)using rectification diodes.The inputs are also

independent of supply voltage and have a20-V ?Specified from-40to140°C

maximum rating.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UCC27210UCC27211

SLUSAT7B –NOVEMBER 2011–REVISED FEBRUARY https://www.wendangku.net/doc/5513777697.html,

These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONT.)

The UCC27210/1’s switching node (HS pin)is able to handle -18V maximum which allows the high-side channel

to be protected from inherent negative voltages caused parasitic inductance and stray capacitance.The

UCC27210(Pseudo-CMOS inputs)and UCC27211(TTL inputs)have increased hysteresis allowing for interface

to analog or digital PWM controllers with enhanced noise immunity.

The low-side and high-side gate drivers are independently controlled and matched to 2ns between the turn on

and turn off of each other.

An on-chip 120-V rated bootstrap diode eliminates the external discrete diodes.Under-voltage lockout is

provided for both the high-side and the low-side drivers providing symmetric turn-on/turn-off behavior and forcing

the outputs low if the drive voltage is below the specified threshold.

Both devices are offered in 8-pin SOIC (D),PowerPAD ?SOIC-8(DDA),4-mm x 4-mm SON-8(DRM)and

SON-10(DPR)packages.

Typical Application Diagrams

ORDERING INFORMATION

(1)PACKAGED DEVICES (1)INPUT TEMPERATURE RANGE T A =T J PowerPAD ?COMPATIBILITY

SOIC-8(D)(2)SON-8(DRM)(3)SON-10(DPR)(4)SOIC-8(DDA)(2)Pseudo CMOS

UCC27210D UCC27210DDA UCC27210DRM UCC27210DPR -40°C to 140°C

TTL UCC27211D UCC27211DDA UCC27211DRM UCC27211DPR (1)

These products are packaged in Lead (Pb)-Free and green lead finish of PdNiAu which is compatible with MSL level 1at 255°C to 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.(2)

D (SOIC-8)and DDA (Power Pad ?SOIC-8)packages are available taped and reeled.Add R suffix to device type (e.g.UCC27210ADR/UCC27211ADR)to order quantities of 2,500devices per reel.(3)

DRM (SON-8)package comes either in a small reel of 250pieces as part number UCC27210ADRMT/UCC27211ADRMT,or larger reels of 3000pieces as part number UCC27210ADRMR/UCC27211ADRMR.(4)DPR (SON-10)package comes either in a small reel of 250pieces as part number UCC27210ADPRT/UCC27211ADPRT,or large reels

of 3000pieces as part number UCC27210ADPRR/UCC27211ADPRR.

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UCC27210

UCC27211 https://www.wendangku.net/doc/5513777697.html, SLUSAT7B–NOVEMBER2011–REVISED FEBRUARY2012 ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range(unless otherwise noted)

MIN MAX UNIT Supply voltage range,V DD(1),V HB-V HS-0.320

Input voltages on LI and HI,V LI,V HI-1020

DC-0.3V DD+0.3

Output voltage on LO,V LO

Repetitive pulse<100ns(2)-2V DD+0.3

DC V HS–0.3V HB+0.3V Output voltage on HO,V HO

Repetitive pulse<100ns(2)V HS-2V HB+0.3

DC-1115

Voltage on HS,V HS

Repetitive pulse<100ns(2)-18115

Voltage on HB,V HB-0.3120

Human Body Model(HBM)2

ESD kV

Field Induced Charged Device Model

(FICDM)

Operating virtual junction temperature range,T J-40150

Storage temperature,T STG-65150°C

Lead temperature(soldering,10sec.)300

(1)All voltages are with respect to VSS unless otherwise noted.Currents are positive into,negative out of the specified terminal.

(2)Verified at bench characterization.

RECOMMENDED OPERATING CONDITIONS

all voltages are with respect to V SS;currents are positive into and negative out of the specified terminal.–40°C

PARAMETER MIN TYP MAX UNIT Supply voltage range,V DD,V HB-V HS81217

Voltage on HS,V HS-1105

V Voltage on HS,V HS(repetitive pulse<100ns)-15110

V HS+8,V HS+17,

Voltage on HB,V HB

V DD–1115

Voltage slew rate on HS50V/ns Operating junction temperature range-40140°C

UCC27210

UCC27211

SLUSAT7B–NOVEMBER2011–REVISED https://www.wendangku.net/doc/5513777697.html, THERMAL INFORMATION

UCC27210/11(1)

THERMAL METRIC D DDA UNITS

8PINS8PINS

θJA Junction-to-ambient thermal resistance(2)111.837.7

θJCtop Junction-to-case(top)thermal resistance(3)56.947.2

θJB Junction-to-board thermal resistance(4)53.09.6

°C/W

ψJT Junction-to-top characterization parameter(5)7.8 2.8

ψJB Junction-to-board characterization parameter(6)52.39.4

θJCbot Junction-to-case(bottom)thermal resistance(7)n/a 3.6

(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.

(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as

specified in JESD51-7,in an environment described in JESD51-2a.

(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific

JEDEC-standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature,as described in JESD51-8.

(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(7)The junction-to-case(bottom)thermal resistance is obtained by simulating a cold plate test on the exposed(power)pad.No specific

JEDEC standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

THERMAL INFORMATION

UCC27210/11(1)

THERMAL METRIC DRM DPR UNITS

8PINS10PINS

θJA Junction-to-ambient thermal resistance(2)33.936.8

θJCtop Junction-to-case(top)thermal resistance(3)33.236.0

θJB Junction-to-board thermal resistance(4)11.414.0

°C/W

ψJT Junction-to-top characterization parameter(5)0.40.3

ψJB Junction-to-board characterization parameter(6)11.714.2

θJCbot Junction-to-case(bottom)thermal resistance(7) 2.3 3.4

(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.

(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as

specified in JESD51-7,in an environment described in JESD51-2a.

(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific

JEDEC-standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature,as described in JESD51-8.

(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(7)The junction-to-case(bottom)thermal resistance is obtained by simulating a cold plate test on the exposed(power)pad.No specific

JEDEC standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

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UCC27210

UCC27211 https://www.wendangku.net/doc/5513777697.html, SLUSAT7B–NOVEMBER2011–REVISED FEBRUARY2012 ELECTRICAL CHARACTERISTICS

V DD=V HB=12V,V HS=V SS=0V,no load on LO or HO,T A=T J=-40°C to140°C,(unless otherwise noted)

PARAMETER TEST CONDITION MIN TYP MAX UNITS Supply Currents

I DD V DD quiescent current V(LI)=V(HI)=0V0.050.0850.17

I DDO UCC27210 2.4 2.6 4.3

V DD operating current f=500kHz,C LOAD=0

UCC27211 2.4 2.5 4.3mA

I HB Boot voltage quiescent current V(LI)=V(HI)=0V0.0150.0650.1

I HBO Boot voltage operating current f=500kHz,C LOAD=0 1.5 2.54

I HBS HB to V SS quiescent current V(HS)=V(HB)=115V0.00050.13μA

I HBSO HB to V SS operating current f=500kHz,C LOAD=00.070.9mA Input

V HIT Input voltage threshold 4.2 5.0 5.8

V LIT Input voltage threshold 2.4 3.2 4.0V

UCC27210

V IHYS Input voltage hysteresis 1.8

R IN Input pulldown resistance102kΩ

V HIT Input voltage threshold 1.9 2.3 2.7

V LIT Input voltage threshold 1.3 1.6 1.9

UCC27211

V IHYS Input voltage hysteresis700mV

R IN Input pulldown resistance68kΩUnder-Voltage Lockout(UVLO)

V DDR V DD turn-on threshold 6.27.07.8

V DDHYS Hysteresis0.5

V HBR V HB turn-on threshold 5.6 6.77.9

V HBHYS Hysteresis 1.1

Bootstrap Diode

V F Low-current forward voltage I VDD-HB=100μA0.650.8

V FI High-current forward voltage I VDD-HB=100mA0.850.95

R D Dynamic resistance,ΔVF/ΔI I VDD-HB=100mA and80mA0.30.50.85Ω

LO Gate Driver

V LOL Low-level output voltage I LO=100mA0.050.090.15

V LOH High level output voltage I LO=-100mA,V LOH=V DD-V LO0.10.160.27

Peak pull-up current(1)V LO=0V 3.7

A Peak pull-down current(1)V LO=12V 4.5

HO GATE Driver

V HOL Low-level output voltage I HO=100mA0.050.090.15

V HOH High-level output voltage I HO=-100mA,V HOH=V HB-V HO0.10.160.27

Peak pull-up current(1)V HO=0V 3.7

A Peak pull-down current(1)V HO=12V 4.5

(1)Ensured by design.

UCC27210

UCC27211

SLUSAT7B–NOVEMBER2011–REVISED https://www.wendangku.net/doc/5513777697.html, ELECTRICAL CHARACTERISTICS(continued)

V DD=V HB=12V,V HS=V SS=0V,no load on LO or HO,T A=T J=-40°C to140°C,(unless otherwise noted)

PARAMETER TEST CONDITION MIN TYP MAX UNITS

Switching Parameters:Propagation Delays

T DLFF V LI falling to V LO falling172137

T DHFF V HI falling to V HO falling172137

UCC27210,C LOAD=0

T DLRR V LI rising to V LO rising182446

T DHRR V HI rising to V HO rising182446

T DLFF V LI falling to V LO falling101730

T DHFF V HI falling to V HO falling101730

UCC27211,C LOAD=0

T DLRR V LI rising to V LO rising101840

T DHRR V HI rising to V HO rising101840

Switching Parameters:Delay Matching

T J=25°C311

T MON From HO OFF to LO ON ns

T J=–40°C to140°C314

UCC27210

T J=25°C311

T MOFF From LO OFF to HO ON ns

T J=–40°C to140°C314

T J=25°C29.5

T MON From HO OFF to LO ON ns

T J=–40°C to140°C214

UCC27211

T J=25°C29.5

T MOFF From LO OFF to HO ON ns

T J=–40°C to140°C214

Switching Parameters:Output Rise and Fall Time

t R LO rise time7.2

C LOAD=1000pF,from10%to90%

t R HO rise time7.2

t F LO fall time 5.5

C LOAD=1000pF,from90%to10%

t F HO fall time 5.5

t R LO,HO C LOAD=0.1μF,(3V to9V)0.360.6

μs

t F LO,HO C LOAD=0.1μF,(9V to3V)0.150.4

Switching Parameters:Miscellaneous

Minimum input pulse width that changes the

50 output ns

Bootstrap diode turn-off time(2)(3)I F=20mA,I REV=0.5A(4)20

(2)Ensured by design.

(3)I F:Forward current applied to bootstrap diode,I REV:Reverse current applied to bootstrap diode.

(4)Typical values for T A=25°C.

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Input (HI,LI)

Output (HO,

MON MOFF

UCC27210

UCC27211

https://www.wendangku.net/doc/5513777697.html, SLUSAT7B–NOVEMBER2011–REVISED FEBRUARY2012

Timing Diagrams

LI V DD

HB HO HS LO

V SS VDD HB HO HS NC LO VSS

NC 10912345876

SON-10 (DPR)TOP

VIEW

VDD HB HO HS VSS

Power Pad TM SOIC-8(DDA)TOP VIEW

LO LI

VDD HB HO HS LO VSS LI HI SOIC-8(D)

TOP VIEW VDD HB HO HS VSS SON-8(DRM)

TOP VIEW

LO LI HI UCC27210UCC27211

SLUSAT7B –NOVEMBER 2011–REVISED FEBRUARY https://www.wendangku.net/doc/5513777697.html,

DEVICE INFORMATION

Functional Block Diagram

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UCC27210

UCC27211 https://www.wendangku.net/doc/5513777697.html, SLUSAT7B–NOVEMBER2011–REVISED FEBRUARY2012

TERMINAL FUNCTIONS

PIN NAME DESCRIPTION

D/DDA/DRM DPR

Positive supply to the lower-gate driver.De-couple this pin to V SS(GND).Typical VDD11

decoupling capacitor range is0.22μF to1.0μF.

High-side bootstrap supply.The bootstrap diode is on-chip but the external bootstrap

capacitor is required.Connect positive side of the bootstrap capacitor to this pin.

HB22Typical range of HB bypass capacitor is0.022μF to0.1μF.The capacitor value is

dependant on the gate charge of the high-side MOSFET and should also be selected

based on speed and ripple criteria

HO33High-side output.Connect to the gate of the high-side power MOSFET.

High-side source connection.Connect to source of high-side power MOSFET.

HS44

Connect the negative side of bootstrap capacitor to this pin.

HI57High-side input.

LI68Low-side input.

VSS79Negative supply terminal for the device which is generally grounded.

LO810Low-side output.Connect to the gate of the low-side power MOSFET.

N/C-5/6Not Connected.

Utilized on the DDA,DRM and DPR packages only.Electrically referenced to V SS PowerPAD?(1)Pad Pad(GND).Connect to a large thermal mass trace or GND plane to dramatically improve

thermal performance.

(1)The PowerPAD?is not directly connected to any leads of the package.However it is electrically and thermally connected to the

substrate which is the ground of the device.

020*********

V DD = V HB ? Supply Voltage (V)I D D , I H B ? Q u i e s c e n t C u r r e n t (μA )G001 0.01

0.1110100

Frequency (kHz)I D D O ? O p e r a t i n g C u r r e n t (m A )G002 0.010.1110

100Frequency (kHz)I D D O ? O p e r a t i n g C u r r e n t (m A )G003 0.01

0.1110100

Frequency (kHz)I H B O ? O p e r a t i n g C u r r e n t (m A )

G004 ?10

123456

V DD ? Supply Voltage (V)H I , L I ? I n p u t T h r e s h o l d V o l t a g e (V )G005 ?10123

456Temperature (°C)H I , L I ? I n p u t T h r e s h o l d V o l t a g e (V )G006 UCC27210UCC27211

SLUSAT7B –NOVEMBER 2011–REVISED FEBRUARY https://www.wendangku.net/doc/5513777697.html,

TYPICAL CHARACTERISTICS

QUIESCENT CURRENT

UCC27210IDD OPERATING CURRENT vs

vs SUPPLY VOLTAGE

FREQUENCY Figure 1.

Figure 2.UCC27211IDD OPERATING CURRENT

BOOT VOLTAGE OPERATING CURRENT vs

vs FREQUENCY

FREQUENCY (HB to HS)Figure 3.

Figure 4.UCC27210/11INPUT THRESHOLD

UCC27210/11INPUT THRESHOLDS vs

vs SUPPLY VOLTAGE

TEMPERATURE Figure 5.Figure 6.

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00.04

0.08

0.120.160.20.240.280.32

Temperature (°C)V O H ? L O /H O O u t p u t V o l t a g e (V )G007 00.040.080.120.160.2

Temperature (°C)V O L ? L O /H O O u t p u t V o l t a g e (V )

G008 5.25.6

6.4

6.8

7.2

7.6

Temperature (°C)T h r

e s h o l d (V )G009 00.30.60.91.21.5Temperature (°C)H y s t e r e s i s (V )

G010

162024283236

Temperature (°C)P r o p a g a t i o n D e l a y (n s )

G011 08162432Temperature (°C)P r o p a g a t i o n D e l a y (n s )G012 UCC27210UCC27211

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TYPICAL CHARACTERISTICS (continued)

LO AND HO HIGH LEVEL OUTPUT VOLTAGE

LO AND HO LOW LEVEL OUTPUT VOLTAGE vs

vs TEMPERATURE

TEMPERATURE Figure 7.

Figure 8.UNDERVOLTAGE LOCKOUT THRESHOLD

UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS vs

vs TEMPERATURE

TEMPERATURE Figure 9.

Figure 10.UCC27210PROPAGATION DELAYS

UCC27211PROPAGATION DELAYS vs

vs TEMPERATURE

TEMPERATURE Figure 11.Figure 12.

1216202428

V DD =V HB ? Supply Voltage (V)P r o p a g a t i o n D e l a y (n s )G012 0481216202428

32V DD =V HB ? Supply Voltage (V)P r o p a g a t i o n D e l a y (n s )G014 ?20

246810

Temperature (°C)D e l a y M a t c h i n g (n s )G015 0

12345

V LO , V HO ? Output Voltage (V)I L O , I H O ? O u t p u t C u r r e n t (A )G016 UCC27210UCC27211

SLUSAT7B –NOVEMBER 2011–REVISED FEBRUARY https://www.wendangku.net/doc/5513777697.html,

TYPICAL CHARACTERISTICS (continued)

UCC27210PROPAGATION DELAYS

UCC27211PROPAGATION DELAYS vs

vs SUPPLY VOLTAGE

SUPPLY VOLTAGE Figure 13.

Figure 14.DELAY MATCHING

OUTPUT CURRENT vs

vs TEMPERATURE

OUTPUT VOLTAGE Figure 15.Figure 16.

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0.0010.01

0.1

110

100500

550

600

650700750800850Diode Voltage (mV)D i o d e C u r r e n t (m A )G017

UCC27210UCC27211

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TYPICAL CHARACTERISTICS (continued)

DIODE CURRENT

DIODE VOLTAGE

NEGATIVE 10-V INPUT

Figure 17.

Figure 18.STEP INPUT SYMMETRICAL UVLO

Figure 19.Figure 20.

UCC27210

UCC27211

SLUSAT7B–NOVEMBER2011–REVISED https://www.wendangku.net/doc/5513777697.html,

APPLICATION INFORMATION

Functional Description

The UCC27210/11represent Texas Instruments’latest generation of high voltage gate drivers which are designed to drive both the high-side and low-side of N-Channel MOSFETs in a half-/full-bridge or synchronous buck configuration.The floating high-side driver is capable of operating with supply voltages of up to120V.This allows for N-Channel MOSFET control in half-bridge,full-bridge,push pull,two-switch forward and active clamp forward converters.

The UCC27210/11feature4-A source/sink capability,industry best-in-class switching characteristics and a host of other features listed in the table below.These features combine to ensure efficient,robust and reliable operation in high-frequency switching power circuits.

Table1.UCC27210/11Highlights

FEATURE BENEFIT

High peak current ideal for driving large power MOSFETs with

4-A source and sink current with0.9-Ωoutput resistance

minimal power loss(fast-drive capability at Miller plateau)

Increased robustness and ability to handle under/overshoot.Can Input pins(HI and LI)can directly handle-10VDC up to20VDC interface directly to gate-drive transformers without having to use

rectification diodes

120-V internal boot diode Provides voltage margin to meet telecom100-V surge requirements

Allows the high-side channel to have extra protection from inherent Switch node(HS pin)able to handle-18V maximum for100ns negative voltages caused parasitic inductance and stray

capacitance.

Robust ESD circuitry to handle voltage spikes Excellent immunity to large dV/dT conditions

Best-in-class switching characteristics and extremely low-pulse

18-ns propagation delay with7.2-ns/5.5-ns rise/fall Times

transmission distortion

2-ns(typ)delay matching between channels Avoids transformer volt-second offset in bridge

Symmetrical UVLO circuit Ensures high-side and low-side shut down at the same time

CMOS optimized threshold or TTL optimized thresholds with Complementary to analog or digital PWM controllers.Increased increased hysteresis hysteresis offers added noise immunity

In UCC27210/11,the high side and low side each have independent inputs which allow maximum flexibility of input control signals in the application.The boot diode for the high-side driver bias supply is internal to the UCC27210and UCC27211.The UCC27210is the Pseudo-CMOS compatible input version and the UCC27211 is the TTL or logic compatible version.The high-side driver is referenced to the switch node(HS)which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET.The low-side driver is referenced to V SS which is typically ground.The functions contained are the input stages,UVLO protection,level shift,boot diode,and output driver stages.

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UCC27210

UCC27211 https://www.wendangku.net/doc/5513777697.html, SLUSAT7B–NOVEMBER2011–REVISED FEBRUARY2012 Input Stages

The input stages provide the interface to the PWM output signals.The input impedance of the UCC27210is100 kΩnominal and input capacitance is approximately2pF.The100kΩis a pull-down resistance to V SS(ground). The UCC27210Pseudo-CMOS input structure has been designed to provide large hysteresis and at the same time to allows interfacing to a multitude of analog or digital PWM controllers.In some CMOS designs,the input thresholds are determined as a percentage of VDD.By doing so,the high-level input threshold can become unreasonably high and unusable.The UCC27210recognizes the fact that VDD levels are trending downward and it therefore provides a rising threshold with5.0V(typ)and falling threshold with3.2V(typ).The input hysteresis of the UCC27210is1.8V(typ).

The input stages of the UCC27211have impedance of70kΩnominal and input capacitance is approximately2 pF.Pull-down resistance to V SS(ground)is70kΩ.The logic level compatible input provides a rising threshold of 2.3V and a falling threshold of1.6V.

Under Voltage Lockout(UVLO)

The bias supplies for the high-side and low-side drivers have UVLO protection.V DD as well as V HB to V HS differential voltages are monitored.The V DD UVLO disables both drivers when V DD is below the specified threshold.The rising V DD threshold is7.0V with0.5-V hysteresis.The VHB UVLO disables only the high-side driver when the V HB to V HS differential voltage is below the specified threshold.The V HB UVLO rising threshold is 6.7V with1.1-V hysteresis.

Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node(HS).The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver.

Boot Diode

The boot diode necessary to generate the high-side bias is included in the UCC27210/11family of drivers.The diode anode is connected to V DD and cathode connected to V HB.With the V HB capacitor connected to HB and the HS pins,the V HB capacitor charge is refreshed every switching cycle when HS transitions to ground.The boot diode provides fast recovery times,low diode resistance,and voltage rating margin to allow for efficient and reliable operation.

Output Stages

The output stages are the interface to the power MOSFETs in the power train.High slew rate,low resistance and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs.The low-side output stage is referenced from V DD to V SS and the high side is referenced from V HB to V HS.

UCC27210

UCC27211

SLUSAT7B–NOVEMBER2011–REVISED https://www.wendangku.net/doc/5513777697.html, Layout Recommendations

To improve the switching characteristics and efficiency of a design,the following layout rules should be followed.?Locate the driver as close as possible to the MOSFETs.

?Locate the V DD and V HB(bootstrap)capacitors as close as possible to the driver.

?Pay close attention to the GND https://www.wendangku.net/doc/5513777697.html,e the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin(GND).The GND trace from the driver goes directly to the source of the MOSFET but should not be in the high current path of the MOSFET(S)drain or source current.

?Use similar rules for the HS node as for GND for the high-side driver.

?Use wide traces for LO and HO closely following the associated GND or HS traces.60to100-mils width is preferable where possible.

?Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another.

For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic inductance.

?Avoid LI and HI(driver input)going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads.

Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system.

Example

Additional References

These references and links to additional information may be found at https://www.wendangku.net/doc/5513777697.html,

?Additional layout guidelines for PCB land patterns may be found in,QFN/SON PCB Attachment,Application Brief(Texas Instrument's Literature Number SLUA271)

?Additional thermal performance guidelines may be found in,PowerPAD?Thermally Enhanced Package Application Report,Application Report(Texas Instrument's Literature Number SLMA002A)

?Additional thermal performance guidelines may be found in,PowerPAD?Made Easy,Application Report (Texas Instrument's Literature Number SLMA004)

16Submit Documentation Feedback Copyright?2011–2012,Texas Instruments Incorporated

UCC27210

UCC27211 https://www.wendangku.net/doc/5513777697.html, SLUSAT7B–NOVEMBER2011–REVISED FEBRUARY2012

REVISION HISTORY

Changes from Revision A(November,2011)to Revision B Page ?Changed ordering information notes to reflect corrected part number (2)

PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package

Drawing Pins Package Qty Eco Plan (2)Lead/

Ball Finish

MSL Peak Temp (3)Samples

(Requires Login)

UCC27210D ACTIVE SOIC D875Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC27210DDA PREVIEW SO PowerPAD DDA875Green (RoHS

& no Sb/Br)

CU NIPDAUAGLevel-1-260C-UNLIM

UCC27210DDAR PREVIEW SO PowerPAD DDA82500Green (RoHS

& no Sb/Br)

CU NIPDAUAGLevel-1-260C-UNLIM

UCC27210DPRR ACTIVE WSON DPR103000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

UCC27210DPRT ACTIVE WSON DPR10250Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

UCC27210DR ACTIVE SOIC D82500Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC27210DRMR ACTIVE VSON DRM83000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC27210DRMT ACTIVE VSON DRM8250Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC27211D ACTIVE SOIC D875Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC27211DDA PREVIEW SO PowerPAD DDA875Green (RoHS

& no Sb/Br)

CU NIPDAUAGLevel-1-260C-UNLIM

UCC27211DDAR PREVIEW SO PowerPAD DDA82500Green (RoHS

& no Sb/Br)

CU NIPDAUAGLevel-1-260C-UNLIM

UCC27211DPRR ACTIVE WSON DPR103000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

UCC27211DPRT ACTIVE WSON DPR10250Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

UCC27211DR ACTIVE SOIC D82500Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC27211DRMR ACTIVE VSON DRM83000Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC27211DRMT ACTIVE VSON DRM8250Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows:

Addendum-Page 1

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check https://www.wendangku.net/doc/5513777697.html,/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Type Package Drawing

Pins

SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant UCC27210DPRR WSON

DPR 103000330.012.4 4.25 4.25 1.158.012.0Q2UCC27210DPRT WSON

DPR 10250180.012.4 4.25 4.25 1.158.012.0Q2UCC27210DR SOIC

D 82500330.012.4 6.4 5.2 2.18.012.0Q1UCC27210DRMR VSON

DRM 83000330.012.4 4.25 4.25 1.158.012.0Q2UCC27211DPRR WSON

DPR 103000330.012.4 4.25 4.25 1.158.012.0Q2UCC27211DPRT WSON

DPR 10250180.012.4 4.25 4.25 1.158.012.0Q2UCC27211DR SOIC

D 82500330.012.4 6.4 5.2 2.18.012.0Q1UCC27211DRMR VSON

DRM 83000330.012.4 4.25 4.25 1.158.012.0Q2UCC27211DRMT VSON DRM 8250

180.012.4 4.25 4.25 1.158.012.0Q2

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浙教版八年级上册 4.7 电路分析与应用同步练习(含答案)

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确定版的50个典型经典应用电路实例分析

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4.7电路分析与应用

的计算公式国1 5、图2伏安法测电阻的实验电路图，要求：（1）在图中填上电表的符号。（2）在图中标出电表的正、负接线柱。（3）如要使电流表的读数变小，滑动变阻器的滑片P应向图中__________ 端滑动。

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aZTb 10、如图6所示。R=10欧姆，R2=2O欧姆，R=30欧姆，电源电压恒定不变。 S1闭合，S2断开时安培表的读数为0.3安培。问： (1)电源的电压是多少？ (2)当S1与S2均断开时，电流表的读数是多少？R1两端的电压是多少？ (3)当S1与S2均闭合时，安培表的读数又是多少？通过R3的电流强度是多少？ 11、有一个电池组、一个开关，一个已知电阻R0和导线若干：(1)只有一个电流表；(2)只有一只电压表。设计一个测未知电阻Rx的值的电路，并列出Rx的测量表达式。

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串联电路 1.如右图所示，电源电压为6V，，R1=20Ω，R2=40Ω，S闭合后电压表的示数是（） A．4VB．6VC．3VD．2V 2.一个滑动变阻器标有“50Ω1.5A”的字样，当它与一个阻值为30Ω的电阻串联接入电路时，整个电路总电阻的变化范围为_________。 3.已知R1

集成运算放大器电路分析及应用(完整电子教案)

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图3.3 集成运算放大电路的结构组成集成运放的图形和文字符号如图3.4 所示。图3.4 集成运放的图形和文字符号其中“ -”称为反相输入端，即当信号在该端进入时，输出相位与输入相位相反；而 “+”称为同相输入端，输出相位与输入信号相位相同。 2. 集成运放的基本技术指标集成运放的基本技术指标如下。 ⑴输入失调电压U OS 实际的集成运放难以做到差动输入级完全对称，当输入电压为零时，输出电压并不为零。规定在室温(25℃ )及标准电源电压下，为了使输出电压为零，需在集成运放的两输入端额外附加补偿电压，称之为输入失调电压U OS，U OS 越小越好，一般约为0.5～5mV 。 ⑵开环差模电压放大倍数A od 集成运放在开环时(无外加反馈时)，输出电压与输入差模信号的电压之比称为开环差模电压放大倍数A od。它是决定运放运算精度的重要因素，常用分贝(dB) 表示，目前最高值可达140dB(即开环电压放大倍数达107)。 ⑶共模抑制比K CMRR K CMRR 是差模电压放大倍数与共模电压放大倍数之比，即K CMRR = A A od，其含义与差动放大器中所定义的K CMRR 相同，高质量的运放K CMRR 可达160dB 。 ⑷差模输入电阻r id r id 是集成运放在开环时输入电压变化量与由它引起的输入电流的变化量之比，即从输入端看进去的动态电阻，一般为M Ω数量级，以场效应晶体管为输入级的r id 可达104M Ω。分析集成运放应用电路时，把集成运放看成理想运算放大器可以使分析简化。实际集成运放绝大部分接近理想运放。对于理想运放，A od、K CMRR 、r id 均趋于无穷大。 ⑸开环输出电阻r o r o 是集成运放开环时从输出端向里看进去的等效电阻。其值越小，说明运放的带负载能力越强。理想集成运放r o趋于零。其他参数包括输入失调电流I OS、输入偏置电流I B、输入失调电压温漂d UOS/d T 和输入失调电流温漂d IOS/ d T、最大共模输入电压U Icmax、最大差模输入电压U Idmax 等，可通过器件

电路动态分析的几个结论及应用

电路动态分析的几个结论及应用门宁利（陕西省长安区第三中学陕西西安710100）摘要：电路动态分析有几个很实用的二级结论，很多老师在教学实践中经常使用，这里，利用数学知识予以证明，兼论及其应用。关键词：电路动态分析二级结论证明应用在直流电路问题中，对电路作动态分析是一类典型的问题。在这里，有几个二级结论，书上虽没有，但却很有用。本文就这几个结论的导出及应用做一讨论。一、在闭合电路中，只要部分电阻增大，则总电阻必增大；反之，则减小。即R 部分↑?→?R 总↑ ；R 部分↓?→?R 总↓ 。设有两电阻R 1、R 2，其中R 1保持不变，R 2逐渐增大。（1）当它们串联时：R 2↑??????→?+=21串R R R R 串↑ （2）当它们并联时：R 2↑??? ????→?+=)1/(R R 211R R 并 R 并↑ 而不管怎样复杂的电路，总可等效成串联或并联电路，所以结论普遍成立。例1、如图（1）所示，求R AB 的取值范围。分析：据“R 部分↑?→?R 总↑ 知，当R 3=30Ω时，R AB 有最大值，当 R 3=0时，R AB 有最小值。

解：当R 3=0时，有R ABmin =R 1=10Ω时当R 3=30Ω时，有R ABmin =R 1+323 2R R R R +=22Ω ∴10Ω≤R AB ≤22Ω 二、“并同串反”规律——所谓“并同”，即某一电阻增大（或减小）时，与它关联或间接并联的电阻中的电流、两端电压、电功率都将增大（或减小）；所谓“串反”，即某一电阻增大（或减小）时，与它串联或间接串联的电阻中的电流、两端电压、电功率都将减小（或增大）。使用条件： 1、适用于只有一个支路的电阻发生变化的情况。若几条支路的电阻同时发生变化（如本文的例6、例7），则不适用。 2、当整个电路可等效为一个并联电路时，若电源内阻不计（如例2中的R L1=0，r=0时），则不适用。下面用例2将该结论导出。例2、如图（2）所示，当滑动变阻器的滑片P 向左移动时，L 1、L 2的亮度变化情况是L 1 ，L 2 。分析： P 左移?→?P ↑?→?P 总↑?????→?=R I /ε干 I 干（变亮）图（1）图（2）

555电路的应用与分析

基于EWB的电路设计与仿真 ―－555集成器电路部分前言在当今电子设计领域，EDA设计和仿真是一个十分重要的设计环节。在众多的EDA设计和仿真软件中，EWB软件以其强大的仿真设计应用功能，在各高校电信类专业电子电路的仿真和设计中得到了较广泛的应用。EWB软件及其相关库包的应用对提高学生的仿真设计能力，更新设计理念有较大的好处。 EWB（电子工作平台）软件，最突出的特点是用户界面友好，各类器件和集成芯片丰富，尤其是其直观的虚拟仪表是EWB软件的一大特色。它采用直观的图形界面创建电路：在计算机屏幕上模仿真实验室的工作台，绘制电路图需要的元器件、电路仿真需要的测试仪器均可直接从屏幕上选取。EWB软件所包含的虚拟仪表有：示波器，万用表，函数发生器，波特图图示仪，失真度分析仪，频谱分析仪，逻辑分析仪，网络分析仪等。这些仪器的使用使仿真分析的操作更符合平时实验的习惯。本次毕业设计主要是利用EWB软件对555集成电路的原理及其基本应用电路进行设计和仿真，并通过实验箱进行硬件调试实现。

1EWB软件的简介 1.1 EWB软件的概述随着电子技术和计算机技术的发展，电子产品已与计算机紧密相连，电子产品的智能化日益完善，电路的集成度越来越高，而产品的更新周期却越来越短。电子设计自动化（EDA）技术，使得电子线路的设计人员能在计算机上完成电路的功能设计、逻辑设计、性能分析、时序测试直至印刷电路板的自动设计。EDA是在计算机辅助设计（CAD）技术的基础上发展起来的计算机设计软件系统。与早期的CAD软件相比，EDA软件的自动化程度更高、功能更完善、运行速度更快，而且操作界面友善，有良好的数据开放性和互换性。电子工作平台Electronics Workbench (EWB)(现称为MultiSim) 软件是加拿大Interactive Image Technologies公司于八十年代末、九十年代初推出的电子电路仿真的虚拟电子工作台软件，它具有这样一些特点：（1）软件仪器的控制面板外形和操作方式都与实物相似，可以实时显示测量结果。（2）EWB软件带有丰富的电路元件库，提供多种电路分析方法。（3）作为设计工具，它可以同其它流行的电路分析、设计和制板软件交换数据。（4）EWB还是一个优秀的电子技术训练工具，利用它提供的虚拟仪器可以用比实验室中更灵活的方式进行电路实验，仿真电路的

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