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MAX4692ETE+T中文资料

MAX4692ETE+T中文资料
MAX4692ETE+T中文资料

General Description

The MAX4691–MAX4694 are low-voltage CMOS analog ICs configured as an 8-channel multiplexer (MAX4691),two 4-channel multiplexers (MAX4692), three single-pole/double-throw (SPDT) switches (MAX4693), and four SPDT switches (MAX4694).

The MAX4691/MAX4692/MAX4693 operate from either a single +2V to +11V power supply or dual ±2V to ±5.5V power supplies. When operating from ±5V sup-plies they offer 25Ωon-resistance (R ON ), 3.5Ω(max)R ON flatness, and 3Ω(max) matching between chan-nels. The MAX4694 operates from a single +2V to +11V supply. Each switch has rail-to-rail signal handling and a low 1nA leakage current.

All digital inputs are 1.8V logic-compatible when oper-ating from a +3V supply and TTL compatible when operating from a +5V supply.

The MAX4691–MAX4694 are available in 16-pin, 4mm ?4mm QFN and 16-bump UCSP packages. The chip-scale package (UCSP?) occupies a 2mm x 2mm area, significantly reducing the required PC board area.

Applications

Audio and Video Signal Routing Cellular Phones

Battery-Operated Equipment Communications Circuits Modems

Features

?16 bump, 0.5mm-Pitch UCSP (2mm x 2mm)

?1.8V Logic Compatibility

?Guaranteed On-Resistance

70Ω(max) with +2.7V Supply 35Ω(max) with +5V Supply

25Ω(max) with ±4.5V Dual Supplies ?Guaranteed Match Between Channels

5Ω(max) with +2.7V Supply

3Ω(max) with ±4.5V Dual Supplies ?Guaranteed Flatness Over Signal Range

3.5Ω(max) with ±

4.5V Dual Supplies ?Low Leakage Currents Over Temperature

20nA (max) at +85°C ?Fast 90ns Transition Time ?Guaranteed Break-Before-Make

?Single-Supply Operation from +2V to +11V ?Dual-Supply Operation from ±2V to ±5.5V (MAX4691/MAX4692/MAX4693)?V+ to V- Signal Handling ?Low Crosstalk: -90dB (100kHz)?High Off-Isolation: -88dB (100kHz)

MAX4691–MAX4694

Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/

Quad SPDT in UCSP Package

________________________________________________________________Maxim Integrated Products 1

Functional Diagrams

19-1945; Rev 3; 12/06

Functional Diagrams continued at end of data sheet.UCSP is a trademark of Maxim Integrated Products, Inc.

PART

TEMP RANGE

PIN-

PACKAGE

PKG CODE

MAX4691EBE-T -40°C to +85°C 16-Bu mp UCSP*B16-1 MAX4691EGE -40°C to +85°C 16 QFN-EP ?G1644-1 MAX4692EBE-T -40°C to +85°C 16-Bu mp UCSP*B16-1 MAX4692EGE -40°C to +85°C 16 QFN-EP ?G1644-1 MAX4693EBE-T -40°C to +85°C 16-Bu mp UCSP*B16-1 MAX4693EGE -40°C to +85°C 16 QFN-EP ?G1644-1 MAX4694EBE-T -40°C to +85°C 16-Bu mp UCSP*B16-1 MAX4694EGE -40°C to +85°C 16 QFN-EP ?G1644-1

Ordering Information

*Requires special solder temperature profile described in the Absolute Maximum Ratings section.

*UCSP reliability is integrally linked to the user’s assembly meth-ods, circuit board, and environment. See the UCSP Reliability Notice in the UCSP Reliability section for information.?EP = Exposed pad.

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.wendangku.net/doc/5e16034124.html,.

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 2_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—Single +3V Supply

(V+ = +2.7V to +3.6V, V- = 0, V IH = +1.4V, V IL = +0.4V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V+ to GND..............................................................-0.3V to +12V V+ to V- (MAX4691/MAX4692/MAX4693)..............-0.3V to +12V Voltage into any Terminal (Note 1)......(V- - 0.3V) to (V+ + 0.3V)Continuous Current into any Terminal.............................±20mA Peak Current W_, X_, Y_, Z_ (pulsed at 1ms,

10% duty cycle)...........................................................±40mA ESD per Method 3015.7.......................................................>2kV Continuous Power Dissipation (T A = +70°C)

16-Bump UCSP (derate 8.3mW/°C above +70°C)....659mW 16-Pin QFN (derate 18.5mW/°C above +70°C).......1481mW

Operating Temperature Range ..........................-40°C to +85°C Storage Temperature Range............................-65°C to +150°C Lead Temperature (Soldering)

16-Bump UCSP (Note 2) Infrared (15s).....................+220°C Vapor Phase (60s).....................................................+215°C 16-Pin QFN.................................................................+300°C

Note 1:Voltages exceeding V+ or V- on any signal terminal are clamped by internal diodes. Limit forward-diode current to maxi-mum current rating.

Note 2:This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device

can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recom-mended in the industry standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow.Preheating is required. Hand or wave soldering is not allowed.

MAX4691–MAX4694

Quad SPDT in UCSP Package

_______________________________________________________________________________________3

ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)

(V+ = +2.7V to +3.6V, V- = 0, V IH = +1.4V, V IL = +0.4V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at T A = +25°C.) (Notes 3, 4, 5)

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 4_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(V+ = +4.5V to +5.5V, V- = 0, V IH = +2V, V IL = +0.8V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at T A = +25°C.) (Notes 3, 4, 5)

MAX4691–MAX4694

Quad SPDT in UCSP Package

_______________________________________________________________________________________5

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies

(MAX4691/MAX4692/MAX4693 only)

(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, V IH = +2V, V IL = +0.8V, T A = -40°C to +85°C, unless otherwise noted.) (Notes 3, 4, 5)

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(V+ = +4.5V to +5.5V, V- = 0, V IH = +2V, V IL = +0.8V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at T A = +25°C.) (Notes 3, 4, 5)

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 6_______________________________________________________________________________________

Note 4:UCSP parts are 100% tested at T A = +25°C. Limits across the full temperature range are guaranteed by correlation.Note 5:QFN parts are 100% tested at T A = +85°C. Limits across the full temperature range are guaranteed by correlation.Note 6:UCSP R ON and R ON match are guaranteed by design.Note 7:ΔR ON = R ON(MAX)- R ON(MIN).

Note 8:Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the

specified analog signal ranges.

Note 9:Leakage parameters are guaranteed by design.

Note 10:Off-isolation = 20log 10(V W,X,Y,Z / V W_,X_,Y_,Z_), V W,X,Y,Z = output, V W_,X_,Y_,Z_= input to off switch.Note 11:Between any two switches.

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)(MAX4691/MAX4692/MAX4693 only)

MAX4691–MAX4694

Quad SPDT in UCSP Package

_______________________________________________________________________________________7

40

3020

10

0-6

0-4

-2

2

4

6

ON-RESISTANCE vs. V X , V Y , V Z

(DUAL SUPPLIES)

V X , V Y , V Z (V)

R O N (Ω)

6108161412

22201824-5

-1

-3

1

35

ON-RESISTANCE vs. V X , V Y , V Z AND TEMPERATURE (DUAL SUPPLIES)

V X , V Y , V Z (V)R O N (Ω)

30

2010405060708090100

4

2

6

8

10

12

ON-RESISTANCE vs. V W , V X , V Y , V Z

(SINGLE SUPPLY)

V W , V X , V Y , V Z (V)

R O N (Ω)

10

1412161820222426283032340

1

2

3

4

5

ON-RESISTANCE vs. V W , V X , V Y , V Z AND TEMPERATURE (SINGLE SUPPLY)

V W , V X , V Y , V Z (V)

R O N (Ω)

10

20

30

40

50

00.60.90.3 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3

ON-RESISTANCE vs. V W , V X , V Y , V Z AND TEMPERATURE (SINGLE SUPPLY)

V W , V X , V Y , V Z (V)

R O N (Ω)

10

10.1

0.01

0.001

-40

10

-15

35

60

85

SUPPLY CURRENT vs. TEMPERATURE

(DUAL SUPPLIES)

TEMPERATURE (°C)

I +, I - (n A )

10

10.1

0.01

0.001

-40

10

-15

35

60

85

SUPPLY CURRENT vs. TEMPERATURE

(SINGLE SUPPLY)

TEMPERATURE (°C)

I +, I - (n A )

1pA

0.1nA 0.01nA 1nA 0.01μA 0.1μA 1μA 0.01mA 0.1mA 1mA 0.01A 0.1A 1A 0

1

2

3

4

5

I+ vs. LOGIC LEVEL

V A , V B , V C , V ENB (V)

I +

00.40.2

0.80.61.21.01.41.81.62.0

2

4

5

6

3

7

8

9

10

11

LOGIC-LEVEL THRESHOLD vs. V+

M A X 4691 t o c 09

V+ (V)

V A , V B , V C , V E N (V )

Typical Operating Characteristics

(T A = +25°C, unless otherwise noted.)

FREQUENCY RESPONSE vs. ±5V SUPPLIES

FREQUENCY (MHz)

0.001

100

L O S S (d B )

-140

0-100-120-60-80-20-400.010.1110FREQUENCY RESPONSE vs. +3V SUPPLIES

FREQUENCY (MHz)

0.001

100

L O S S (d B )

-140

0-100-120-60-80

-20-40

0.01

0.1

1

10

10

1k

100

10k

100k

TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY

FREQUENCY (Hz)

T H D +N (%)

0.1

0.001

0.01

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 8_______________________________________________________________________________________

Typical Operating Characteristics (continued)

(T A

= +25°C, unless otherwise noted.)

0.0001

0.0010.1

0.01110

-40

10

-15

35

60

85

ON-LEAKAGE CURRENT vs. TEMPERATURE

TEMPERATURE (°C)

O N -L E A K A G E (n A )

0.0001

0.001

0.1

0.01

110-40

10

-15

35

60

85

OFF-LEAKAGE CURRENT vs. TEMPERATURE

TEMPERATURE (°C)

O F F -L E A K A G E (n A )

30

40355045605565-4010-15356085

TURN-ON/TURN-OFF TIME vs. TEMPERATURE (DUAL SUPPLY)

T U R N -O N /T U R N -O F F T I M E (n s )

TEMPERATURE (°C)

3050407060

8090

-40

10

-15

35

60

85TURN-ON/TURN-OFF TIME

vs. TEMPERATURE (SINGLE SUPPLY)

T U R N -O N /T U R N -O F F T I M E (n s )

TEMPERATURE (°C)30

130

80230

180330280380

SUPPLY VOLTAGE V+, V- (V)

T U R N -O N /T U R N -O F F T I M E (n s )

±2

±3±4±5±6

TURN-ON/TURN-OFF TIME vs. SUPPLY VOLTAGE

1.0

0.52.01.53.02.53.5

-5

-1-3

13-4

0-2

245

CHARGE INJECTION vs. V W , V X , V Y , V Z

V W , V X , V Y , V Z (V)

Q (p C )

MAX4691–MAX4694

Quad SPDT in UCSP Package

_______________________________________________________________________________________9

Pin Description

MAX4691

MAX4692

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 10______________________________________________________________________________________

MAX4693

Pin Description (continued)

Quad SPDT in UCSP Package

Pin Description (continued) MAX4694

______________________________________________________________________________________11

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 12

______________________________________________________________________________________

Detailed Description

The MAX4691–MAX4694 are low-voltage CMOS analog ICs configured as an 8-channel multiplexer (MAX4691),two 4-channel multiplexers (MAX4692), three SPDT switches (MAX4693), and four SPDT switches (MAX4694). All switches are bidirectional.

The MAX4691/MAX4692/MAX4693 operate from either a single +2V to +11V power supply or dual ±2V to ±5.5V power supplies. When operating from ±5V sup-plies they offer 25Ωon-resistance (R ON ), 3.5Ωmax R ON flatness, and 3Ωmax matching between channels.The MAX4694 operates from a single +2V to +11V sup-ply. Each switch has rail-to-rail signal handling, fast switching times of t ON = 80ns, t OFF = 50ns, and a low 1nA leakage current.

All digital inputs are 1.8V logic-compatible when oper-ating from a +3V supply and TTL-compatible when operating from a +5V supply.

Digital Inputs

The MAX4691 and MAX4692 include address pins that allow control of the multiplexers. For the MAX4691, pins

A, B, C determine which switch is closed. The two 4-1muxes in the MAX4692 are controlled by the same address pins (A and B). (Table 1)

The MAX4693 and MAX4694 offer SPDT switches in triple and quadruple packages. In the MAX4693, each switch has a unique control input. The MAX4694 has two digital control inputs: A (for switches “W” and “Y”)and B (for switches “X” and “Z”). (Table 1)

Applications Information

Power-Supply Considerations

Overview

The MAX4691–MAX4694 construction is typical of most CMOS analog switches. V+ and V-* are used to drive the internal CMOS switches and set the limits of the analog voltage on any switch. Reverse ESD-protection diodes are internally connected between each analog signal pin and both V+ and V-. If any analog signal exceeds V+ or V-, one of these diodes will conduct. *V- is found only on the MAX4691/MAX4692/MAX4693.

X = Don’t care

1. EN is not present on the MAX4694.

2. C is not present on the MAX4692 and MAX4694.

MAX4691–MAX4694

Quad SPDT in UCSP Package

______________________________________________________________________________________13

During normal operation, these (and other) reverse-biased ESD diodes leak, forming the only current drawn from V+ or V-.

Virtually all the analog leakage current comes from the ESD diodes. Although the ESD diodes on a given sig-nal pin are identical, and therefore fairly well balanced,they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins consti-tutes the analog signal path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of either the same or opposite polarity.

V+ and G ND power the internal logic and logic-level translators, and set both the input and output logic lim-its. The logic-level translators convert the logic levels into switched V+ and V- signals to drive the gates of the analog signals. This drive signal is the only connec-tion between the logic supplies (and signals) and the analog supplies. V+ and V- have ESD-protection diodes on GND.

Bipolar Supplies

The MAX4691/MAX4692/MAX4693 operate with bipolar supplies between ±2V and ±5.5V. The V+ and V- sup-plies need not be symmetrical, but their difference can-not exceed the absolute maximum rating of +12V.Single Supply

These devices operate from a single supply between +2V and +11V when V- is connected to GND. All of the bipolar precautions must be observed. At room temperature,they operate with a single supply at near or below +2V,although as supply voltage decreases, switch on-resis-tance and switching times become very high.Always bypass supplies with a 0.1μF capacitor.

Overvoltage Protection

Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maxi-mum ratings, because stresses beyond the listed rat-ings can cause permanent damage to the devices.Always sequence V+ on first, then V-, followed by the logic inputs and by W, X, Y, Z. If power-supply sequencing is not possible, add two small signal diodes (D1, D2) in series with the supply pins for over-voltage protection (Figure 1).

Adding diodes reduces the analog signal range to one diode drop below V+ and one diode drop above V-, but does not affect the devices’ low switch resistance and low leakage characteristics. Device operation is

unchanged, and the difference between V+ and V-should not exceed 12V. These protection diodes are not recommended when using a single supply if signal levels must extend to ground.

UCSP Reliability

The chip-scale package (UCSP) represents a unique package that greatly reduces board space compared to other packages. UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering a UCSP. Performance through Operating Life Test and Moisture Resistance is equal to conventional package technology as it is primarily deter-mined by the wafer-fabrication process. However, this form factor may not perform equally to a packaged prod-uct through traditional mechanical reliability tests.

Mechanical stress performance is a greater considera-tion for a UCSP. UCSP solder joint contact integrity must be considered since the package is attached through direct solder contact to the user’s PC board.Testing done to characterize the UCSP reliability per-formance shows that it is capable of performing reli-ably through environmental stresses. Results of environmental stress tests and additional usage data and recommendations are detailed in the UCSP appli-cation note, which can be found on Maxim’s website, at https://www.wendangku.net/doc/5e16034124.html,.

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 14______________________________________________________________________________________

Figure 2. Enable Transition Time

Test Circuits/Timing Diagrams

MAX4691–MAX4694

Quad SPDT in UCSP Package

______________________________________________________________________________________15

Figure 3. Address Transition Time

Test Circuits/Timing Diagrams (continued)

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 16______________________________________________________________________________________

Figure 4. Break-Before-Make Interval

Figure 5. Charge Injection

Test Circuits/Timing Diagrams (continued)

MAX4691–MAX4694

Quad SPDT in UCSP Package

______________________________________________________________________________________17

Figure 6. Off-Isolation, On-Loss, and Crosstalk

Figure 7. Capacitance

Test Circuits/Timing Diagrams (continued)

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 18______________________________________________________________________________________

Functional Diagrams (continued)

Chip Information

TRANSISTOR COUNT: 292

MAX4691–MAX4694

Quad SPDT in UCSP Package

______________________________________________________________________________________19

Pin Configurations

M A X 4691–M A X 4694

Quad SPDT in UCSP Package 20______________________________________________________________________________________

Pin Configurations (continued)

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