HS1-3374RH-8中文资料

?File Number

3038.2

HS-3374RH

Radiation Hardened 8-Bit Bidirectional CMOS/TTL Level Converter

The Intersil HS-3374RH is a radiation hardened 8-bit bidirectional level converter designed to interface CMOS logic levels with TTL logic levels in radiation hardened bus oriented systems. The HS-3374RH is fabricated using a radiation hardened EPI-CMOS process and features eight parallel bidirectional buffer/level converters.

Two control inputs, ENABLE and DISABLE, are used to determine the direction of data flow, and to set both the in puts and outputs in the high impedance state. The control inputs may be driven by either TTL or CMOS logic drivers capable of sinking one standard TTL load.

The HS-3374RH is a non-inverting version of the industry standard CD40116. The non-inverting outputs of the

HS-3374RH reduce PC board chip count by eliminating the need to restore data back to a non-inverted format.

Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering.Detailed Electrical Specifications for these devices are contained in SMD 5962-96786. A “hot-link” is provided on our homepage for downloading.

https://www.wendangku.net/doc/5a16519372.html,/spacedefense/space.asp

Functional Diagram

Features

?Electrically Screened to SMD # 5962-96786?QML Qualified per MIL-PRF-38535 Requirements ?Radiation Hardened EPI-CMOS

-Total Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 105RAD(Si)-Latch-Up Immune. . . . . . . >1 x 1012RAD(Si)/s (Note 1)?Low Propagation Delay Time

-Typical CMOS to TTL Pre-RAD . . . . . . . . . . . . . . .40ns -Typical CMOS to TTL Post 100KRAD . . . . . . . . . .40ns -Typical TTL to CMOS Pre-RAD . . . . . . . . . . . . . . .50ns -Typical TTL to CMOS Post 100KRAD . . . . . . . . . .50ns ?Low Standby Power

?+10V CMOS and +5V TTL Power Supply Inputs ?Eight Non-Inverting Three-State Input/Output Channels ?No External TTL Input Pull-Up Resistors Required ?High TTL Sink Current ?Equivalent to Sandia SA2996

?Military Temperature Range. . . . . . . . . . . . -55o C to 125o C

NOTE:

1.For operation at 10V and transient levels above

1x 1010RAD(Si)/s, please refer to Application Note 401.

Pinout

HS-3374RH

MIL-STD-1835, CDIP2-T22

(SBDIP)TOP VIEW

Ordering Information

ORDERING NUMBER INTERNAL MKT. NUMBER TEMP. RANGE

(o C)5962R9678601QWC HS1-3374RH-8-55 to 1255962R9678601VWC

HS1-3374RH-Q

-55 to 125

DISABLE 13

CMOS IN/OUT

ENABLE 10

2-9

88

14-21

TTL

OUT (IN)VDD = 1VCC = 22GND = 11

LEVEL SHIFTER

111

10

9

87653242212131415161718192120A0A1

A2

A3A4A5

A7

A6ENABLE GND B0B2B3B4B1B5B6B7DISABLE NC

VDD VCC CMOS

INPUT/OUTPUT

TTL

INPUT/OUTPUT

Data Sheet August 2000

O B S O L E T E P R O D U C T N O R E

C O M M E N

D

E D R

E P L A C E

M E N T c o n t a c

t o u r T e c h n i c a l S u p p o r t C e n t e r a t 1-88

8-I N T E R S

I L o r w w w .i n t e r s i l .c

o m /t s c

Functional Block Diagram

1 OF 8 IDENTICAL CIRCUITS

NOTES:

2.Enable and disable are TTL type inputs

3.D and E outputs are common to all 8 channels

GND

2 (3, 4, 5, 6, 7, 8, 9)

A1 CMOS INPUT (OUTPUT)

VDD

D

E

VCC

VDD

LEVEL SHIFTER

VCC

B1 TTL OUTPUT (INPUT)21 (20, 19,18, 17, 16,15, 14)ENABLE DISABLE

13

10

GND

GND

VDD

VDD

D

E

LEVEL SHIFTER

LEVEL SHIFTER

INPUT (OUTPUT)OUTPUT (INPUT)DATA TERMINAL NUMBER

DATA TERMINAL NUMBER

A02B021A13B120A24B219A35B318A46B417A57B516A68B615A7

9

B7

14

TRUTH TABLE

ENABLE

DISABLE

FUNCTION

X 0Convert CMOS Level to TTL Level 11Convert TTL Level to CMOS Level 0

1

High Impedance (Z)

0 = Low Level 1 = High Level X = Don’t Care Z = High Impedance on Both CMOS and TTL sides.

NOTE:An important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is

eliminated by the presence of regenerative latches on the following HS-3374RH pins: A0 - 7.

The functional block diagram depicts one of these pins with the regenerative latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-state condition. A transient drive current of ±1.5mA at VDD/2 ±0.5V for 10ns is required to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions.

WARNING:Do not activate the Disable input by hardwiring to any TTL input pins. This is an incorrect mode of operation.

Die Characteristics

DIE DIMENSIONS:

89.4 mils x 76.0 mils x 14 mils ±1 mil INTERFACE MATERIALS:Glassivation:

Type: SiO2

Thickness: 11k ? ±2k ?Top Metallization:Type:AlSi

Thickness: 8k ? ±1k ?

Substrate:

Radiation Hardened Silicon Gate,Dielectric Isolation Backside Finish:Silicon

ASSEMBLY RELATED INFORMATION:Substrate Potential:Unbiased (DI)

Metallization Mask Layout

HS-3374RH

(20) B1

A2 (4)

(19) B2

(18) B3

(17) B4

(16) B5

(15) B6

(14) B7

A3 (5)

A4 (6)

A5 (7)

A6 (8)

A7 (9)

(3) A 1

(2) A 0

(1) V D D

(22) V C C

(21) B 0

D I S A B L

E (13)

G N D (11)

E N A B L E (10)