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EDI2GG46464V11D中文资料

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February 1999 Rev. 2ECO# 10858

4x64Kx64, 3.3V Synchronous SRAM CARD EDGE DIMM

FEATURES

s 4x64Kx64 Synchronous

s Access Speed(s): T KHQV = 9.5, 10, 11,12, 15ns s Flow-Through Architecture

s Clock Controlled Registered Bank Enables (E 1\,E 2\, E 3\, E 4\)s Clock Controlled Registered Address

s Clock Controlled Registered Global Write (GW\)s Aysnchronous Output Enable (G\)s Internally self-timed Write+s Gold Lead Finish s 3.3V ±10%, -5% Operation s Common Data I/O

s High Capacitance (30pF) drive, at rated Access Speed s Single total array Clock s Multiple Vcc and Vss

The EDI2GG46464VxxD is a Synchronous SRAM, 60 position Dual Key; Card Edge DIMM (120 contacts) Module, organized as 4x64Kx64. The Module contains eight (8) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Synchronous Only, Flow-Through, Early Write device. This Module provides high performance, ultra fast access times at a cost per bit benefit over BiCMOS Asynchronous devices.As well as improved cost per bit, the use of Synchronous or Synchronous burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement.

Synchronous operations are in relation to an externally supplied clock, registered address, registered global write, registered enables as well as an Asynchronous Output enable. All Read and Write operations are performed in Quad Words (64 bit operations).Write cycles are internally self timed and are initiated by a rising clock edge. This feature relieves the designer the task of developing external pulse width circuitry.

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PIN CONFIGURATION

VSS VSS A0A1A15A2A14A3A13VCC VCC A4A12A5A6A7VSS A8VSS CLK VSS E 4\VCC E 3\G\VSS DQ0DQ1DQ2DQ3VCC DQ8DQ9DQ10DQ16DQ17DQ18DQ19VCC DQ24DQ25DQ26DQ27VSS DQ32DQ33DQ34DQ35VCC DQ40DQ41DQ42DQ43VSS DQ48DQ49DQ50DQ51VCC DQ56DQ57DQ58DQ59VSS

1113151719VSS DQ11A11A10A9VSS RFU VSS NC 16141210VSS E 2\VCC E1\G W\VSS DQ7DQ6DQ5DQ4VCC DQ15

DQ14DQ13DQ12VSS DQ23DQ22DQ21DQ20VCC DQ31DQ30DQ29DQ28VSS DQ39DQ38DQ37DQ36VCC DQ47DQ46DQ45DQ44VSS DQ55DQ54DQ53DQ52VCC DQ63DQ62DQ61DQ60VSS

NC 135798642212325272826242220182931333537394143454749515250484644424038363430325355575961636567697173545658606264666870727475777981838587899193767880828486889092949698100102104106108110112114116959799101103105107109111113115117119118120

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GW\E1\

GW\

E\DQ

64K x 32

GW\G\E\

64K x 32

GW\G\E\

64K x 32

GW\G\E\

DQ 64K x 32

E3\

GW\

G\E\

DQ 64K x 32

GW\G\E\

64K x 32

GW\G\E\

64K x 32

GW\G\E\

64K x 32

E2\

E4\

DQ0-DQ31DQ32-DQ63

CLK

CLK CLK

CLK

CLK CLK

CLK A0-A15FUNCTIONAL BLOCK DIAGRAM

DQ 0-63Input/Output Bus A 0-15

Address Bus E 1\, E 2\,Synchronous Bank

E 3\, E 4\ Enables CLK Array Clock GW\Synchronous Global Write Enable G\

Asynchronous Output Enable

Vcc 3.3V Power Supply

Vss Ground NC

No Connect

PIN NAMES

PIN DESCRIPTIONS

DIMM Pins Symbol Type Description

3, 5, 7, 9, 13, 15,A0-15

Input Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK.17, 19, 23, 20, 18,Synchronous The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.16, 14, 10, 8, 6

38GW\Input Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines Synchronous and must meet the setup and hold times around the rising edge of CLK.

27CLK Input Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising Synchronous edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.36, 32,E1\, E2\Input Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\.35, 31E3\, E4\Synchronous

37G\Input Output Enable: This active LOW asynchronous input enables the data output drivers.

Various DQ0-63Input/Output Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.Various Vcc Supply Core power supply: +3.3V -5%/+10%Various

Vss

Ground

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Parameter Sym Min Typ Max Units Supply Voltage V CC 3.14 3.3 3.6V Supply Voltage V SS 0.00.00.0V Input High V IH 2.2 3.0V CC +0.3V Input Low V IL -0.30.00.8V Input Leakage ILi -212mA Output Leakage ILo -212mA Output High V OH 2.4--V I OH = -4mA Output Low V OL

--0.4

I OL = 8mA

RECOMMENDED DC OPERATING CONDITIONS

SYNCHRONOUS ONLY - TRUTH TABLE

Operation

E1\E2\E3\E4\GW\G\CLK DQ Synchronous Write-Bank 1L H H H L H ↑High-Z Synchronous Read-Bank 1L H H H H

L ↑Synchronous Write-Bank 2H L H H L H ↑ High-Z Synchronous Read-Bank 2H L H H H L ↑Synchronous Write-Bank 3H H L H L H ↑High-Z Synchronous Read-Bank 3H H L H H L ↑Synchronous Write-Bank 4H H H L L H ↑High-Z Synchronous Read-Bank 4H H H L H L ↑Snooze Mode

High-Z

*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

ABSOLUTE MAXIMUM RATINGS*

Voltage on Vcc Relative to Vss -0.5V to +4.6V Vin

-0.5V to Vcc +0.5V Storage Temperature

-55°C to +125°C Operating Temperature (Commercial)0°C to +70°C Operating Temperature (Industrial)-40°C to +85°C

Short Circuit Output Current

20mA

Max Description

Symbol Typ 9.510111215Units Power Supply Current Icc1 1.8* 1.2 1.1 1.00.9A Power Supply Current

Icc 0.8*0.90.80.80.7A Device Selected,No Operation

Snooze Mode IccZZ 500*700700700700mA CMOS Standby

Icc3270*350350350350mA Clock Running-Deselect

IccK

900

1.1

1.0

DC ELECTRICAL CHARACTERISTICS - READ CYCLE

*TBD

READ CYCLE TIMING PARAMETERS

9.5ns10ns11ns12ns15ns Description Symbol Min Max Min Max Min Max Min Max Min Max Units Clock Cycle Time t KHKH**12121520ns Clock High Time t KHKL**5556ns Clock Low Time t KLKH**5556ns Clock to Output Valid t KHQV**10111215ns Clock to Output Invalid t KHQX1**3333ns Clock to Output Low-Z t KHQX**2222ns Output Enable to Output Valid t GLQV**5556ns Output Enable to Output Low-Z t GLQX**0000ns Output Enable to Output High-Z t GHQZ**5556ns Address Setup t AVKH** 2.5 2.5 2.5 2.5ns Bank Enable Setup t EVKH** 2.5 2.5 2.5 2.5ns Address Hold t KHAX** 1.0 1.0 1.0 1.0ns Bank Enable Hold t KHEX** 1.0 1.0 1.0 1.0ns

*TBD

WRITE CYCLE TIMING PARAMETERS

9.5ns10ns11ns12ns15ns Description Symbol Min Max Min Max Min Max Min Max Min Max Units Clock Cycle Time t KHKH**12121520ns Clock High Time t KHKL**5556ns Clock Low Time t KLKH**5556ns Address Setup t AVKH** 2.5 2.5 2.5 2.5ns Address Hold t KHAX** 1.0 1.0 1.0 1.0ns Bank Enable Setup t EVKH** 2.5 2.5 2.5 2.5ns Bank Enable Hold t KHEX** 1.0 1.0 1.0 1.0ns Global Write Enable Setup t WVKH** 2.5 2.5 2.5 2.5ns Global Write Enable Hold t KHWX** 1.0 1.0 1.0 1.0ns Data Setup t DVKH** 2.5 2.5 2.5 2.5ns Data Hold t KHDX** 1.0 1.0 1.0 1.0ns

*TBD

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ORDERING INFORMATION

Part Number Organization Voltage Speed (ns)Package EDI2GG46464V95D*4x64Kx64 3.39.5120 Card Edge DIMM EDI2GG46464V10D4x64Kx64 3.310120 Card Edge DIMM EDI2GG46464V11D4x64Kx64 3.311120 Card Edge DIMM EDI2GG46464V12D4x64Kx64 3.312120 Card Edge DIMM EDI2GG46464V15D4x64Kx64 3.315120 Card Edge DIMM

*Consult Factory for Availability

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