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杭州矽力杰笔试

IC Design Engineer Test Sheet

Analog Design

Device Knowledge

1. p+/n- junction and p-/n+ junction, which has a higher breakdown voltage Why For

a p+/n- junction having N

A and N

D

, what is the approximate function of junction

capacitance (C

j ) vs. reverse biased voltage (V

R

)

2. Draw the cross-section of a CMOS inverter. Draw the parasitic structure on the cross-section. Describe ways to prevent “latch-up”

Circuit Analysis

3. See the figure below.

a. Draw the bode plot for this circuit.

b. Estimate the systematic offset in this amplifier.

c. Which is the positive input

杭州矽力杰笔试

4. See the figure below.

a. What is this circuit

b. Which input is the positive input

c. How much current flows in P

2

d. If I=10uA, what is a good selection for the value of R

e. What is the Common Mode Input Range for this circuit

f. What is the Common Mode Output Range for this circuit

g. Assume the only capacitance is from OUT to GND. Draw a Bode Plot.

=C What is the

h. Assume no load. What is the maximum positive slew rate if C

OUT

maximum negative slew rate

杭州矽力杰笔试

5. See the figure below.

Assume at time=0 inductor current is 0A. Draw inductor current, V

X and V

OUT

vs. time.

杭州矽力杰笔试

杭州矽力杰笔试

I

6. See the figure below.

a. What is this circuit

b. What is the desired ratio R

2/R

1

c. How many stable points does this circuit have

d. Assume R

1 and R

2

have no Temperature Coefficient. Draw a graph of I in R

2

vs.

Temperature.

e. What is the minimum supply voltage necessary for this circuit to work properly

杭州矽力杰笔试

OUT

7. See the figure below.

a. Write the gain equation of each circuit.

b. Assuming V O =0 at time 0. Sketch V O (t) for the given input signal.

A

杭州矽力杰笔试

杭州矽力杰笔试

B

杭州矽力杰笔试

杭州矽力杰笔试

C

8. Draw Buck Converter Circuit and key waveform, explain the basic operations at steady state.

Other

Must Answer (Question 1-3)

Question 1:

Write the V/I relationship equations for resistor (R), capacitor (C), and inductor (L).

Question 2:

Given V

B in Table 1, please calculate V

C

and V

E

. Assumptions: beta of NPN is infinity,

P-N junction forward voltage drop is .

杭州矽力杰笔试

杭州矽力杰笔试

Question 3:

假设图中理想放大器工作在深度负反馈状态,请计算下图输出端电压(V

)。

OUT

杭州矽力杰笔试

For Test Engineer (Question 4-5)

Question 4:

用C语言写一个递归算法求N!

Question 5:

C语言题目

a. 在编译环境下,下列类型变量需要占几个字节内存:

int

float

double

long

char

unsigned char

b. 以下程序的输出结果:

#define ADD(x) (x)+(x)

main()

{

int a=4, b=6, c=7, d=ADD(a+b)*c;

printf(“d=%d\n”,d);

}

c. 设int a=7,b=9,t;执行完表达式t=(a>b)a:b;后,t的值是

d. 设计一个排序函数,并同时获得最大值,最小值,均方根。函数名、排序数列等自行定义。

For AE Engineer (Question 6-8)

Question 6:

a. What is this circuit shown in the Figure

杭州矽力杰笔试

C1

b. Please draw the waveforms for V

2

for three cases (use the same scale):

C 1=open, R

3

=1k;

R 3=open, C

1

=1uF;

R 3=1k, C

1

=1uF.

杭州矽力杰笔试

杭州矽力杰笔试

0V

0V Question 7:

Draw bode plots of V

O /V

I

(gain and phase) for the circuit shown below. Please label

the proper pole/zero location.

杭州矽力杰笔试

V I

O

Case 1: R3=open

Case 2: R3=1K

Question 8:

Figure below shows a simple buck converter. The switching frequency of the converter is 1MHz.

L 1

I OUT

杭州矽力杰笔试

a. V IN =10V, V OUT =4V, I OUT =5A, what is the ON time of Q 2

b. Draw waveforms of V SW and I L1 below (under the same time scale of V G -V SW ). Assumption: I OUT =5A.

For Layout Engineer (Question 9-12)

Question 9: 简述CMOS 工艺流程。

Question 10:

Draw the layout of a two-input NAND gate.

杭州矽力杰笔试

Z

A

B

Question 11:

下面电路图中有两个MOSFET(M

A and M

B

)

杭州矽力杰笔试

。假设每个MOSFET有两个gate figure,右下版图应

该如何连接,才能使M

A

和M

B

匹配。

杭州矽力杰笔试

Question 12:

画出不同的电流镜图,并简述各自特点。