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AD5764中文资料

Complete, Quad, 16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DAC Preliminary Technical Data AD5764

Rev.PrC 21-Oct-04

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: https://www.wendangku.net/doc/613908145.html, Fax: 781.326.8703? 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Complete quad 16-bit D/A converter

Programmable output range: ±10 V, ±10.25 V, or ±10.5 V ±1 LSB max INL error, ±1 LSB max DNL error

Low noise : 60 nV/√Hz

Settling time: 10μs max

Integrated reference buffers

Internal reference, 10 ppm/°C

On-chip temp sensor, ±5°C accuracy

Output control during power-up/brownout Programmable short-circuit protection

Simultaneous updating via LDAC

Asynchronous CLR to zero code

Digital offset and gain adjust

Logic output control pins

DSP/microcontroller compatible serial interface Temperature range:?40°C to +85°C

i CMOS? Process Technology

APPLICATIONS

Industrial automation

Closed-loop servo control, process control

Data acquisition systems

Automatic Test Equipment

Automotive test and measurement

High accuracy instrumentation GENERAL DESCRIPTION

The AD5764 is a quad, 16-bit serial input, voltage output

digital-to analog converter that operates from supply voltages of ±12 V up to ±15 V. Nominal full-scale output range is ±10 V, provided are integrated output amplifiers, reference buffers, internal reference, and proprietary power-up/power-down control circuitry. It also features a digital I/O port that may be programmed via the serial interface, and an analog temperature sensor. The part incorporates digital offset and gain adjust registers per channel.

The AD5764 is a high performance converter that offers guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low noise and 10 μs settling time and includes an on-chip 5 V reference with a reference tempco of 10 ppm/°C max. During power-up (when the supply voltages are changing), Vout is clamped to 0V via a low impedance path.

The AD5764 uses a serial interface that operates at clock rates up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or straight binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero-scale depending on the coding used. The AD5764 is ideal for both closed-loop servo control and open-loop control applications. The AD5764 is available in a 32-lead TQFP package, and offers guaranteed specifications over the ?40°C to +85°C industrial temperature range. See functional block diagram, Figure 1.

i CMOS? Process Technology

For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, i CMOS is a technology platform that enables the development of analog ICs capable of 30V and operating at +/-15V supplies while allowing dramatic reductions in power consumption and package size, and increased AC and DC performance.

AD5764

Preliminary Technical Data

Rev. PrC 21-Oct-04| Page 2 of 28

TABLE OF CONTENTS

Functional Block Diagram..............................................................3 Specifications.....................................................................................4 AC Performance Characteristics................................................6 Timing Characteristics................................................................7 Absolute Maximum Ratings..........................................................10 ESD Caution................................................................................10 Pin Configuration and Function Descriptions...........................11 Terminology....................................................................................13 Typical Performance Characteristics........Error! Bookmark not defined.

General Description.......................................................................15 dac architecture...........................................................................16 Reference Buffers........................................................................16 Serial interface............................................................................16 Simultaneous Updating Via LDAC ..........................................17 transfer function.........................................................................18 Asynchronous Clear (CLR ).......................................................18 Function Register.......................................................................20 DAta register...............................................................................21 Coarse gain register....................................................................21 Fine gain register........................................................................21 offset register...............................................................................22 AD5764 Features............................................................................23 Analog Output Control.............................................................23 Digital Offset and Gain Control...............................................23 Programmable Short-Circuit protection.................................23 Digital I/O Port...........................................................................23 Temperature Sensor...................................................................23 Local ground offset adjust.........................................................23 Outline Dimensions.......................................................................24 Ordering Guide.. (28)

REVISION HISTORY

Revision PrC 21-Oct-04: Preliminary Version

Preliminary Technical Data

AD5764

Rev. PrC 21-Oct-04| Page 3 of 28

FUNCTIONAL BLOCK DIAGRAM

AGNDD

VOUTD AGNDC

VOUTC

AGNDB

VOUTB AGNDA

VOUTA

ISCC

04641-P r A -001

Figure 1. Functional Block Diagram

AD5764 Preliminary Technical Data

SPECIFICATIONS

AV DD = +11.4 V to +15.75 V, AV SS = ?11.4 V to ?15.75 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;

DV CC = 2.7 V to 5.5 V, R LOAD = 10 k?, C L = 200 pF. All specifications T MIN to T MAX, unless otherwise noted.

1 Temperature range ?40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.

2 Guaranteed by characterization. Not production tested.

3 Output amplifier headroom requirement is 1.

4 V min.

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Preliminary Technical Data

AD5764

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Parameter

A Grade 1

B Grade 1

C Grade 1 Unit Test Conditions/Comments DIGITAL INPUTS 2

DV CC = 2.7 V to 5.5 V, JEDEC compliant V IH , Input High Voltage 2 2 2 V min V IL , Input Low Voltage 0.8 0.8 0.8 V max

Input Current ±10 ±10 ±10 μA max Total for All Pins. T A = T MIN to T MAX . Pin Capacitance

10 10 10 pF max DIGITAL OUTPUTS (D0,D1, SDO) 2

Output Low Voltage 0.4

0.4

V max DV CC = 5 V ± 10%, sinking 200 μA Output High Voltage DV CC – 1 DV CC – 1 DV CC – 1 V min DV CC = 5 V ± 10%, Sourcing 200 μA

Output Low Voltage 0.4 0.4 0.4 V max DV CC = 2.7 V to 3.6 V, Sinking 200 μA

Output High Voltage DV CC – 0.5 DV CC – 0.5 DV CC – 0.5 V min DV CC = 2.7 V to 3.6 V, Sourcing 200 μA High Impedance Leakage Current

±1 ±1 ±1 μA max SDO only High Impedance Output Capacitance

pF typ

SDO only

TEMP SENSOR Accuracy ±1 ±1 ±1 °C typ At 25°C

±5 ±5 ±5 °C max ?40°C < T <+85°C Output Voltage @ 25°C

1.5 1.5 1.5 V typ Output Voltage Scale Factor 5 5 5 mV/°C typ Output Voltage Range 0/3.0 0/3.0 0/3.0 V min/max

Output Load Current 200 200 200 μA max Current source only. Power On Time

10 10 10 ms typ To within ±5°C POWER REQUIREMENTS

AV DD /AV SS 11.4/15.75 11.4/15.75 11.4/15.75 V min/max DV CC

2.7/5.5 2.7/5.5 2.7/5.5 V min/max Power Supply Sensitivity 4 ?V OUT /?ΑV DD ?85 ?85 ?85 dB typ

AI DD 3.75 3.75 3.75 mA/Channel max Outputs unloaded AI SS 2.75 2.75 2.75 mA/Channel max Outputs unloaded

DI CC 1 1 1 mA max V IH = DV CC , V IL = DGND. TBD mA typ

Power Dissipation

244

mW typ

±12 V operation output unloaded

Guaranteed by characterization. Not production tested.

AD5764 Preliminary Technical Data

AC PERFORMANCE CHARACTERISTICS

AV DD = +11.4 V to +15.75 V, AV SS = ?11.4 V to ?15.75 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;

DV CC = 2.7 V to 5.5 V, R LOAD = 10 k?, C L = 200 pF. All specifications T MIN to T MAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.

5 Guaranteed by design and characterization. Not production tested.

6 Includes noise contributions from integrated reference buffers, 16-bit DAC and output amplifier.

Rev. PrC 21-Oct-04| Page 6 of 28

Preliminary Technical Data AD5764

TIMING CHARACTERISTICS

AV DD = +11.4 V to +15.75 V, AV SS = ?11.4 V to ?15.75 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext;

DV CC = 2.7 V to 5.5 V, R LOAD = 10 k?, C L = 200 pF. All specifications T MIN to T MAX, unless otherwise noted.

7 Guaranteed by design and characterization. Not production tested.

8 All input signals are specified with t r = t f = 5 ns (10% to 90% of DV CC) and timed from a voltage level of 1.2 V.

9 See Figure 2, Figure 3, and Figure 4.

10 Stand-alone mode only.

11 Measured with the load circuit of Figure 5.

12 Daisy-chain mode only.

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AD5764

Preliminary Technical Data

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SCLK

SYNC

SDIN

LDAC

V OUT

LDAC = 0

V OUT

04641-P r A -002

Figure 2. Serial Interface Timing Diagram

LDAC

SDO

SDIN

SYNC

SCLK

04641-P r A -003

Figure 3. Daisy Chain Timing Diagram

Preliminary Technical Data

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Rev. PrC 21-Oct-04| Page 9 of 28

SDO

SDIN SYNC

SCLK

DB23DB0DB23DB0

DB23

SELECTED REGISTER DATA

CLOCKED OUT

UNDEFINED

NOP CONDITION

INPUT WORD SPECIFIES REGISTER TO BE READ

DB0

04641-P r A -005

Figure 4. Readback Timing Diagram

V OH (MIN) OR V OL (MAX)

TO OUTPUT

04641-P r A -004

Figure 5. Load Circuit for SDO Timing Diagram

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ABSOLUTE MAXIMUM RATINGS

T A = 25°C unless otherwise noted.

Transient currents of up to 100 mA will not cause SCR latch-up.

Table 4.

Parameter Rating

AV DD to AGND, DGND ?0.3 V to +17 V

AV SS to AGND, DGND +0.3 V to ?17 V

DV CC to DGND

?0.3 V to +7 V

Digital Inputs to DGND ?0.3 V to DV CC + 0.3 V Digital Outputs to DGND ?0.3 V to DV CC + 0.3 V REF IN to AGND, PWRGND ?0.3 V to +17 V REF OUT to AGND AV SS to AV DD V OUT A,B,C,D to AGND AV SS to AV DD AGND to DGND

?0.3 V to +0.3 V Operating Temperature Range

Industrial

?40°C to +85°C Storage Temperature Range ?65°C to +150°C Junction Temperature (T J max) 150°C 32-Lead TQFP Package, θJA Thermal Impedance TBD°C/W Reflow Soldering

Peak Temperature

220°C

Time at Peak Temperature

10 sec to 40 sec

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Preliminary Technical Data

AD5764

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGNDA VOUTA VOUTB AGNDB AGNDC VOUTC VOUTD AGNDD

I N /2s C O M P V D D

V S S

E M P E

G N D E F O U T E F C D E F A B

04641-P r A -007

Figure 6. 32-Lead TQFP Pin Configuration Diagram

Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.

AD5764 Preliminary Technical Data

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TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer

function. A typical INL vs. code plot can be seen in Figure ?. Differential Nonlinearity

Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure ?. Monotonicity

A DAC is monotonic, if the output either increases or remains constant for increasing digital input code. The AD5764 is monotonic over its full operating temperature range Bipolar Zero Error

Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (Straight Binary coding) or 0x0000 (2sComplement coding) Full-Scale Error

Full-scale error is a measure of the output error when full-scale code (FFFF Hex) is loaded to the DAC register. Ideally the output should be programmed full scale value – 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure ?. Negative Full-Scale Error / Zero Scale Error

Negative full-scale error is the error in the DAC output voltage when 0x0000 (Straight Binary coding) or 0x8000

(2sComplement coding) is loaded to the DAC register. Ideally the output voltage should be programmed negative full scale value – 1 LSB.

Output Voltage Settling Time

Output voltage settling time is the amount od time it takes for the output to settle to a specified level for a full-scale input change. Slew Rate

The slew rate of a device is a limatation in the rate of change of the output voltage. The output slewing speed of a voltage-output D/A converter is usually limited by the slew rate of the

amplifierused at its output. Slew rate is measured from 10% to 90% of the output signal and is given in Vμs. Gain Error

This is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error

Total Unadjusted Error (TUE) is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure ?. Zero-Code Error Drift

This is a measure of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Error Drift

This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital input code is changed by

1 LSB at the major carry transition (7FFF Hex to 8000 Hex). See Figure ?.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. Power Supply Sensitivity

Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. DC Crosstalk

This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in μV . DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC

AD5764

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Rev. PrC 21-Oct-04| Page 14 of 28

due to a digital code changeand subsequent output change of another DAC. This includes both digital and anlalog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with /LDAC low and

monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB.

Preliminary Technical Data AD5764 TYPICAL PERFORMANCE CHARACTERISTICS

Rev. PrC 21-Oct-04| Page 15 of 28

AD5764

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GENERAL DESCRIPTION

The AD5764 is a quad 16-bit, serial input, bipolar voltage output DAC. It operates from supply voltages of ±11.4 V to ±16.5 V and has a buffered output voltage of up to ± 10.25 V . Data is written to the AD5764 in a 24-bit word format, via a 3-wire serial interface. The device also offers an SDO pin, which is available for daisy chaining or readback.

The AD5764 incorporates a power-on reset circuit, which

ensures that the DAC outputs power up to 0V . The AD5764 also features a digital I/O port that may be programmed via the serial interface, an analog temperature sensor, on-chip 10 ppm/°C voltage reference, on-chip reference buffers and per channel digital gain and offset registers.

DAC ARCHITECTURE

The DAC architecture of the AD5764 consists of a 16-bit current-mode segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 13.

The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGND or IOUT. The remaining 12 bits of the data word drive switches S0 to S11 of the 12-bit R-2R ladder network.

V ref

12 BIT R-2R LADDER

4 MSBs DECODED INTO 1

5 EQUAL SEGMENTS

Figure 7. DAC Ladder Structure

REFERENCE BUFFERS

The AD5764 can operate with either an external or internal reference. The reference inputs (REFAB and REFCD) have an input range up to 5 V . This input voltage is then used to provide a buffered positive and negative reference for the DAC cores. The positive reference is given by + V REF = 2* V REF

While the negative reference to the DAC cores is given by -V REF = -2*V REF

These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs.

SERIAL INTERFACE

The AD5764 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE and DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits and 16 data bits as shown in Table 6. The timing diagram for this operation is shown in Figure 2.

Upon power-up the DAC registers are loaded with zero code (0x0000). The corresponding output voltage depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to DGND then the data coding is 2sComplement and the outputs will power-up to 0V . If the BIN/2sCOMP pin is tied high then the data coding is straight binary and the outputs will power-up to Negative Full-scale.

Standalone Operation

The serial interface works with both a continuous and noncon-tinuous serial clock. A continuous SCLK source can only be used if is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought back high again; if SYNC is brought high before the 24th falling SCLK edge, the write is aborted. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data will be corrupted. The input register addressed is updated on the rising edge of . In order for another serial transfer to take place, must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the input register of the addressed DAC. When the data has been transferred into the input register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low while SYNC is high.

Preliminary Technical Data

AD5764

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*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 8. Daisy chaining the AD5764

Daisy-Chain Operation

For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5764s in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock may be a continuous or a gated clock. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock

containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data.

Readback Operation

Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A2–A0, in association with Bits REG2 , REG1, and REG0, select the register to be read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO output will contain the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the fine gain register of Channel A on the AD5764, the following sequence should be implemented. First, write 0xA0XXXX to the AD5764 input register. This configures the AD5764 for read mode with the fine gain register of Channel A selected. Note that all the data bits, D15 to D0, are don’t cares. Follow this with a second write, a NOP condition, 0x00XXXX. During this write, the data from the fine gain register is clocked out on the SDO line, i.e., data clocked out will contain the data from the fine gain register in Bits D5 to D0.

SIMULTANEOUS UPDATING VIA LDAC

After data has been transferred into the input register of the DACs, there are two ways in which the DAC registers and DAC outputs can be updated. Depending on the status of both SYNC and LDAC , one of two update modes is selected.

Individual DAC Updating

In this mode, LDAC is held low while data is being clocked into the input shift register. The addressed DAC output is updated on the rising edge of SYNC .

Simultaneous Updating of All DACs

In this mode, LDAC is held high while data is being clocked into the input shift register. All DAC outputs are updated by taking LDAC low any time after SYNC has been taken high. The update now occurs on the falling edge of LDAC .

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V OUT

OUTPUT V

Figure 9. Simplified Serial Interface showing input loading circuitry for one DAC Channel

TRANSFER FUNCTION

Table ? Shows the ideal input code to output voltage relationship for the AD5764 for both straight binary and twos complement data coding.

Digital Input

Analog Output

Straight Binary Data Coding

MSB LSB V OUT

1111 1111 1111 1111 +2 V REF x (32767/32768)

1000 0000 0000 0001 +2 V REF x (1/32768) 1000 0000 0000 0000 0 V 0111 1111 1111 1111 -2 V REF x (1/32768)

0000 0000 0000 0000 -2 V REF x (32767/32768)

Twos Complement Data Coding MSB LSB

V OUT 0111 1111 1111 1111

+2 V REF x (32767/32768) 0000 0000 0000 0001 +2 V REF x (1/32768) 0000 0000 0000 0000

0 V 1111 1111 1111 1111

-2 V REF x (1/32768) 1000 0000 0000 0000 -2 V REF x (32767/32768) The output voltage expression is given by

???

?×+×?=6553642D V V V REFIN REFIN OUT where:

D is the decimal equivalent of the code loaded to the DAC. V REFIN is the reference voltage applied at the REFIN pin.

ASYNCHRONOUS CLEAR (CLR)

CLR is an active low, level sensitive clear that allows the outputs to be cleared to either 0 V (straight binary coding) or negative full scale (twos complement coding). It is necessary to maintain CLR low for a minimum amount of time (refer to Figure 3) for the operation to complete. When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. The CLR signal has priority over LDAC and

SYNC . A clear can also be initiated through software by writing the command 0x04XXXX to the AD5764.

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Table 6. Input Register Format

Table 7. Input Register Bit Functions

FUNCTION REGISTER

The Function Register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The Functions available through the function register are shown in Table 8 and Table 9.

Table 8. Function Register Options

REG2 REG1 REG0 A2 A1 A0 D15 …. D6 D5 D4 D3 D2

D1 D0 0 0 0 0 0 0 NOP, Data = Don’t Care

0 0 0 0 0 1 Don’t Care Local-Ground-Offset Adjust D1

Direction D1 Value D0 Direction D0 Value

SDO Disable

0 0 0 1 0 0 CLR, Data = Don’t Care 0 0 0 1 0 1

LOAD, Data = Don’t Care

Table 9. Explanation of Function Register Options

NOP

No operation instruction used in readback operations.

Local-Ground-Offset Adjust Set by the user to enable local-ground-offset adjust function.

Cleared by the user to disable local-ground-offset adjust function (default). D0 / D1 Direction Set by the user to enable D0/D1 as outputs.

Cleared by the user to enable D0/D1 as inputs (default). Have weak internal pull-ups.

D0 / D1 Value

I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation. SDO Disable Set by the user to disable the SDO output.

Cleared by the user to enable the SDO output (default).

CLR Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.

LOAD

Addressing this function updates the DAC registers and consequently the analog outputs.

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DATA REGISTER

The Data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC Channel the Data transfer is to take place (Refer to Table 7). The 16 data bits are in positions D15 to D0 as shown in Table 10.

Table 10. Programming the Data Register

REG2 REG1 REG0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D 0 1 0 DAC Address 16 Bit DAC Data

COARSE GAIN REGISTER

The Coarse Gain Register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC Channel the Data transfer is to take place (Refer to Table 7). The Coarse Gain Register ia a 2-bit register and allows the user to select the output range of each DAC as shown in Table 12.

Table 11. Programming the Coarse Gain Register

REG2 REG1 REG0 A2 A1 A0 D15 …. D2 D1 D0 0 1 1 DAC Address Don’t Care CG1 CG0

Table 12. Output Range Selection

Output Range CG1 CG0 ± 10 V 0 0 ± 10.25 V 0 1 ± 10.5 V

FINE GAIN REGISTER

The Fine Gain Register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC Channel the Data transfer is to take place (Refer to Table 7). The Fine Gain Register is a 6-bit register and allows the user to adjust the gain of each DAC channel by -32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 13 and Table 14. Table 13. Programming the Fine Gain Register

REG2 REG1 REG0 A2 A1 A0 D15 …. D6 D5 D4 D3 D2 D1 D0 1 0 0 DAC Address Don’t Care F

G5 F

G4 F

G3 F

G2 F

G1 F

Table 14. Fine Gain Register Options

Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0

+31 LSBs 0 0 0 0 0 0 +30 LSBs 0 0 0 0 0 1 - - - - - - No Adjustment 1 0 0 0 0 0 - - - - - - -31 LSBs 1 1 1 1 1 0 -32 LSBs

1 1 1 1 1 1