SRAM
SD Card
Audio CODEC
HDMI TX
HSMC Interface
ADC
GPIO - 2x20 Header and Arduino Interface
Switch and Key
LED and 7'Segment
UART to USB Bridge
Power
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.
All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
Title
5
4
3
2
Title
Size Document Number Date:
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Block Diagram
Cyclone V GX Starter Kit
B Friday, November 15, 2013
SWITCH
7-SEGMENT
ADC Interface
DDR2LP_DQ7
DDR2LP_DM0DDR2LP_DQ4DDR2LP_DQ5DDR2LP_DQ14DDR2LP_DQ15
DDR2LP_CKE0DDR2LP_DM1DDR2LP_DQ12DDR2LP_DQ13DDR2LP_DQ11DDR2LP_CKE1DDR2LP_DQS_n1DDR2LP_DQS_p1DDR2LP_DQ8DDR2LP_DQ9GND
DDR2LP_DQ10DDR2LP_CA0DDR2LP_CA1
SW[9..0]
HEX0_D[6..0]HEX1_D[6..0]
ADC_CONVST ADC_SCK ADC_SDO ADC_SDI
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
IO_4A/DIFFIO_RX_B30N/DQ4B/B_DQ_4Y13IO_4A/DIFFIO_RX_B30P/DQ4B/B_DQ_5W12IO_4A/DIFFIO_TX_B32N/DQ4B/B_DQ_7AF12IO_4A/DIFFIO_TX_B32P/DQ4B/B_DM_0AF11IO_4A/DIFFIO_TX_B33N/GND AC13IO_4A/DIFFIO_RX_B34N/DQ5B/B_DQ_8AC15IO_4A/DIFFIO_TX_B33P/DQ5B/B_DQ_10AC14IO_4A/DIFFIO_RX_B34P/DQ5B/B_DQ_9AB15IO_4A/DIFFIO_RX_B35N/DQSN5B/B_DQSN_1V14IO_4A/DIFFIO_TX_B36N/DQ5B/B_DQ_11AF13IO_4A/DIFFIO_RX_B35P/DQS5B/B_DQS_1U14IO_4A/DIFFIO_TX_B36P/B_CKE_1AE13IO_4A/DIFFIO_TX_B37N/DQ5B/B_CKE_0AF14IO_4A/DIFFIO_RX_B38N/DQ5B/B_DQ_12AB16IO_4A/DIFFIO_TX_B37P/DQ5B/B_DQ_14AE14IO_4A/DIFFIO_RX_B38P/DQ5B/B_DQ_13AA16IO_4A/DIFFIO_TX_B40N/DQ5B/B_DQ_15AF18
IO_4A/DIFFIO_TX_B40P/DQ5B/B_DM_1AE18IO_4A/DIFFIO_RX_B46N/DQ6B/B_DQ_20
IO_4A/DIFFIO_RX_B46P/DQ6B/B_DQ_21IO_4A/DIFFIO_TX_B48N/DQ6B/B_DQ_23IO_4A/DIFFIO_TX_B48P/DQ6B/B_DM_2IO_4A/DIFFIO_RX_B50N/DQ7B/B_DQ_24IO_4A/DIFFIO_TX_B49P/DQ7B/B_DQ_26IO_4A/DIFFIO_RX_B50P/DQ7B/B_DQ_25IO_4A/DIFFIO_RX_B51N/DQSN7B/B_DQSN_3IO_4A/DIFFIO_TX_B52N/DQ7B/B_DQ_27IO_4A/DIFFIO_RX_B51P/DQS7B/B_DQS_3IO_4A/DIFFIO_RX_B54N/DQ7B/B_DQ_28
IO_4A/DIFFIO_TX_B53P/DQ7B/B_DQ_30IO_4A/DIFFIO_RX_B54P/DQ7B/B_DQ_29IO_4A/DIFFIO_TX_B56N/DQ7B/B_DQ_31
IO_4A/DIFFIO_TX_B56P/DQ7B/B_DM_3IO_4A/DIFFIO_RX_B58N/DQ8B/B_DQ_32IO_4A/DIFFIO_TX_B57P/DQ8B/B_DQ_34
IO_4A/DIFFIO_RX_B58P/DQ8B/B_DQ_33IO_4A/DIFFIO_RX_B59N/DQSN8B/B_DQSN_4
IO_4A/DIFFIO_TX_B60N/DQ8B/B_DQ_35IO_4A/DIFFIO_RX_B59P/DQS8B/B_DQS_4IO_4A/DIFFIO_RX_B62N/DQ8B/B_DQ_36
IO_4A/DIFFIO_TX_B61P/DQ8B/B_DQ_38
IO_4A/DIFFIO_RX_B62P/DQ8B/B_DQ_37IO_4A/DIFFIO_TX_B64N/DQ8B/B_DQ_39
IO_4A/DIFFIO_TX_B64P/DQ8B/B_DM_4IO_3B/DIFFIO_TX_B24N/DQ3B/B_CA_1
AF6
IO_3B/DIFFIO_TX_B24P/DQ3B/B_CA_0AE6
SRAM_D0SRAM_D1SRAM_D2SRAM_D3SRAM_D4SRAM_D5SRAM_D6SRAM_D7SRAM_D8SRAM_D9SRAM_D10SRAM_D11SRAM_D12SRAM_D13SRAM_D14SRAM_D15
HDMI_TX_VS HDMI_TX_HS
HDMI_TX_D19HDMI_TX_D1HDMI_TX_D2HDMI_TX_D3HDMI_TX_D5
HDMI_TX_D6HDMI_TX_D9HDMI_TX_D11HDMI_TX_D18HDMI_TX_D17HDMI_TX_D16HDMI_TX_D15HDMI_TX_D12HDMI_TX_D14Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
5CGXFC5C6F27C7N
IO_6A/DIFFIO_TX_R34P/DQ5R E24IO_6A/DIFFIO_TX_R34N/DQ5R E25IO_6A/DIFFIO_RX_R35P/DQ5R K24IO_6A/DIFFIO_TX_R36P/DQ5R F24IO_6A/DIFFIO_RX_R35N/DQ5R K23IO_6A/DIFFIO_TX_R36N/DQ5R G24IO_6A/DIFFIO_RX_R37P/DQS5R L23IO_6A/DIFFIO_TX_R38P
H23IO_6A/DIFFIO_RX_R37N/DQSN5R L24IO_6A/DIFFIO_TX_R38N/DQ5R H24IO_6A/DIFFIO_RX_R39P/DQ5R H22IO_6A/DIFFIO_TX_R40P/DQ5R F23IO_6A/DIFFIO_RX_R39N/DQ5R J23IO_6A/DIFFIO_TX_R40N G22IO_6A/DIFFIO_RX_R41P L22IO_6A/DIFFIO_RX_R41N
K21
IO_5B/DIFFIO_RX_R15P/DQ2R R24IO_5B/DIFFIO_TX_R16P/DQ2R
U24IO_5B/DIFFIO_RX_R15N/DQ2R R25IO_5B/DIFFIO_TX_R16N
V25
IO_5B/DIFFIO_TX_R18P/DQ3R AB26IO_5B/DIFFIO_TX_R18N/DQ3R AA26IO_5B/DIFFIO_RX_R19P/DQ3R T26IO_5B/DIFFIO_RX_R19N/DQ3R
R26IO_5B/DIFFIO_RX_R21P/DQS3R P21IO_5B/DIFFIO_TX_R22P
W25IO_5B/DIFFIO_RX_R21N/DQSN3R
P22IO_5B/DIFFIO_TX_R22N/DQ3R W26IO_5B/DIFFIO_RX_R23P/DQ3R N25IO_5B/DIFFIO_TX_R24P/DQ3R
U25IO_5B/DIFFIO_RX_R23N/DQ3R P26IO_5B/DIFFIO_TX_R24N
U26
Audio CODEC
HSMC_D0
HSMC_RX_n0HSMC_RX_p0HSMC_RX_n10HSMC_RX_p10HSMC_RX_p9HSMC_RX_n9HSMC_RX_p11HSMC_RX_n11HSMC_RX_n12HSMC_RX_p12HSMC_RX_p1HSMC_RX_n1HSMC_RX_n7HSMC_RX_p7HSMC_TX_n8HSMC_TX_p8HSMC_TX_p9HSMC_TX_n9
HSMC_TX_p10HSMC_TX_n10HSMC_TX_p0HSMC_TX_n0
HSMC_TX_p2HSMC_TX_n2HSMC_TX_n1HSMC_TX_p1HSMC_TX_n4HSMC_TX_p4HSMC_TX_n3HSMC_TX_p3HSMC_TX_n6HSMC_TX_p6AUD_XCK 13AUD_DACDAT 13AUD_ADCDAT 13AUD_DACLRCK 13AUD_ADCLRCK
13
AUD_BCLK 13Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
5CGXFC5C6F27C7N
IO_7A/DIFFIO_TX_T6N/DQ1T/T_DQ_35IO_7A/DIFFIO_RX_T7P/DQ1T/T_DQ_33IO_7A/DIFFIO_TX_T8P/DQ1T/T_DQ_34IO_7A/DIFFIO_RX_T7N/DQ1T/T_DQ_32IO_7A/DIFFIO_TX_T10P/DQ2T/T_DM_3IO_7A/DIFFIO_TX_T10N/DQ2T/T_DQ_31IO_7A/DIFFIO_RX_T11P/DQ2T/T_DQ_29IO_7A/DIFFIO_TX_T12P/DQ2T/T_DQ_30IO_7A/DIFFIO_RX_T11N/DQ2T/T_DQ_28IO_7A/DIFFIO_RX_T13P/DQS2T/T_DQS_3IO_7A/DIFFIO_RX_T13N/DQSN2T/T_DQSN_3IO_7A/DIFFIO_TX_T14N/DQ2T/T_DQ_27IO_7A/DIFFIO_RX_T15P/DQ2T/T_DQ_25IO_7A/DIFFIO_TX_T16P/DQ2T/T_DQ_26IO_7A/DIFFIO_RX_T15N/DQ2T/T_DQ_24IO_7A/DIFFIO_TX_T22P/T_RESETN B15IO_7A/DIFFIO_TX_T22N/DQ3T/T_DQ_19C15IO_7A/DIFFIO_RX_T23P/DQ3T/T_DQ_17C14IO_7A/DIFFIO_TX_T24P/DQ3T/T_DQ_18
A8IO_7A/DIFFIO_RX_T23N/DQ3T/T_DQ_16D15IO_7A/DIFFIO_TX_T24N/GND
A9
IO_7A/DIFFIO_TX_T26P/DQ4T/T_DM_1
C9IO_7A/DIFFIO_TX_T26N/DQ4T/T_DQ_15B9IO_7A/DIFFIO_RX_T27P/DQ4T/T_DQ_13E16IO_7A/DIFFIO_TX_T28P/DQ4T/T_DQ_14D10IO_7A/DIFFIO_RX_T27N/DQ4T/T_DQ_12D16IO_7A/DIFFIO_TX_T28N/DQ4T/T_CKE_0C10IO_7A/DIFFIO_RX_T29P/DQS4T/T_DQS_1N12IO_7A/DIFFIO_TX_T30P/T_CKE_1B10IO_7A/DIFFIO_RX_T29N/DQSN4T/T_DQSN_1
M12IO_7A/DIFFIO_TX_T30N/DQ4T/T_DQ_11A11IO_7A/DIFFIO_RX_T31P/DQ4T/T_DQ_9F16IO_7A/DIFFIO_TX_T32P/DQ4T/T_DQ_10
E10IO_7A/DIFFIO_RX_T31N/DQ4T/T_DQ_8E15IO_7A/DIFFIO_TX_T32N/GND
E11IO_7A/DIFFIO_TX_T34P/DQ5T/T_DM_0B12IO_7A/DIFFIO_TX_T34N/DQ5T/T_DQ_7A13IO_7A/DIFFIO_RX_T35P/DQ5T/T_DQ_5G12IO_7A/DIFFIO_TX_T36P/DQ5T/T_DQ_6A12IO_7A/DIFFIO_RX_T35N/DQ5T/T_DQ_4F12IO_7A/DIFFIO_TX_T36N/DQ5T/T_ODT_1B11IO_7A/DIFFIO_RX_T37P/DQS5T/T_DQS_0M11IO_7A/DIFFIO_TX_T38P/T_ODT_0C13IO_7A/DIFFIO_RX_T37N/DQSN5T/T_DQSN_0
L11IO_7A/DIFFIO_TX_T38N/DQ5T/T_DQ_3C12IO_7A/DIFFIO_RX_T39P/DQ5T/T_DQ_1E13IO_7A/DIFFIO_TX_T40P/DQ5T/T_DQ_2
D11IO_7A/DIFFIO_RX_T39N/DQ5T/T_DQ_0D13
GXB L2 is C7 FPGA only
HSMC_GXB_RX_p3HSMC_GXB_RX_n3
HSMC_GXB_TX_p3HSMC_GXB_TX_n3SMA_GXB_TX_p
SMA_GXB_RX_p
REFCLK_p1REFCLK_n1
SMA_GXB_RX_p SMA_GXB_RX_n
SMA_GXB_TX_p SMA_GXB_TX_n Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GXB_L1
GXB_L2
5CGXFC5C6F27C7N
REFCLK1LN
P6
REFCLK1LP N7GXB_TX_L5N
K1
GXB_TX_L5P K2GXB_RX_L5P,GXB_REFCLK_L5P M2GXB_RX_L5N,GXB_REFCLK_L5N M1GXB_TX_L4N P1GXB_TX_L4P P2GXB_RX_L4P,GXB_REFCLK_L4P T2GXB_RX_L4N,GXB_REFCLK_L4N T1GXB_TX_L3N W3GXB_TX_L3P W4GXB_RX_L3P,GXB_REFCLK_L3P V2GXB_RX_L3N,GXB_REFCLK_L3N V1RREF_TL
B1
GXB_RX_L8n,GXB_REFCLK_L8n D1GXB_RX_L8p,GXB_REFCLK_L8p D2GXB_RX_L7n,GXB_REFCLK_L7n F1GXB_RX_L7p,GXB_REFCLK_L7p F2GXB_RX_L6n,GXB_REFCLK_L6n H1GXB_RX_L6p,GXB_REFCLK_L6p H2GXB_TX_L6p G4GXB_TX_L6n G3GXB_TX_L7p E4GXB_TX_L7n E3GXB_TX_L8p C4GXB_TX_L8n
C3
REFCLK2Lp M6REFCLK2Ln
L5
R1990
R204
2K
J12
J7
R1980
C1360.01u
VCCIO = 3.3V
VCCIO = 3.3V
VCCIO = 2.5V
VCCIO = 2.5V
HSMC_CLKIN_p1HSMC_CLKIN_n1
CLOCK_50_B7A HSMC_CLKIN_n1HSMC_CLKIN_n2
CLOCK_50_B5B CLOCK_50_B6A GPIO0GPIO2I2C_SDA
CLOCK_125_n GPIO8GPIO7GPIO6GPIO4
CLOCK_50_B8A HSMC_CLKIN0HSMC_CLKIN_p2HSMC_CLKIN_n2VCC2P5VCC2P5VCC2P5
VCC3P3
VCC2P5
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
C2690.1u 10V C2680.1u 10V
C1110.1u 10V
R188100R197
100
R200100R11220K
C2670.1u 10V Bank 5B
Bank 6A
Bank 7A
Bank 8A
5CGXFC5C6F27C7N
IO_5B/CLK7P,FPLL_BR_FBP/DIFFIO_RX_R9P T21IO_5B/CLK7N,FPLL_BR_FBN/DIFFIO_RX_R9N
T22
IO_5B/CLK6P/DIFFIO_RX_R17P R20IO_5B/CLK6N/DIFFIO_RX_R17N
P20IO_5B/FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTP,FPLL_BR_FB/DIFFIO_TX_R20P/DQ3R
IO_5B/FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTN/DIFFIO_TX_R20N/DQ3R
IO_6A/CLK5P/DIFFIO_RX_R25P N20IO_6A/CLK5N/DIFFIO_RX_R25N
M21IO_6A/FPLL_TR_CLKOUT0,FPLL_TR_CLKOUTP,FPLL_TR_FB/DIFFIO_TX_R28P/DQ4R
IO_6A/FPLL_TR_CLKOUT1,FPLL_TR_CLKOUTN/DIFFIO_TX_R28N/DQ4R
IO_6A/CLK4P,FPLL_TR_FBP/DIFFIO_RX_R33P K25IO_6A/CLK4N,FPLL_TR_FBN/DIFFIO_RX_R33N
K26
IO_7A/CLK11P/DIFFIO_RX_T25P G15IO_7A/CLK11N/DIFFIO_RX_T25N
G14
IO_7A/CLK10P/DIFFIO_RX_T33P H12IO_7A/CLK10N/DIFFIO_RX_T33N G11IO_8A/CLK9P/DIFFIO_RX_T41P N9IO_8A/CLK9N/DIFFIO_RX_T41N
M10
IO_8A/FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTP,FPLL_TL_FB/DIFFIO_TX_T44P/DQ6T/T_CA_2
IO_8A/FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTN/DIFFIO_TX_T44N/DQ6T/T_CA_3
IO_8A/CLK8P,FPLL_TL_FBP/DIFFIO_RX_T49P L8IO_8A/CLK8N,FPLL_TL_FBN/DIFFIO_RX_T49N K9U20
MSEL Settings : MSEL[4:0] = 10010 Active serial (AS)(x1 and x4),
no compression, no security, fast POR
FPGA
HSMC
SD_DAT0SD_DAT1SD_DAT2SD_DAT3SD_CMD SD_CLK MSEL0MSEL1MSEL3MSEL2MSEL4
BST_TDI BST_TDO JTAG_FPGA_TDI FPGA_CONF_DONE FPGA_nSTATUS FPGA_nCONFIG
HSMC_JTAG_TDI HSMC_JTAG_TDO JTAG_FPGA_TDO FPGA_nCE
GPIO34
GPIO11GPIO23GPIO22
GPIO21GPIO20GPIO19
GPIO17GPIO15GPIO14GPIO13
GPIO12GPIO31VCC3P3
VCC3P3
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
R1730DNI R520R1770DNI RN2210K
1234
5
678Bank 9A
5CGXFC5C6F27C7N
IO_3A/DATA6/DIFFIO_RX_B1N/DQ1B T7IO_3A/DATA5/DIFFIO_TX_B2N
U7IO_3A/DATA8/DIFFIO_RX_B1P/DQ1B T8IO_3A/DATA7/DIFFIO_TX_B2P/DQ1B V8IO_3A/DATA10/DIFFIO_RX_B3N/DQSN1B W8IO_3A/DATA9/DIFFIO_TX_B4N/DQ1B
AB6IO_3A/DATA12/DIFFIO_RX_B3P/DQS1B Y9IO_3A/DATA11/DIFFIO_TX_B4P
AA6IO_3A/DATA14/DIFFIO_RX_B5N/DQ1B R10IO_3A/DATA13/DIFFIO_TX_B6N/DQ1B AA7IO_3A/CLKUSR/DIFFIO_RX_B5P/DQ1B R9IO_3A/DATA15/DIFFIO_TX_B6P/DQ1B Y8IO_5A/PR_REQUEST/DIFFIO_TX_R1N/DQ1R
AC23
IO_5A/CVP_CONFDONE/DIFFIO_TX_R3N/DQ1R
AA23IO_5A/nPERSTL1/DIFFIO_RX_R6N/DQSN1R U22MSEL0M7CONF_DONE A6MSEL1L6nSTATUS B5nCE
D5
MSEL2A2MSEL3K5nCONFIG F5MSEL4
J5
IO_3A/PR_DONE/DIFFIO_RX_B7N
R8
IO_3A/PR_READY/DIFFIO_TX_B8N/DQ1B
AD6IO_3A/PR_ERROR/DIFFIO_RX_B7P P8IO_3A/DIFFIO_TX_B8P/DQ1B
AD7
R530
VCCAUX_VCCA_FPLL
VCC2P5
VCC3P3
VREF_3P3_VCCIO
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
5CGXFC5C6F27C7N
VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPGM AA9
VCCPGM W22VCCPGM F8VCCBAT
VCCPD5B R21VCCPD6A J22VCCPD6A L21VCCPD7A8A
F19VCCPD7A8A F17VCCPD7A8A F13VCCPD7A8A F11VCCPD7A8A F9VCCA_FPLL W7VCCA_FPLL J6VCCA_FPLL
Y21
VCCA_FPLL G21VCC_AUX G9VCC_AUX E14VCC_AUX G19VCC_AUX
AB20VCC_AUX AB14VCC_AUX AA85CGXFC5C6F27C7N
VCCIO4A U18VCCIO4A AE22VCCIO4A AA20VCCIO4A AD19VCCIO4A Y17VCCIO4A W14VCCIO4A AC16VCCIO4A AF15VCCIO4A AB13VCCIO4A AE12VCCIO5A V21VCCIO5A AB23VCCIO5B N26VCCIO5B T25VCCIO5B W24VCCIO5B R22VREFB4AN0AD15VREFB5AN0W23VREFB5BN0
P25
CYCLONE V GX XCVR Power
U14-12
2.5V
2.5V
for VCCIO_VCCPD 2.5V
for VCCIO_VCCPD 3.3V
for VCCIO 1.2V
VCCH_GXBL VCCAUX_VCCA_FPLL
VCC1P2
VCC3P3
VCC2P5
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
C2204.7n 50V
C25522n 16V
C1674.7u 6.3V
C2510.01u 50V
C1830.01u 50V
C2320.47u 10V
C1804.7n 50V
C1782.2n 50V
C1940.01u 50V
C1701u 10V
C1720.47u 10V
C2504.7n 50V
C1764.7u 6.3V
C10510u 6.3V
C2492.2n 50V
C1910.01u 50V
C1044.7u 6.3V
C1820.1u 10V
C2460.01u 50V
C1900.1u 10V
C25322n 16V
C1851u 10V
C2590.1u 10V
C2130.01u 50V
C25247n 25V
Note:
Place decoupling caps near LPDDR2 power pins place close to DDR2 chip
DDR2LP_CKE0DDR2LP_CS_n0DDR2LP_DM0DDR2LP_DM1DDR2LP_DQ2DDR2LP_DQ3DDR2LP_DQ4DDR2LP_DQ5DDR2LP_DQ6DDR2LP_DQ7DDR2LP_DQ8DDR2LP_DQ9DDR2LP_DQ10DDR2LP_DQ11DDR2LP_DQ12DDR2LP_DQ13DDR2LP_DQ14DDR2LP_DQ15DDR2LP_DM3
DDR2LP_DQ31
DDR2LP_DQ24DDR2LP_DQ25DDR2LP_DQ26DDR2LP_DQ27DDR2LP_DQ28DDR2LP_DQ29DDR2LP_DQ30DDR2LP_DM2DDR2LP_DQ16DDR2LP_DQ17DDR2LP_DQ19DDR2LP_DQ18DDR2LP_DQ20DDR2LP_DQ22DDR2LP_DQ21DDR2LP_DQ23DDR2LP_ZQ0DDR2LP_ZQ1
DDR2LP_CKE1DDR2LP_CS_n1DDR2LP_CK_n
VCC1P2
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
C1450.1u 10V
240DNI
C1580.1u 10V
R169 4.7K R168
4.7K DNI
C15510u 10V
DNU0A1DNU1A2NC0A3NC1A4NC2A5NC3A6NC4A7NC5A8NC6A9NC7A10DNU2A22DNU3A23DM2AB20DNU10AB22DNU8AB1DNU9AB2CS#0AB3CS#1AB4NC/ZQ AC11CKE0AC3CKE1AC4DNU4B1DNU5B2DM3B20DNU6B22DNU7B23NC8B4NC9B6NC10B7NC11B9NC12D1NC13D2NC14E1NC15E2NC16F1NC17G1NC18G2NC19H1NC20H2NC21J1NC22K1NC23K2NC24L1DM1L23DM0N23ZQ P1DQ30A13DQ29A14DQ26A16DQ25A17DQ16AB12DQ18AB14DQ20AB15DQ22AB17DQ17AC13DQ19AC14DQ21AC16DQ23AC17DQ31B12DQ28B14DQ27B15DQ24B17DQ15C22DQ14D23DQ12E22DQ13E23DQ11F22DQ10G23DQ8H22DQ9H23DQ6T22DQ7T23DQ5U22DQ4V23DQ2W22DQ3W23240C4010u 10V
C14622n 16V
MT42L128M32D1LF-25WT
VSS A21VSS AA1VDD2AA2VDD2AB10VSS AB11VDD2
AB21
VSS AC21VSS AC5VSS/NC AC9VSS B10VDD2B21VSS/NC B5VSS/NC B8VSS C1VDD2C2VSS/NC F2VSS/NC
J2
VDD2L22VSS M2VSS M23VSS R1VDD2R2VSSQ A12VSSQ A15VSSQ A18VDDQ AA22VDDQ AB13VDDQ AB16VDDQ AB19VSSCA AB7VSSQ AC12VSSQ AC15VSSQ
AC18
VSSQ C23VDDQ D22VSSQ F23VDDQ G22VSSQ J23VDDQ K22VSSQ P23VDDQ R22VSSQ U23VSSCA V1VDDQ V22VSSQ Y23C1594.7u 6.3V
C16222n 16V
C1530.1u 10V
SD_DAT1SD_DAT0SD_DAT3SD_DAT2SD_CMD
SD_DAT2SD_DAT3SD_CMD SRAM_CE_n SRAM_OE_n SRAM_WE_n SRAM_LB_n SRAM_UB_n
SRAM_D11SRAM_D12SRAM_D15
SRAM_D13SRAM_D9SRAM_D10SRAM_D14SRAM_CE_n
SRAM_A14SRAM_A16SRAM_A15SRAM_A17SRAM_A13VCC3P3_SD
VCC3P3_SD
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
R185RN1010K 12345678L2130ohm, 3A
SRAM 256Kx16
nCE 6G N D 12nWE 17A1326A1427A1828D930D1031D1132G N D
34
D1235D1336D1437D15
38nLB 39nUB
40
nOE 41A1542A1643A1744123J6c k e t
DAT3CMD DAT2R117
10K
Default :
I2C Address 0x34/35
AUD_XCK
AUD_BCLK
AUD_DACDAT AUD_DACLRCK AUD_ADCDAT
AUD_ADCLRCK I2C_SDA_3P3I2C_SCL_3P3
AUD_MUTE
AUD_CSB
AUD_I2C_SDAT AUD_I2C_SCLK AGND AGND
VCC_AUDD
VCC_AUDD
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
R18
680
R1502K DNI
C22
100u C13410u 6.3V
U7
SSM2603BCLK 7H P V D D 12XTO 2
D C V D D 3MICBIAS
21
MICIN
22RLINEIN 23LLINEIN
24
MUTE
25CSB
26
SDIN
27SCLK
28ROUT 17A V D D
18
A G N D
19
VMID 20
LOUT
16P G N D 15RHPOUT 14LHPOUT
13
XTI/MCLK 1D G N D
4
RECLRC
11RECDAT 10D B V D D
5
CLKOUT
6
PBDAT 8PBLRCK 9E P _G N D 29C1390.1u 10V DNI
R2822R20330R30
22
R1512K DNI
R174.7K
C15
1u 10V
Default :
I2C Address 0x72/0x73
Pull-high to FPGA bank I/O power
Note:
Place Capacitor near ADV7513 DVDD pins
HDMI_TX_CLK HDMI_TX_DE HDMI_TX_VS HDMI_TX_HS HDMI_HPD CEC_CLK
HDMI_SPDIF HDMI_MCLK HDMI_I2S0HDMI_I2S1HDMI_I2S2HDMI_I2S3HDMI_SCLK HDMI_LRCLK
HDMI_TX_D17HDMI_TX_D18HDMI_TX_D19HDMI_TX_D20HDMI_TX_D21HDMI_TX_D22HDMI_TX_D23
CLK_12MHz VCC1P8
VCC1P8_DVDD
VCC1P8
VCC1P8_AVDD
VCC1P8_DVDD
VCC1P8_PVDD
VCC1P8_AVDD
VCC3P3_DVDD VCC3P3_DVDD
VCC1P8_AVDD
VCC1P2
VCC1P8_DVDD
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
C3510u 6.3V
R153
49.9DNI R128
22DNI
R1242K X312MHZ
DNI
VCC 4OUT 3
GND
2
EN
1C1490.1u 10V
L9
10uH
74479887310A
C1520.1u 10V
C1380.1u 10V
R129R125
2K DNI
C1290.1u 10V
DNI
C1300.1u 10V
L4
10uH
R80
R138
887
ADV7513BSWZ
D1743D1842D1941D2040D2139D2238D2337CLK 53DE
63HSYNC 64VSYNC 2R_EXT 14HPD 16SPDIF 3MCLK 4I2S05I2S16I2S27I2S38SCLK 9LRCLK 10PD
22
DVDD_3V 29DVDD11DVDD211DVDD331DVDD451PVDD 12BGVDD 13AVDD115AVDD219AVDD3
25
EPAD_GND
65
R130
R127
TX_n TX_p RX_p RX_n
Default
Jumper Open
HSMC_RX_p5HSMC_RX_n5HSMC_TX_p5HSMC_TX_n5HSMC_CLKIN_p1HSMC_CLKIN_n1
NET_HSMC_GXB_TX_p0NET_HSMC_GXB_TX_n0HSMC_TX_n0HSMC_CLKOUT_n1
HSMC_CLKOUT_p1HSMC_RX_p6HSMC_RX_n6HSMC_TX_n6HSMC_TX_p6HSMC_RX_n1HSMC_RX_p1HSMC_RX_p7HSMC_RX_n7HSMC_TX_p7HSMC_TX_n7
HSMC_TX_p1HSMC_TX_n1HSMC_RX_p2HSMC_RX_n2HSMC_CLKOUT0
HSMC_JTAG_TCK
HSMC_CLKIN0
HSMC_JTAG_TDI HSMC_JTAG_TMS HSMC_JTAG_TDO HSMC_D1HSMC_TX_p2HSMC_TX_n2HSMC_GXB_TX_p0HSMC_GXB_TX_n0
HSMC_D2HSMC_RX_p3HSMC_RX_n3HSMC_RX_p0HSMC_GXB_RX_n0HSMC_GXB_RX_p0HSMC_RX_n0HSMC_TX_n3
HSMC_TX_p3HSMC_D3HSMC_RX_n4HSMC_RX_p4HSMC_TX_p4HSMC_TX_n4HSMC_TX_p0HSMC_D0HSMC_SDA
HSMC_SCL
I2C_SDA I2C_SCL
HSMC_SDA HSMC_SCL
VCC12_HSMC
VCC12_HSMC
VCC3P3_HSMC
VCC3P3_HSMC
VCC12_HSMC
VCC3P3
VCC3P3_HSMC
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
R460C12010u 35V C2650.1u 25V
TP1Dummy Pin
C2660.1u 25V R187
22
R49
JP13
HEADER 2
1
2C11510u 6.3V C24822u 25V 1164
168
165
1661672929313133333535373739
39
3030323234343636383840
40
41414343454547474949515153535555575759596161636365656767696971717373757577777979818183838585878789899191939395959797999942424444464648485050525254545656585860606262646466666868707072727474767678788080828284848686888890909292949496969898100100161161162162163163164
164R18622XJ1
Jumper-2.54mm
VREF ADC_IN1ADC_IN2ADC_IN3ADC_IN5ADC_IN6ADC_IN7ADC_IN0ADC_IN4ex_ADC_SDO ADC_VREF
ADC_REFCOMP ex_ADC_CONVST ex_ADC_SDI
ex_ADC_SCK Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
C7810u 10V C800.1u 10V
CH0
CH1CH2CH3
CH4CH5CH6
CH7COM
G N D
G N D G N D
G N D
G N D G N D
VREF
REFCOMP SDI
SCK
SDO
CONV
D V D D
O V D D
A V D D 1A V D D 1
U17
LTC2308CUF
22232412345
6
25
91011
20
18
7
8
15
16
1714
12
1319
21
C1021n 50V
C981n 50V C8210u 10V
C991n 50V C1001n 50V TP13
TP_YELLOW
C790.1u 10V
R8649.9
C872.2u 10V
C1011n 50V C840.1u 10V
GPIO_D0GPIO_D2GPIO_D4GPIO_D6GPIO_D8GPIO_D1GPIO_D3GPIO_D5GPIO_D7GPIO_D9GPIO_D14GPIO_D12GPIO_D10GPIO_D18GPIO_D16GPIO_D22GPIO_D20GPIO_D24GPIO_D15GPIO_D13GPIO_D11GPIO_D19GPIO_D17GPIO_D23GPIO_D21GPIO_D25GPIO_D26GPIO_D28GPIO_D30GPIO_D32GPIO_D34
GPIO_D33GPIO_D31GPIO_D29GPIO_D27GPIO_D35
GPIO_D7
GPIO_D11GPIO_D15GPIO_D19GPIO_D23GPIO_D27GPIO3GPIO20GPIO_D20Arduino_IO0CPU_RESET_n Arduino_Reset_n
Analog_In1Analog_In2Analog_In3
Arduino_Reset_n
Analog_In0Arduino_AD4_IO14Arduino_AD5_IO15
Analog_In6
Analog_In7
Arduino_IO11
Arduino_IO12Arduino_IO13Arduino_Reset_n
Arduino_IO15
Arduino_IO14GND
VCC5VCC12
VCC3P3VCC3P3
VCC5
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
BAT54S D15BAT54S
1
2
3
JP14HEADER 2x3
12345
6
D38BAT54S
1
2
3
BAT54S D13BAT54S
1
2
3
R22222R2242.2K DNI
RN4
18BAT54S BAT54S RN11
18BAT54S D45BAT54S
1
2
3
BAT54S 3
BAT54S R2252.2K DNI
D43BAT54S
1
2
3
JP9
BOX Header 2X20M 12345678910111312141618202224262715171921232528293133353739
303234363840
Reserved 6x6mm tact switch
SW1SW0SW2SW3
BTN3
BTN1BTN2BTN0VCC1P2
VCC1P2
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
RN2318BUTTON1
TACT SW DNI
432
1
SW0
SLIDE SW
12345
BUTTON3
TACT SW DNI
432
1
SW2
SLIDE SW
12345
SW1
SLIDE SW
12345
RN31
1RN2610K
1234
5
678BUTTON2
TACT SW DNI
432
1
RN24
120
1
2345678
B2A2E1G0
F0E0B1C1D1F1G1
C0B0A0D0A1C2D2E2F2HEX0_D0HEX0_D1HEX0_D2HEX0_D3
HEX0_D4HEX0_D5HEX0_D6HEX1_D0
HEX1_D1HEX1_D3HEX1_D4
HEX1_D2HEX1_D5HEX1_D6HEX2_D0HEX2_D1
HEX2_D2HEX2_D3HEX2_D4HEX2_D5
GPIO22GPIO23GPIO24GPIO25GPIO26GPIO27GPIO28GPIO30GPIO29HEX2_D0HEX3_D0HEX2_D1HEX3_D1HEX2_D2HEX2_D3HEX2_D4HEX2_D5HEX2_D6LEDR0LEDG1LEDG2LEDG3
LEDG4LEDG5LEDG6LEDG7
LEDR1LEDR2LEDR3
LEDR4LEDR5LEDR6LEDR7VCC_HEX2
VCC_HEX
VCC_HEX
VCC_HEX2
VCC_HEX
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
e d dp
c g b f a CA1CA2
HEX0
7Segment Display
123456
10987
ON
1
S2
121615RN18680
1
2345678e d c b f a CA1CA2
HEX2
12456
1098RN16680
1
2345678RN1568012345678
ON
1
S1
SW DIP-812345678
161514131211109
RN1912345678
e d dp
c g b f a CA1CA2
HEX1
7Segment Display
123456
10987
R2010
R20510k
RN1768012345678
Self Powered and Internal OSC
USB to UART
UART_CTS
RX_LED
TX_LED
UART_RTS
FT232_DP FT232_DM UART_RX UART_TX UART_RESET_n
UART_RXLED UART_TXLED UART_CTS UART_RTS
UART_CTS
UART_RTS
UART_PW_EN
VCC5_UART
VCC3P3_UART
VCC5_UART
VCC5_USB_UART
VCCIO_UART VCC2P5
VCC5
Title
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
DNI
TP_YELLOW
U4FT232R VCC
19VCCIO 1G N D 4RESET 183V3OUT
16USBDP 14USBDM
15TXD 30RXD 2CTS#8RTS#32DSR#6DTR#31DCD#7RI#3CBUS022NC15A G N D 24NC212NC313NC525NC629NC423OSCI 27OSCO 28
G N D 17G N D 20TEST
26
CBUS121CBUS311CBUS210CBUS4
9
E P _G N D
33
R71M R143
10k
C140.1u 25V
TPD2E001DRLR
U2VCC 1NC
2IO1
3
GND
4
IO2
5
D9LEDR
2
1
R220DNI
C314.7u 6.3V
L24
321R142 4.7K C6
0.1u 25V
R23
R15733C330.1u 25V
C80.1u 25V DNI
TP_YELLOW
D8LEDG
21
R156
33
C254.7u 6.3V
C270.1u 25V
L2230ohm, 3A
10k
C184.7u 6.3V
设计题目:STC89C51单片机学习电路板设计 题目性质:一般设计 指导教师:[04054]吕青 毕业设计(论文)要求及原始数据(资料) 1.课题简介: STC89C51系列单片机具有功能强、价格低的特点,是51系列单片机最好的替代机型。本题目就是为入门该系列单片机设计一个学习电路板,满足学习该型号单片机的需求。 该学习电路板用于C8051F330单片机的学习。该板具有RS232接口、数码管、发光二极管显示、键盘、模拟量输入、蜂鸣器和具有扩展实验接口。设计原则是简单实用。 2.技术参数 1)使用美国Silabs公司STC89C51单片机 2)具有1个RS232接口 3)具有8个数码管(HC595驱动) 4)具有4个按钮 5)具有1路模拟量电压输入 6)ISP下载接口与下载电缆电路 7)具有蜂鸣器与驱动电路 8)供电:AC220V 9)具有8个LED 10)具有功率接口(具有AC220V,1A驱动能力) 11)具有D/A输出 毕业设计(论文)主要工作内容 主要内容 1)了解市场上的各种单片机学习板,制定设计方案。 2)学习STC89C51单片机的数据手册 3)学习STC89C51 单片机的相关参考书 4)学习PROTEL软件 5)学习板原理图设计 6)电路板(PCB)设计 7)调试电路板 8)熟悉STC89C51 单片机的C编译器与编程软件 9)编写C语言的电路板测试程序 10)编写学习使用说明 学生应交出的设计文件(论文) 1论文。要求内容准确,叙述清晰流畅,图文详尽,正文不少于60页,不得有错别字,并符合学校对论文的各项要求。主要内容包括: 1)学习板总体设计概述; 2)学习板结构设计说明(包括总体结构总框图); 3)学习板原理图设计说明(包括硬件电路原理图,用Protel98se画); 4)学习板硬件电路板设计说明(包括PCB板图); 5)学习板软件程序设计说明(包括程序流程图和源程序清单及注释); 6)学习板主要示例子程序设计说明(包括程序流程图和源程序清单及注释); 7)设计难点和遗留问题(包括设计中遇到的难题和解决方法,以及尚未解决的问题和解决的思路);
基于STC89C52单片机的电子密码锁 学生姓名: xx 学生学号: xxxxx 院(系):电气信息工程学院 年级专业: 2010级电子信息工程2班 指导教师:陶文英 二〇一三年六月 摘要
随着人们生活水平的提高,如何实现家庭防盗这一问题也变的尤其的突出,传统的机械锁由于其构造的简单,被撬的事情屡见不鲜,电子密码锁具有安全性能高,成本低,功耗低,操作简单等优点使其作为防盗卫士的角色越来越重要。 从经济实用角度出发,采用51系列单片机,设计一款可更改密码,LCD1602显示,具有报警功能,该电子密码锁体积小,易于开发,成本较低,安全性高,能将其存储的现场历史数据及时上报给上位机系统,实现网络实时监控,方便管理人员及时分析和处理数据。其性能和安全性已大大超过了机械锁,特点有保密性好,编码量多,远远大于弹子锁,随机开锁成功率几乎为零;密码可变,用户可以经常更改密码,防止密码被盗,同时也可以避免因人员的更替而使锁的密级下降;误码输入保护。当输入密码多次错误时,报警系统自动启动;电子密码锁操作简单易行,受到广大用户的亲睐。 关键词单片机, 密码锁, 更改密码, LCD1602 目录
错误!未定义书签。 1 绪论 1.1电子密码锁简介 (1) 1.2 电子密码锁的发展趋势 (1) 2 设计方案 (3) 3 主要元器件 (4) 3.1 主控芯片STC89C52 (4) 3.2 晶体振荡器 (8) 3.3 LCD显示密码模块的设计 (9) 3.3.1 LCD1602简介 (9) 3.3.2 LCD1602液晶显示模块与单片机连接电路 (11) 4 硬件系统设计 (12) 4.1 设计原理 (12) 4.2 电源输入电路 (12) 4.3 矩阵键盘 (13) 4.4 复位电路 (14) 4.5 晶振电路 (14) 4.6 报警电路 (15) 4.7 显示电路 (15) 4.8 开锁电路 (16) 4.9 电路总体构成 (16) 5 软件程序设计 (18) 5.1 主程序流程介绍 (18) 5.2 键盘模块流程图 (19) 5.3 显示模块流程图 (21) 5.4 修改密码流程图 (22) 5.5 开锁和报警模块流程图 (23) 6 电子密码锁的系统调试及仿真 (25) 6.1硬件电路调试及结果分析 (25) 6.2软件调试及功能分析 (25) 6.2.1调试过程 (25) 6.2.2 仿真结果分 (26)
自循迹小车 第一章引言 1.1 设计目的 通过设计进一步掌握51单片机的应用,特别是在嵌入式系统中的应用。进一步学习51单片机在系统中的控制功能,能够合理设计单片机的外围电路,并使之与单片机构成整个系统。 1.2 设计方案介绍 该智能车采用红外对管方案进行道路检测,单片机根据采集到的红外对管的不同状态判断小车当前状态,通过pid控制发出控制命令,控电机的工作状态以实现对小车姿态的控制。 1.3 技术报告内容安排 本技术报告主要分为三个部分。第一部分是对整个系统实现方法的一个概要说明,主要内容是对整个技术方案的概述;第二部分是对硬件电路设计的说明,主要介绍系统传感器的设计及其他硬件电路的设计原理等;第三部分是对系统软件设计部分的说明,主要内容是智能模型车设计中主要用到的控制理论、算法说明及代码设计介绍等。
第二章技术方案概要说明 本模型车的电路系统包括电源管理模块、单片机模块、传感器模块、电机驱动模块. 在整个系统中,由电源管理模块实现对其他各模块的电源管理。其中,对单片机、光电管提供5V电压,对电机提供6V电压 路径识别电路由3对光电发送与接收管组成。由于路面存在黑色引导线,落在黑线区域内的光电接收管接收到反射的光线的强度与白色的路面不同,进而在光电接收管两端产生不同的电压值,由此判断路线的走向。传感器模块将当前采集到的一组电压值传递给单片机,进而根据一定得算法对舵机进行控制,使小车自动寻线行走。 单片机模块是智能车的核心部分,主要完成对外围各个模块的管理,实现对外围模块的信号发送,以及对传感器模块的信号采集,并根据软件算法对所采集的信号进行处理,发送信号给执行模块进行任务执行,还对各种突发事件进行监控和处理,保证整个系统的正常运作。 电机驱动采用L293驱动芯片,该芯片支持2路电机驱动同时支持PWM 调速
3.1 STC89C51单片机的介绍 STC系列单片机是美国STC公司最新推出的一种新型51内核的单片机。片内含有Flash 程序存储器、SRAM、UART、SPI、A\D、PWM等模块。该器件的基本功能与普通的51单片机完全兼容。 3.1.1主要功能、性能参数 1.内置标准51内核,机器周期:增强型为6时钟,普通型为12时钟; 2.工作频率范围:0~40MHZ,相当于普通8051的0~80MHZ; 3.STC89C5xRC对应Flash空间:4KB\8KB\15KB; 4.内部存储器(RAM):512B; 5.定时器\计数器:3个16位; 6.通用异步通信口(UART)1个; 7.中断源:8个; 8.有ISP(在系统可编程)\IAP(在应用可编程),无需专用编程器\仿真器; 9.通用I\O口:32\36个; 10.工作电压:3.8~5.5V; 11.外形封装:40脚PDIP、44脚PLCC和PQFP等 3.1.2 89C51单片机的引脚功能说明 (1)VCC:电源电压 (2)GND:地 (3)P0口:P0口是一组8位漏极开路型双向I/O口,也即地址/数据总线复用口。作为输出口用时,每位能吸收电流的方式驱动8个TTL逻辑门电路,对端口P0写“1”时可作为高阻抗输入端用。 在访问外部数据存储器或程序存储器时,这组口线分时转换地址(低8位)和数据总线复位,在访问期间激活内部上拉电阻。 (4)P1口:P1是一个带内部上拉电阻的8位双向I/O口,P1的输出缓冲级可驱动(吸收或输出电流)4个TTE逻辑门电路。对端口写“1”,通过内部的上拉电阻把端口拉到高电平,此时可作输入口。作输入口使用时,因为内部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(ILL)。 与A T89C51不同之处是,P1.0和P1.1还可分别作为定时/计数器2的外部计数输入(P 1.0/T2)和输入(P 1.1/T2EX ),参见表4-1。
目录 1绪论 ............................................................................................ 错误!未定义书签。 本设计的研究背景与研究目的............................................. 错误!未定义书签。 国内外研究现状..................................................................... 错误!未定义书签。2电子密码锁的总体设计方案 .................................................... 错误!未定义书签。 方案论证................................................................................. 错误!未定义书签。 方案一采用单片机控制方案.......................................... 错误!未定义书签。 方案二采用数字电路控制方案...................................... 错误!未定义书签。 方案三采用EDA控制方案............................................. 错误!未定义书签。 方案比较以及可行性............................................................. 错误!未定义书签。3电子密码锁硬件电路的设计 .................................................... 错误!未定义书签。 中央控制模块的设计............................................................. 错误!未定义书签。 主控芯片STC89C52单片机的简介 ............................... 错误!未定义书签。 时钟电路的设计.............................................................. 错误!未定义书签。 复位电路的设计.............................................................. 错误!未定义书签。 键盘输入模块的设计............................................................. 错误!未定义书签。 矩阵键盘工作原理.......................................................... 错误!未定义书签。 单片机键盘扫描法.......................................................... 错误!未定义书签。 显示密码模块的设计............................................................. 错误!未定义书签。 简介.................................................................................. 错误!未定义书签。 液晶显示模块与单片机连接电路.................................. 错误!未定义书签。 开锁模块的设计..................................................................... 错误!未定义书签。 报警模块的设计..................................................................... 错误!未定义书签。 硬件电路总体设计................................................................. 错误!未定义书签。4电子密码锁的软件设计 ............................................................ 错误!未定义书签。 主程序流程介绍..................................................................... 错误!未定义书签。 键盘模块流程图..................................................................... 错误!未定义书签。 显示模块流程图..................................................................... 错误!未定义书签。 修改密码流程图..................................................................... 错误!未定义书签。 开锁和报警模块流程图......................................................... 错误!未定义书签。5电子密码锁的系统调试及分析 ................................................ 错误!未定义书签。
基于STC89C52单片机的电子密码锁完整版附仿真图原理图
目录 1绪论 (1) 1.1本设计的研究背景与研究目的 (1) 1.2国内外研究现状 (2) 2电子密码锁的总体设计方案 (3) 2.1方案论证 (3) 2.1.1方案一采用单片机控制方案 (3) 2.1.2方案二采用数字电路控制方案 (4) 2.1.3方案三采用EDA控制方案 (5) 2.2方案比较以及可行性 (5) 3电子密码锁硬件电路的设计 (6) 3.1中央控制模块的设计 (6) 3.1.1主控芯片STC89C52单片机的简介 (6) 3.1.2时钟电路的设计 (7) 3.1.3复位电路的设计 (8) 3.2键盘输入模块的设计 (9) 3.2.1矩阵键盘工作原理 (9) 3.2.2单片机键盘扫描法 (10) 3.3LCD显示密码模块的设计 (10) 3.3.1LCD1602简介 (11) 3.3.2LCD1602液晶显示模块与单片机连接电路 (12) 3.4开锁模块的设计 (13) 3.5报警模块的设计 (13) 3.6硬件电路总体设计 (14) 4电子密码锁的软件设计 (15) 4.1主程序流程介绍 (15) 4.2键盘模块流程图 (16) 4.3显示模块流程图 (18) 4.4修改密码流程图 (19) 4.5开锁和报警模块流程图 (20) 5电子密码锁的系统调试及分析 (22)
5.1硬件电路调试及结果分析 (22) 5.2软件调试及功能分析 (22) 5.2.1调试过程 (22) 5.2.2仿真结果分析 (24) 5.3系统调试 (26) 6结论及展望 (28) 6.1结论 (28) 6.2展望 (28) 谢辞 (29) 参考文献 (30) 附录 (32) 附1部分代码 (32) 附2总电路图 (40)
1.系统概述 89C51单片机学习板是一款基于8位单片机处理芯片STC89C52RC的系统。其功能强大,可以实现单片机开发的多种要求,学习、开发者可以根据需要选配多种常用模块,达到实验及教学的目的。 89C51单片机学习板功能强大,具有报警,跑马灯、串行通信(max232)、段码液晶(msm0801LCD)和字符液晶显示(LCD1602)、电机控制(L298)、A/D转换(TLC2543)、D/A 转换(TLC5615)、温度采集(DS1602)、数字信号合成(AD9851)、实时时钟电路(DS1302)、4—20mA输出、PWM输出(UC3842)、红外检测(KSM-603LM)控制等十七种功能,供学习者学习开发使用。89C51-III单片机学习板采用的芯片都是常用芯片,使学习者对常用电子产品进一步学习理解。 2.系统原理 2.1系统组成 2.2主CPU电路 主CPU电路选用STC89C52RC系列单片机,STC89C52RC是采用8051核的ISP(In System Programming)在系统可编程芯片,最高工作时钟频率为80MHz,片内含8K Bytes 的可反复擦写1000次的Flash只读程序存储器,器件兼容标准MCS-51指令系统及80C51引脚结构,芯片内集成了通用8位中央处理器和ISP Flash存储单元,具有在系统可编程(ISP)特性,配
合PC端的控制程序即可将用户的程序代码下载进单片机内部,省去了购买通用编程器,而且速度更快。 STC89C52RC系列单片机是单时钟/ 机器周期(1T)的兼容8051 内核单片机,是高速/ 低功耗的新一代8051 单片机,全新的流水线/ 精简指令集结构,内部集成MAX810 专用复位电路。 STC89C51系列单片机的特点: (1)增强型1T 流水线/ 精简指令集结构8051 CPU (2)工作电压:3.4V-5.5V (5V 单片机)/ 2.0V-3.8V (3V 单片机) (3)工作频率范围:0 -35 MHz,相当于普通8051 的0~420MHz.实际工作频率可达48MHz. (4)用户应用程序空间12K / 10K / 8K / 6K / 4K / 2K 字节 (5)片上集成512 字节RAM (6)通用I/O 口(27/23个),复位后为:准双向口/ 弱上拉(普通8051 传统I/O 口) 可设置成四种模式:准双向口/ 弱上拉,推挽/ 强上拉,仅为输入/ 高阻,开漏 每个I/O 口驱动能力均可达到20mA,但整个芯片最大不得超过55mA (7)ISP(在系统可编程)/IAP(在应用可编程),无需专用编程器 可通过串口(P3.0/P3.1)直接下载用户程序,数秒即可完成一片 (8)EEPROM 功能 (9)看门狗 (10)内部集成MAX810 专用复位电路(外部晶体20M 以下时,可省外部复位电路) (11)时钟源:外部高精度晶体/ 时钟,内部R/C 振荡器。用户在下载用户程序时,可选择是使用内部R/C 振荡器还是外部晶体/ 时钟。常温下内部R/C 振荡器频率为:5.2MHz ~6.8MHz。精度要求不高时,可选择使用内部时钟,因为有温漂,请选4MHz ~8MHz (12)有2个16 位定时器/ 计数器 (13)外部中断2 路,下降沿中断或低电平触发中断,Power Down 模式可由外部中断低电平触发中断方式唤醒 (14)PWM( 4 路)/ P C A(可编程计数器阵列),也可用来再实现4个定时器或4个外部中断(上升沿中断/ 下降沿中断均可支持) (15)STC89Cc516AD具有ADC功能。10 位精度ADC,共8 路 (16)通用异步串行口(UART) (17)SPI 同步通信口,主模式/ 从模式 (18)工作温度范围:0 -75℃/ -40 -+85℃ (19)封装:PDIP-28,SOP-28,PDIP-20,SOP-20,PLCC-32,TSSOP-20(超小封状,定货) STC89C52RC系列单片机为真正的看门狗,缺省为关闭(冷启动),启动后无法关闭,可省去外部看门狗。此系列单片机P4口地址为E8H,并有2个附加外部中断, P4.2/INT3,P4.3/INT2。 晶振电路部分,使用11.0592M晶体,和20PF的电容。 在复位电路中,采用阻容复位时,电容为10uF,电阻为10k;晶振及复位电路如图2.1。因为STC89C52RC系列单片机RESET脚内部没有下拉电阻,必须接10k电阻。