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CD4510BMS中文资料

CD4510BMS, CD4516BMS

CMOS Presettable Up/Down Counters

CD4510BMS Presettable BCD Up/Down Counter and the CD4516BMS Presettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T -type flip-flop capability)connected as counters.These counters can be cleared by a high level on the RESET line,and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line.The CD4510BMS will count out of non-BCD counter states in a maximum of two clock pulses in the up mode,and a maximum of four clock pulses in the down mode.If the CARRY IN input is held low,the counter advances up or down on each positive-going clock transition.Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY OUT of a less significant stage to the CARRY IN of a more significant stage.

The CD4510BMS and CD4516BMS can be cascaded in the ripple mode by connecting the CARRY OUT to the clock of the next stage.If the UP/DOWN input changes during a ter-minal count,the CARRY OUT must be gated with the clock,and the UP/DOWN input must change while the clock is high.This method provides a clean clock signal to the sub-sequent counting stage. (See Figures 13, 14.)

These devices are similar to types MC14510 and MC14516.The CD4510BMS and CD4516BMS are supplied in these 16-lead outline packages:Features

?High Voltage Types (20V Rating)?CD4510BMS - BCD Type ?CD4516BMS - Binary Type ?Medium Speed Operation -fCL = 8MHz Typ. at 10V

?Synchronous Internal Carry Propagation ?Reset and Preset Capability

?100% Tested for Quiescent Current at 20V ?5V, 10V and 15V Parametric Ratings

?Standardized Symmetrical Output Characteristics ?Maximum Input Current of 1μA at 18V Over Full Pack-age Temperature Range; 100nA at 18V and +25o C ?Noise Margin (Over Full Package/Temperature Range)-1V at VDD = 5V -2V at VDD = 10V - 2.5V at VDD = 15V ?Meets All Requirements of JEDEC Tentative Standard No.13B,“Standard Speci?cations for Description of ‘B’ Series CMOS Devices”

Applications

?Up/Down Difference Counting ?Multistage Synchronous Counting ?Multistage Ripple Counting ?Synchronous Frequency Dividers

Pinout

CD4510BMS, CD4516BMS

TOP VIEW

Functional Diagram

Braze Seal DIP *H4W ?H45Frit Seal DIP

*FBF ?H1F Ceramic Flatpack H6W

*CD4510B Only

?CD4516B Only

14151691312111012345768

PRESET ENABLE

Q4P4P1

CARRY IN

VSS

CARRY OUT

VDD Q3P3P2Q2UP/DOWN RESET

CLOCK Q1Q2Q3Q4

611142

P1P2P3P4

412133

CARRY OUT

CARRY IN

RESET

CLOCK UP/DOWN 1015PRESET ENABLE

VDD = 16VSS = 8

Data Sheet

December 1992

File Number

3338

元器件交易网https://www.wendangku.net/doc/665463393.html,

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD). . . . . . . . . . . . . . . .-0.5V to +20V (Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . .-55o C to +125o C Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . .-65o C to +150o C Lead T emperature (During Soldering) . . . . . . . . . . . . . . . . .+265o C At Distance1/16±1/32Inch(1.59mm±0.79mm)from case for 10s Maximum Thermal Resistance. . . . . . . . . . . . . . . .θjaθjc Ceramic DIP and FRIT Package . . . .80o C/W20o C/W Flatpack Package. . . . . . . . . . . . . . . .70o C/W20o C/W Maximum Package Power Dissipation (PD) at +125o C

For T A = -55o C to +100o C (Package Type D, F, K) . . . . . .500mW For T A = +100o C to +125o C (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/o C to 200mW Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW For T A = Full Package Temperature Range (All Package Types) Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175o C

TABLE1.DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS(NOTE 1)

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITS

MIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND1+25o C-10μA

2+125o C-1000μA

VDD = 18V, VIN = VDD or GND3-55o C-10μA Input Leakage Current IIL VIN = VDD or GND VDD = 201+25o C-100-nA

2+125o C-1000-nA

VDD = 18V3-55o C-100-nA Input Leakage Current IIH VIN = VDD or GND VDD = 201+25o C-100nA

2+125o C-1000nA

VDD = 18V3-55o C-100nA Output Voltage VOL15VDD = 15V, No Load1, 2, 3+25o C, +125o C, -55o C-50mV Output Voltage VOH15VDD = 15V, No Load (Note 3)1, 2, 3+25o C, +125o C, -55o C14.95-V Output Current (Sink)IOL5VDD = 5V, VOUT = 0.4V1+25o C0.53-mA Output Current (Sink)IOL10VDD = 10V, VOUT = 0.5V1+25o C 1.4-mA Output Current (Sink)IOL15VDD = 15V, VOUT = 1.5V1+25o C 3.5-mA Output Current (Source)IOH5A VDD = 5V, VOUT = 4.6V1+25o C--0.53mA Output Current (Source)IOH5B VDD = 5V, VOUT = 2.5V1+25o C--1.8mA Output Current (Source)IOH10VDD = 10V, VOUT = 9.5V1+25o C--1.4mA Output Current (Source)IOH15VDD = 15V, VOUT = 13.5V1+25o C--3.5mA N Threshold Voltage VNTH VDD = 10V, ISS = -10μA1+25o C-2.8-0.7V P Threshold Voltage VPTH VSS = 0V, IDD = 10μA1+25o C0.7 2.8V

Functional F VDD = 2.8V, VIN = VDD or GND7+25o C VOH>

VDD/2VOL <

VDD/2

VDD = 20V, VIN = VDD or GND7+25o C

VDD = 18V, VIN = VDD or GND8A+125o C

VDD = 3V, VIN = VDD or GND8B-55o C

Input Voltage Low

(Note 2)

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V1, 2, 3+25o C, +125o C, -55o C- 1.5V

Input Voltage High

(Note 2)

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V1, 2, 3+25o C, +125o C, -55o C 3.5-V

Input Voltage Low (Note 2)VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3+25o C, +125o C, -55o C-4V

Input Voltage High (Note 2)VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3+25o C, +125o C, -55o C11-V

NOTES: 1.All voltages referenced to device GND,100%testing being im-plemented.

2.Go/No Go test with limits applied to inputs.

3.For accuracy,voltage is measured differentially to VDD.Limit is

0.050V max.

TABLE2.AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS(NOTE 1, 2)

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITS

MIN MAX

Propagation Delay Clock to Q Output TPHL1

TPLH1

VDD = 5V, VIN = VDD or GND9+25o C-400ns

10, 11+125o C, -55o C-540ns

Propagation Delay Preset or Reset to Q TPHL2

TPLH2

VDD = 5V, VIN = VDD or GND9+25o C-420ns

10, 11+125o C, -55o C-567ns

Propagation Delay Clock to Carry Out TPHL3

TPLH3

VDD = 5V, VIN = VDD or GND9+25o C-480ns

10, 11+125o C, -55o C-648ns

Propagation Delay Carry In to Carry Out TPHL4

TPLH4

VDD = 5V, VIN = VDD or GND9+25o C-250ns

10, 11+125o C, -55o C-338ns

Propagation Delay Preset or Reset to Carry Out TPHL5

TPLH5

VDD = 5V, VIN = VDD or GND

(Note 3)

9+25o C-640ns

10, 11+125o C, -55o C-864ns

Transition Time TTHL

TTLH VDD = 5V, VIN = VDD or GND9+25o C-200ns

10, 11+125o C, -55o C-270ns

Maximum Clock Input Fre-quency FCL VDD = 5V, VIN = VDD or GND9+25o C2-MHz

10, 11+125o C, -55o C 1.48-MHz

NOTES:

1.CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2.-55o C and +125o C limits guaranteed, 100% testing being implemented.

3.Reset to Carry Out (TPLH) only.

TABLE3.ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITS MIN MAX

Supply Current IDD VDD = 5V, VIN = VDD or GND1, 2-55o C, +25o C-5μA

+125o C-150μA

VDD = 10V, VIN = VDD or GND1, 2-55o C, +25o C-10μA

+125o C-300μA

VDD = 15V, VIN = VDD or GND1, 2-55o C, +25o C-10μA

+125o C-600μA Output Voltage VOL VDD = 5V, No Load1, 2+25o C, +125o C, -

55o C

-50mV

Output Voltage VOL VDD = 10V, No Load1, 2+25o C, +125o C, -

55o C

-50mV

Output Voltage VOH VDD = 5V, No Load1, 2+25o C, +125o C, -

55o C

4.95-V

Output Voltage VOH VDD = 10V, No Load1, 2+25o C, +125o C, -

55o C

9.95-V Output Current (Sink)IOL5VDD = 5V, VOUT = 0.4V1, 2+125o C0.36-mA

-55o C0.64-mA Output Current (Sink)IOL10VDD = 10V, VOUT = 0.5V1, 2+125o C0.9-mA

-55o C 1.6-mA Output Current (Sink)IOL15VDD = 15V, VOUT = 1.5V1, 2+125o C 2.4-mA

-55o C 4.2-mA Output Current (Source)IOH5A VDD = 5V, VOUT = 4.6V1, 2+125o C--0.36mA

-55o C--0.64mA

Output Current (Source)

IOH5B

VDD = 5V, VOUT = 2.5V

1, 2

+125o C --1.15mA -55o C

--2.0mA Output Current (Source)

IOH10

VDD = 10V, VOUT = 9.5V

1, 2

+125o C --0.9mA -55o C

--1.6mA Output Current (Source)

IOH15

VDD =15V, VOUT = 13.5V

1, 2

+125o C --2.4mA -55o C

--4.2mA Input Voltage Low VIL VDD = 10V , VOH > 9V , VOL < 1V 1, 2+25o C, +125o C, -55o C -3V Input Voltage High VIH VDD = 10V , VOH > 9V , VOL < 1V 1, 2+25o C, +125o C, -55o C

+7-V Propagation Delay Clock to Q Output TPHL1TPLH1VDD = 10V 1, 2, 3+25o C -200ns VDD = 15V 1, 2, 3+25o C -150ns Propagation Delay Preset or Reset to Q TPHL2TPLH2VDD = 10V 1, 2, 3+25o C -210ns VDD = 15V 1, 2, 3+25o C -160ns Propagation Delay Clock to Carry Out TPHL3TPLH3VDD = 10V 1, 2, 3+25o C -240ns VDD = 15V 1, 2, 3+25o C -180ns Propagation Delay Carry In to Carry Out TPHL4TPLH4VDD = 10V 1, 2, 3+25o C -120ns VDD = 15V 1, 2, 3+25o C -100ns Propagation Delay Preset or Reset to Carry Out TPHL5TPLH5VDD = 10V 1, 2, 3, 4+25o C -320ns VDD = 15V 1, 2, 3, 4+25o C -250ns Transition Time

TTLH TTHL VDD = 10V 1, 2, 3+25o C -100ns VDD = 15V 1, 2, 3+25o C -80ns Maximum Clock Input Fre-quency

FCL

VDD = 10V 1, 2+25o C 4-MHz VDD = 15V

1, 2+25o C 5.5-MHz Minimum Hold Time Preset Enable to JN

VDD = 5V 1, 2, 3+25o C -70ns VDD = 10V 1, 2, 3+25o C -40ns VDD = 15V

1, 2, 3+25o C -40ns Minimum Data Setup Time Preset Enable to JN

VDD = 5V 1, 2, 3+25o C -25ns VDD = 10V 1, 2, 3+25o C -10ns VDD = 15V

1, 2, 3+25o C -10ns Minimum Data Hold Time Clock to Carry In

VDD = 5V 1, 2, 3+25o C -60ns VDD = 10V 1, 2, 3+25o C -30ns VDD = 15V

1, 2, 3+25o C -30ns Minimum Clock Hold Time Clock to Up/Down

VDD = 5V 1, 2, 3+25o C -30ns VDD = 10V 1, 2, 3+25o C -30ns VDD = 15V

1, 2, 3+25o C -30ns Input Capacitance CIN

Any Input

1, 2

+25o C

-7.5

NOTES:

1.All voltages referenced to device GND.

2.The parameters listed on Table 3are controlled via design or process and are not directly tested.These parameters are characterized on initial design release and upon design changes which would affect these characteristics.

3.CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4.Reset to Carry Out (TPLH) only.

TABLE 3.ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL CONDITIONS

NOTES TEMPERATURE

LIMITS

UNITS MIN MAX

TABLE4.POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITS MIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND1, 4+25o C-25μA N Threshold Voltage VNTH VDD = 10V, ISS = -10μA1, 4+25o C-2.8-0.2V N Threshold Voltage

Delta

?VTN VDD = 10V, ISS = -10μA1, 4+25o C-±1V P Threshold Voltage VTP VSS = 0V, IDD = 10μA1, 4+25o C0.2 2.8V P Threshold Voltage

Delta

?VTP VSS = 0V, IDD = 10μA1, 4+25o C-±1V

Functional F VDD = 18V, VIN = VDD or GND1+25o C VOH >

VDD/2VOL <

VDD/2

VDD = 3V, VIN = VDD or GND

Propagation Delay Time TPHL

TPLH VDD = 5V1, 2, 3, 4+25o C- 1.35 x

+25o C

Limit

NOTES: 1.All voltages referenced to device GND.

2.CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3.See Table 2 for +25o C limit.

4.Read and Record

TABLE5.BURN-IN AND LIFE TEST DELTA PARAMETERS +25o C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2IDD± 1.0μA

Output Current (Sink)IOL5± 20% x Pre-Test Reading Output Current (Source)IOH5A± 20% x Pre-Test Reading

TABLE6.APPLICABLE SUBGROUPS

CONFORMANCE GROUP MIL-STD-883

METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Pre Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A

Interim Test 1 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A

Interim Test 2 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A PDA (Note 1)100% 50041, 7, 9, Deltas

Interim Test 3 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A PDA (Note 1)100% 50041, 7, 9, Deltas

Final Test100% 50042, 3, 8A, 8B, 10, 11

Group A Sample 50051, 2, 3, 7, 8A, 8B, 9, 10, 11

Group B Subgroup B-5Sample 50051, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11 Subgroup B-6Sample 50051, 7, 9

Group D Sample 50051, 2, 3, 8A, 8B, 9Subgroups 1, 2 3

NOTE:1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE7.TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS MIL-STD-883

METHOD

TEST READ AND RECORD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

Group E Subgroup 250051, 7, 9Table 41, 9Table 4

TABLE 8.BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION OPEN

GROUND

VDD

9V ± -0.5V

OSCILLATOR

50kHz

25kHz

CD4510BMS Static Burn-In 1(Note 1)2, 6, 7, 11, 141,3-5,8-10,12,13,

Static Burn-In 2(Note 1)2, 6, 7, 11, 14

1,3-5,9,10,12,13,

15, 16

Dynamic Burn-In (Note 1)-1, 3, 4, 8, 9, 12, 13

10, 162, 6, 7, 11, 14

Irradiation (Note 2)2, 6, 7, 11, 14

1,3-5,9,10,12,13,

15, 16

NOTES:

1.Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2.Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,VDD = 10V ± 0.5V

Logic Diagrams

FIGURE 1.CD4510BMS

P Q

PE C T

P1*4

Q16

RESET *

P Q Q PE C

P2*12

Q211

P Q Q PE C T

P3*13

Q314

P Q Q PE C T

P4*3

Q42

PRESET *ENABLE 1

15CLOCK *7

CARRY OUT

U/D

Q4Q3Q4

U/D Q2U/D Q3U/D U/D Q2Q3U/D Q2Q3Q3

CARRY IN *10

UP/DOWN *

U/D U/D

VDD

VSS

ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION NETWORK

U/D

Q2Q2

FIGURE 2.CD4516BMS

TRUTH TABLE

CL CI U/D PE R ACTION X

1X 00NO COUNT 0100COUNT UP 0

000COUNT DOWN X X X 10PRESET X

RESET

X = DON’T CARE

Logic Diagrams (Continued)

P Q

PE C T

P1*4

Q16

RESET *

P Q Q PE C

P2*12

Q211

P Q Q PE C T

P3*13

Q314

P Q Q PE C T

P4*3

Q42

PRESET *ENABLE 1

15CLOCK *7

CARRY OUT

U/D Q3Q4

U/D U/D

U/D Q2Q3U/D Q2

CARRY IN *10

UP/DOWN *

U/D U/D

VDD

VSS

ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK

U/D Q2

Q2Q2Q3Q4Q2

Typical Performance Characteristics

FIGURE 3.TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 4.MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 5.TYPICAL OUTPUT HIGH (SOURCE)CURRENT

CHARACTERISTICS

FIGURE 6.MINIMUM OUTPUT HIGH (SOURCE)CURRENT

CHARACTERISTICS

FIGURE 7.TYPICAL TRANSITION TIME vs LOAD

CAPACITANCE FIGURE 8.TYPICAL PROPAGATION DELAY TIME vs LOAD

CAPACITANCE FOR CLOCK-TO-Q OUTPUTS

10V

AMBIENT TEMPERA TURE (T A ) = +25o C

GATE-TO-SOURCE VOL TAGE (VGS) = 15V

51015

151********DRAIN-TO-SOURCE VOL TAGE (VDS) (V)

O U T P U T L O W (S I N K ) C U R R E N T (I O L ) (m A )

10V

AMBIENT TEMPERA TURE (T A ) = +25o C

GATE-TO-SOURCE VOL TAGE (VGS) = 15V

51015

7.55.02.510.012.515.0DRAIN-TO-SOURCE VOL TAGE (VDS) (V)

O U T P U T L O W (S I N K ) C U R R E N T (I O L ) (m A )

-10V

-15V

AMBIENT TEMPERATURE (T A ) = +25o C

GATE-TO-SOURCE VOLT AGE (VGS) = -5V

0-5-10-15

DRAIN-TO-SOURCE VOL TAGE (VDS) (V)

-20-25

-30

-5

-10-15O U T P U T H I G H (S O U R C E ) C U R R E N T (I O H ) (m A )

-10V

-15V

AMBIENT TEMPERATURE (T A ) = +25o C

-5

-10

-15

DRAIN-TO-SOURCE VOLT AGE (VDS) (V)

-5

-10-15O U T P U T H I G H (S O U R C E ) C U R R E N T (I O H ) (m A )

GATE-TO-SOURCE VOLT AGE (VGS) = -5V

AMBIENT TEMPERATURE (T A ) = +25o C

LOAD CAPACITANCE (CL) (pF)

40608010020

050

100

150

200

SUPPL Y VOLT AGE (VDD) = 5V

10V

15V

T R A N S I T I O N T I M E (t T L H ) (n s )

250

200

150

100

020

406080100LOAD CAPACITANCE (CL) (pF)

P R O P A G A T I O N D E L A Y T I M E (t P L H , t P H L ) (n s )

AMBIENT TEMPERATURE (T A ) = +25o C

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

FIGURE 9.TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs

SUPPLY VOLTAGE FIGURE 10.TYPICAL DYNAMIC POWER DISSIPATION vs

FREQUENCY

Typical Performance Characteristics

(Continued)

SUPPL Y VOL TAGE (VDD)

AMBIENT TEMPERA TURE (T A ) = +25o C LOAD CAPACITANCE (CL) = 50pF

M A X I M U M C L O C K I N P U T F R E Q U E N C Y (f C L M A X ) (M H z )

5101520

10V 5V

10V 8642

104

103

P O W E R D I S S I P A T I O N P E R G A T E (P D ) (μW )

SUPPLY VOLTS (VDD) = 15V

AMBIENT TEMPERATURE (T A )

tr, tf = 20ns = +25o C 8642

102

642INPUT FREQUENCY (fCL) (kHz)

86421086421028642103

642104

CL = 15pF

CL = 50pF 1415169

131211101234

576

100μF

ID 500μF PULSE GENERATOR

50%

10%

90%

20ns VDD

20ns

VARIABLE WIDTH

VSS

Acquisition System

FIGURE 12.TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM

16 CHANNEL MULTIPLEXER

CD4067

SELECT INPUTS

SAMPLE AND HOLD

10 BIT A/D

CONVERTER

CONVERSION

LOGIC

CD4516BMS

AMPLI-FIER

CLOCK

PRESET ENABLE

END

CLOCK

START ANALOG

DATA INPUTS

PARALLEL DATA

OUTPUTS

PRESET INPUTS

NOTE:

This acquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the CD4516BMS.

Timing Diagrams

FIGURE 13.CD4510BMS

FIGURE 14.CD4516BMS

CLOCK CARRY IN UP/DOWN PE P1P2P3P4Q1Q2Q3Q4

CARRY OUT

COUNT

RESET

1011121314159

15CLOCK CARRY IN UP/DOWN PE P1P2P3P4Q1Q2Q3Q4

CARRY OUT

COUNT

RESET

VDD VSS

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FIGURE 15.CASCADING COUNTER PACKAGES

*CARRY OUT lines at the 2nd,3rd,etc.,stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS IC’S.These negative going glitches do not affect proper CD4029BMS operation.However,if the CARRY OUT signals are used to trigger other edge-sensitive logic devices,such as FF’S or counters,the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as CD4071BMS.

UP/D R

PE CL Q1Q2Q3Q4

CI CO J1J2J3J4CD4510/16BMS UP/D R

PE CL Q1Q2Q3Q4

CI CO J1J2J3J4UP/D R

PE CL Q1Q2Q3Q4

CI CO J1J2J3J4*

UP/DOWN PRESET ENABLE

CLOCK RESET

PARALLEL CLOCKING

CD4510/16BMS CD4510/16BMS Ripple Clocking Mode:The up/down control can be changed at any count.The only restriction on changing the up/down control is that the clock input to the ?rst counting stage must be high.For cascading counters operating in a ?xed up-count or down-count mode,the OR gates are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded.

UP/D R

PE CL Q1Q2Q3Q4

CI CO J1J2J3J4UP/D R

PE CL Q1Q2Q3Q4

CI CO J1J2J3J4UP/D R

PE CL Q1Q2Q3Q4

CI CO J1J2J3J4UP/DOWN PRESET ENABLE

CLOCK RESET

1/4 CD4071B

RIPPLE CLOCKING

CD4510/16BMS CD4510/16BMS CD4510/16BMS