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79C0408RT1FH-20中文资料

Memory

4 Megabit (512k x 8-bit)

EEPROM MCM

79C0408

?Four 128k x 8-bit EEPROMs MCM

?R AD -P AK ? radiation-hardened against natural space radiation

?Total dose hardness:

- > 100 krad (Si), depending upon space mission ?Excellent Single Event Effects - SEL > 120 MeV/mg/cm 2

- SEU > 90 MeV/mg/cm 2 read mode - SEU = 18 MeV/mg/cm 2 write mode ?Package:

?- 40 pin R AD -P AK ? flat pack ?- 40 pin X-Ray Pak TM flat pack ?- 40 pin Rad-Tolerant flat pack ?High speed:

- 120, 150, and 200 ns maximum access times available

?Data Polling and Ready/Busy signal ?Software data protection ?Write protection by RES pin ?High endurance

- 10,000 erase/write (in Page Mode), - 10 year data retention

?Page write mode: 1 to 128 byte page ?Low power dissipation - 80 mW/MHz active mode - 440 μW standby mode

D ESCRIPTION :

Maxwell Technologies’ 79C0408 multi-chip module (MCM)memory features a greater than 100 krad (Si) total dose toler-ance, depending upon space mission. Using Maxwell Technol-ogies’ patented radiation-hardened R AD -P AK ? MCM packaging technology, the 79C0408 is the first radiation-hard-ened 4 Megabit MCM EEPROM for space applications. The 79C0408 uses four 1 Megabit high-speed CMOS die to yield a 4 Megabit product. The 79C0408 is capable of in-system elec-trical Byte and Page programmability. It has a 128 bytes Page Programming function to make its erase and write operations faster. It also features Data Polling and a Ready/Busy signal to indicate the completion of erase and programming operations.In the 79C0408, hardware data protection is provided with the RES pin, in addition to noise protection on the WE signal.Software data protection is implemented using the JEDEC optional standard algorithm.

Maxwell Technologies' patented R AD -P AK ? packaging technol-ogy incorporates radiation shielding in the microcircuit pack-age. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, the R AD -P AK ? package provides greater than 100 krad (Si) radiation dose tolerance. This prod-uct is available with screening up to Class K.

F EATURES :

Memory

1.V

IN MIN = -3.0V FOR PULSE WIDTH <50NS.

T ABLE 1. 79C0408 P IN D ESCRIPTION

P IN S YMBOL D ESCRIPTION

16-9, 32-31,

28, 30, 8, 33,

7, 36, 6

A0 to A16Address Input

17-19, 22-26I/O0 to I/O7Data Input/Output

29OE Output Enable

2, 3, 39, 38CE1-4Chip Enable 1 through 4

34WE Write Enable

1, 27, 40VCC Power Supply

4, 20, 21, 37VSS Ground

5RDY/BUSY Ready/Busy

35RES Reset

T ABLE 2. 79C0408 A BSOLUTE M AXIMUM R ATINGS

P ARAMETER S YMBOL M IN M AX U NIT Supply Voltage V

-0.67.0V

Input Voltage V

-0.517.0V Package Weight RP23Grams

RT10

Thermal Resistance ( RP Package)Tjc7.3°C/W

Operating Temperature Range T

OPR

-55125°C

Storage Temperature Range T

STG

-65150°C T ABLE 3. 79C0408 R ECOMMENDED O PERATING C ONDITIONS

P ARAMETER S YMBOL M IN M AX U NIT

Supply Voltage V

4.5

5.5V

Input Voltage

RES_PIN V

-0.31

2.2

-0.5

1.V

IL min = -1.0V for pulse width < 50 ns

0.8

+0.3

Case Operating Temperature T

-55125°C

Memory

T ABLE 4. 79C0408 C APACITANCE 1

(T A = 25 °C, f = 1 MHz)

P ARAMETER

S YMBOL M IN M AX U NIT Input Capacitance: V IN = 0 V 1WE CE 1-4OE A 0-16

1.Guaranteed by design.

C IN

--------

2462424pf

Output Capacitance: V OUT = 0 V 1C OUT

T ABLE 5. D ELTA P ARAMETERS

P ARAMETER C ONDITION

I CC1+ 10% of value in Table 6I CC2+ 10% of value in Table 6I CC3+ 10% of value in Table 6I CC4

+ 10% of value in Table 6

T ABLE 6. 79C0408 DC E LECTRICAL C HARACTERISTICS

(V CC = 5V ±10%, T A = -55 TO +125°C)

P ARAMETER

T EST C ONDITION

S YMBOL S UBGROUPS M IN M AX U NITS Input Leakage Current

V CC = 5.5V , V IN = 5.5V 1I IL

1, 2, 3

μA

CE 1-4-- 2 1OE, WE --8A 0-16

--8Output Leakage Current V CC = 5.5V, V OUT = 5.5V/0.4V I LO 1, 2, 3

--8μA Standby V CC Current

CE = V CC I CC1--80μA CE = V IH

I CC2--4mA Operating V CC Current 2

I OUT = 0mA, Duty = 100%, Cycle = 1μs at V CC = 5.5V I CC31, 2, 3--15mA

I OUT = 0mA, Duty = 100%, Cycle = 150ns at V CC = 5.5V

I CC41, 2, 3--50Input Voltage

RES_PIN

V IL 1, 2, 3--0.8V V IH 2.2--V H V CC -0.5--Output Voltage

I OL = 2.1 mA V OL 1, 2, 3--0.4V I OH = -0.4 mA

V OH

2.4

Memory

1.I LI on RES = 100 uA max.

2.Only one CE\ Active.

T ABLE 7. 79C0408 AC E LECTRICAL C HARACTERISTICS FOR R EAD O PERATIONS 1

(V CC = 5V ±10%, T A = -55 TO +125°C)

1.Test conditions: Input pulse levels - 0.4V to

2.4V; input rise and fall times < 20ns; output load - 1 TTL gate + 100pF (including scope and jig); reference levels for measuring timing - 0.8V/1.8V.P ARAMETER

S YMBOL S UBGROUPS M IN

M AX

U NIT Address Access Time CE = OE = V IL , WE = V IH -120-150-200

t ACC

9, 10, 11

------120150200

Chip Enable Access Time OE = V IL , WE = V IH -120-150-200

t CE

9, 10, 11

------120150200

Output Enable Access Time CE = V IL , WE = V IH -120-150-200

t OE

9, 10, 11

000

7575125

Output Hold to Address Change CE = OE = V IL , WE = V IH -120-150-200

t OH

9, 10, 11

000

------ns

Output Disable to High-Z 2 CE = V IL , WE = V IH -120-150-200

2.t DF and t DFR are defined as the time at which the output becomes an open circuit and data is no longer driven.t DF

9, 10, 11

000

505060ns

CE = OE = V IL , WE = V IH -120-150-200

t DFR

9, 10, 11

000

300350450

RES to Output Delay CE = OE = V IL , WE = V IH 3-120-150-200

3.Guaranteed by design.

t RR

9, 10, 11

------400450650ns

Memory

T ABLE 8. 79C0408 AC E LECTRICAL C HARACTERISTICS FOR W RITE O PERATIONS

(V CC = 5V ±10%, T A = -55 TO +125°C)

P ARAMETER

S YMBOL S UBGROUPS M IN 1

M AX

U NIT Address Setup Time -120-150-200

t AS

9, 10, 11

000

------ns

Chip Enable to Write Setup Time (WE Controlled)-120-150-200

t CS

9, 10, 11

000

------ns

Write Pulse Width CE Controlled -120-150-200

WE Controlled -120-150-200

t CW

t WP

9, 10, 11

200250350200250350

------------ns

Address Hold Time -120-150-200t AH

9, 10, 11

150150200

------ns

Data Setup Time -120-150-200t DS

9, 10, 11

75100150

------ns

Data Hold Time -120-150-200

t DH

9, 10, 11

101010

------ns

Chip Enable Hold Time (WE Controlled)-120-150-200

t CH

9, 10, 11

000

------ns

Write Enable to Write Setup Time (CE Controlled)-120-150-200

t WS

9, 10, 11

000

------ns

Write Enable Hold Time (CE Controlled)-120-150-200

t WH

9, 10, 11

000

------ns

Memory

Output Enable to Write Setup Time -120-150-200

t OES

9, 10, 11

000

------ns

Output Enable Hold Time -120-150-200

t OEH

9, 10, 11

000

------ns

Write Cycle Time 2-120-150-200t WC

9, 10, 11

------101010

Data Latch Time -120-150-200

t DL

9, 10, 11

250300400

------ns

Byte Load Window -120-150-200t BL

9, 10, 11

100100200

------μs

Byte Load Cycle -120-150-200

t BLC

9, 10, 11

0.550.550.95

303030

μs

Time to Device Busy -120-150-200t DB

9, 10, 11

100120170

------ns

Write Start Time 3-120-150-200

t DW

9, 10, 11

150150250

------ns

RES to Write Setup Time -120-150-200

t RP

9, 10, 11

100100200

------μs

V CC to RES Setup Time 4-120-150-200

t RES

9, 10, 11

113------μs

https://www.wendangku.net/doc/619981101.html,e this divice in a longer cycle than this value.

2.t WC must be longer than this value unless polling techniques or RDY/BUSY are used. This device automatically completes the internal write operation within this value.

T ABLE 8. 79C0408 AC E LECTRICAL C HARACTERISTICS FOR W RITE O PERATIONS

(V CC = 5V ±10%, T A = -55 TO +125°C)

P ARAMETER

S YMBOL S UBGROUPS M IN 1

M AX U NIT

Memory

F IGURE 1. R EAD T IMIN

G W AVEFORM

3.Next read or write operation can be initiated after t DW if polling techniques or RDY/BUSY are used.

4.Gauranteed by design.

T ABLE 9. 79C0408 M ODE S ELECTION 1, 2

1.X = Don’t care.

2.Refer to the recommended DC operating conditions.P ARAMETER

CE 33.For CE 1-4 only one CE can be used (“on”) at a time.

OE WE I/O RES RDY/BUSY Read V IL V IL V IH D OUT V H High-Z Standby V IH X X High-Z X High-Z Write V IL V IH V IL D IN V H High-Z --> V OL

Deselect V IL V IH V IH High-Z V H High-Z Write Inhibit X X V IH --X --X V IL X --X --Data Polling V IL V IL V IH Data Out (I/O7)

V H V OL Program X

High-Z

V IL

High-Z

Memory

F IGURE 6. D ATA P OLLIN

G T IMING W AVEFORM

Memory

F IGURE 7. S OFTWARE D ATA P ROTECTION T IMIN

G W AVEFORM (1) (IN PROTECTION MODE )

F IGURE 8. S OFTWARE D ATA P ROTECTION T IMIN

G W AVEFORM (2) (IN NON -PROTECTION MODE )

Toggle Bit Waveform

EEPROM A PPLICATION N OTES

This application note describes the programming procedures for each EEPROM module (four in each MCM) and details of various techniques to preserve data protection.

Automatic Page Write

Page-mode write feature allows from 1 to 128 bytes of data to be written into the EEPROM in a single write cycle, and allows the undefined data within 128 bytes to be written corresponding to the undefined address (A0 to A6). Loading the first byte of data, the data load window opens 30 μs for the second byte. In the same manner each additional byte of data can be loaded within 30 μs. In case CE and WE are kept high for 100 μs after data input, the EEPROM enters erase and write mode automatically and only the input data are written into the EEPROM.

Memory

WE CE Pin Operation

During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE.

Data Polling

Data Polling function allows the status of the EEPROM to be determined. If the EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded output is from I/O 7 to indicate that the EEPROM is per-forming a write operation.

RDY/Busy Signal

RDY/Busy signal also allows a comparison operation to determine the status of the EEPROM. The RDY/Busy signal has high impedance except in write cycle and is lowered to V OL after the first write signal. At the-end of a write cycle,the RDY/Busy signal changes state to high impedance.

RES Signal

When RES is LOW, the EEPROM cannot be read and programmed. Therefore, data can be protected by keeping RES low when V CC is switched. RES should be kept high during read and programming because it doesn’t provide a latch function.

Data Protection

To protect the data during operation and power on/off, the EEPROM has the internal functions described below.

Data Protection against Noise of Control Pins (CE, OE, WE) during Operation.

Memory

During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mis-take. To prevent this phenomenon, the EEPROM has a noise cancellation function that cuts noise if its width is 20 ns or less in programming mode. Be careful not to allow noise of a width of more than 20ns on the control pins.

2. Data Protection at V CC on/off

When V CC is turned on or off, noise on the control pins generated by external circuits, such as CPUs, may turn the EEPROM to programming mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in unprogrammable state during V CC on/off by using a CPU reset signal to RES pin.

RES should be kept at V SS level when V CC is turned on or off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input.

3. Software Data Protection

The software data protection function is to prevent unintentional programming caused by noise generated by external circuits. In software data protection mode, 3 bytes of data must be input before write data as follows. These bytes can switch the non-

protection mode to the protection mode.

10mS min

Memory

Software data protection mode can be canceled by inputting the following 6 bytes. Then, the EEPROM turns to the non-protec-

tion mode and can write data normally. However, when the data is input in the canceling cycle, the data cannot be written.

Pin #1 ID

Memory

40 P IN R AD-P AK? P ACKAGE D IMENSIONS

S YMBOL D IMENSION

M IN N OM M AX

A0.2480.2740.300

b0.0130.0150.022

c0.0060.0080.010

D--0.8500.860

E0.9850.995 1.005

E1---- 1.025

E20.8900.895--

E30.0000.050--

e0.040 BSC

L0.3800.3900.400

Q0.2140.2450.270

S10.0050.038--

N40

F40-01

Note: All dimensions in inches

Memory

40 P IN X-R AY -P AK TM F LAT P ACKAGE D IMENSIONS

NOTE: All Dimensions in Inches

S YMBOL

D IMENSION

M IN

N OM M AX A 0.2480.2740.300b 0.0130.0150.022c 0.0060.0080.010D 0.8400.8500.860E 0.9850.995 1.005E2--0.785--E3--0.105--

e 0.040 BSC L 0.3400.3500.400Q 0.0500.0650.075S1--0.035--N

Memory

40 P IN R AD-T OLERANT F LAT P ACKAGE D IMENSIONS

S YMBOL D IMENSION

M IN N OM M AX

A0.2020.2240.246

b0.0130.0150.022

c0.0060.0080.010

D--0.8500.860

E0.9850.995 1.005

E1---- 1.025

E20.8900.895--

E30.0000.050--

e0.040 BSC

L0.3800.3900.400

Q0.1900.2200.270

S10.0050.038--

N40

NOTE: All Dimensions in Inches

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies

functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to

date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no

responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems

without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies. must be made within 90 days from the date of shipment from Maxwell Tech-

nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

Memory

Product Ordering Options

Model Number

Feature Option Details

79C0408

-XX

Access Time

Screening Flow

Package

Radiation Feature

Base Product Nomenclature

12 = 120 ns 15 = 150 ns 20 = 200 ns

Multi Chip Module (MCM)K = Maxwell Class K H = Maxwell Class H

I = Engineering (testing @-55°C, +25°C and +125°C)

E = Engineering (testing @ +25°C

F = Flat Pack

RP = R AD -P AK ? package

RT1 = Guaranteed to 10 krad at die level

RT2 = Guaranteed to 25 krad at die level

RT4 = Guaranteed to 40 krad at die level

4 Megabit (512k x 8-bit) EEPROM MCM

XP = X-Ray Pak