EDI2GG432128V11D中文资料

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The EDI2GG432128VxxD is a Synchronous SRAM, 60 position Card Edge; DIMM (120 contacts) Module, organized as 4x128Kx32.The Module contains four (4) Synchronous Burst Ram Devices,packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Synchronous Only, Flow-Through, Early Write De-vice. This Module provides high performance, ultra fast access times at a cost per bit benefit over BiCMOS Asynchronous SRAM based devices. As well as improved cost per bit, the use of Synchronous or Synchronous Burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement.

Synchronous operations are in relation to an externally supplied clock , registered address, registered global write, registered enables as well as an Asynchronous Output enable. All read and write operations to this module are performed on long words (double words) 32 bit operations.

Write cycles are internally self timed and are initiated by a rising clock edge. This feature relieves the designer the task of devel-oping external write pulse width circuitry.

FEATURES

s 4x128Kx32 Synchronous

s Access Speed(s): T KHQV = 9.5, 10, 11, 12, 15ns s Flow-Through Architecture

s Clock Controlled Registered Bank Enables (E 1\, E 2\, E 3\, E 4\)s Clock Controlled Registered Address

s Clock Controlled Registered Global Write (GW\)s Aysnchronous Output Enable (G\)s Internally self-timed Write s Gold Lead Finish s 3.3V ±10%, -5% Operation s Common Data Input/Output

s High Capacitance (30pF) drive, at rated Access Speed s Single total array Clock s Multiple Vcc and Vss

July 1999 Rev.ECO#

4x128Kx32 Synchronous SRAM CARD EDGE DIMM

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V SS V SS A 0A 1A 15A 2A 14A 3A 13V CC V CC A 4A 12A 5A 6A 7V SS A 8V SS CLK V SS E 4\V CC E 3\G\V SS DQ 0DQ 1DQ 2DQ 3V CC DQ 8DQ 9DQ 10DQ 16DQ 17DQ 18DQ 19V CC DQ24DQ25DQ26DQ27V SS V CC V SS V CC V SS

V SS DQ 11A 11A 10A 9V SS RFU V SS ZZ V SS E 2\V CC E 1\GW\V SS DQ 7DQ 6DQ 5DQ 4V CC DQ 15

DQ 14DQ 13DQ 12V SS DQ 23DQ 22DQ 21DQ 20V CC DQ 31DQ 30DQ 29DQ 28V SS V CC V SS V CC V SS

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC A 16111315171921232527282624222018161412102931333537394143454749515250484644424038363430325355575961636567697173545658606264666870727475777981838587899193767880828486889092949698100102104106108110112114116959799101103105107109111113115117119118120957318642PIN CONFIGURATION

PIN DESCRIPTIONS

DIMM Pins Symbol Type Description

3, 5, 7, 9, 13, 15,A0-16Input Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 17, 19, 20, 23, 18,Synchronous The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.

16, 14, 10, 8, 6,4

38GW\Input Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\

Synchronous lines and must meet the setup and hold times around the rising edge of CLK.

27CLK Input Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its

Synchronous rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.

36, 32E1, E2\Input Bank Enables: These active LOW inputs are used to enable each individual bank andto gate ADSP\.

E3\, E4\Synchronous

37G\Input Output Enable: This active LOW asynchronous input enables the data output drivers.

Various DQ0-32Input/Output Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth

byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.

Various Vcc Supply Core power supply: +3.3V -5%/+10%

Various Vss Ground Ground

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DC ELECTRICAL CHARACTERISTICS - READ CYCLE

RECOMMENDED DC OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS*

SYNCHRONOUS ONLY - TRUTH TABLE

*Stress greater than those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those

indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Voltage on Vcc Relative to Vss -0.5V to +4.6V Vin

-0.5V to Vcc +0.5V Storage Temperature

-55°C to +125°C Operating Temperature (Commercial)0°C to +70°C Operating Temperature (Industrial)-40°C to +85°C

Short Circuit Output Current

20 mA

Operation

E1\E2\E3\E4\GW\G\CLK DQ Synchronous Write-Bank 1L H H H L H ↑High-Z Synchronous Read-Bank 1L H H H H L ↑Synchronous Write-Bank 2H L H H L H ↑ High-Z Synchronous Read-Bank 2H L H H H L ↑Synchronous Write-Bank 3H H L H L H ↑High-Z Synchronous Read-Bank 3H H L H H L ↑Synchronous Write-Bank 4H H H L L H ↑High-Z Synchronous Read-Bank 4H H H L H L ↑Snooze Mode

X

X

X

X

X

X

X

High-Z

Parameter Sym Min Typ Max Units Supply Voltage V CC 3.14 3.3 3.6V Supply Voltage V SS 0.00.00.0V Input High V IH 2.2 3.0V CC +0.3V Input Low V IL -0.30.00.8V Input Leakage IL I -212μA Output Leakage

ILo -212μA Output High (I OH = -4mA)V OH 2.4--V

Output Low (I OL = 8mA)

V OL

--0.4V

Max

Description

Symbol Typ 9.510111215Units Power Supply Current Icc 10.78* 1.1 1.0 1.0 1.0A Power Supply Current

Icc 325*760760500500mA Device Selected,No Operation

Snooze Mode Icc ZZ 80*120120120120mA CMOS Standby

Icc 3200*360360360360mA Clock Running-Deselect

Icc K

300

*

550

500

380

350

mA

*TBD

READ CYCLE TIMING PARAMETERS

*TBD 9.5ns10ns11ns12ns15ns

Description Sym Min Max Min Max Min Max Min Max Min Max Units Clock Cycle Time t KHKH**12121520ns Clock High Time t KHKL**5556ns Clock Low Time t KLKH**5556ns Clock to Output Valid t KHQV**10111215ns Clock to Output Invalid t KHQX1**3333ns Clock to Output Low-Z t KHQX**2222ns Output Enable to Output Valid t GLQV**5556ns Output Enable to Output Low-Z t GLQX**0000ns Output Enable to Output High-Z t GHQZ**5556ns Address Setup t AVKH** 2.5 2.5 2.5 2.5ns Bank Enable Setup t EVKH** 2.5 2.5 2.5 2.5ns Address Hold t KHAX** 1.0 1.0 1.0 1.0ns Bank Enable Hold t KHEX** 1.0 1.0 1.0 1.0ns

WRITE CYCLE TIMING PARAMETERS

9.5ns10ns11ns12ns15ns

Description Sym Min Max Min Max Min Max Min Max Min Max Units Clock Cycle Time t KHKH**12121520ns Clock High Time t KHKL**5556ns Clock Low Time t KLKH**5556ns Address Setup t AVKH** 2.5 2.5 2.5 2.5ns Address Hold t KHAX** 1.0 1.0 1.0 1.0ns Bank Enable Setup t EVKH** 2.5 2.5 2.5 2.5ns Bank Enable Hold t KHEX** 1.0 1.0 1.0 1.0ns Global Write Enable Setup t WVKH** 2.5 2.5 2.5 2.5ns Global Write Enable Hold t KHWX** 1.0 1.0 1.0 1.0ns Data Setup t DVKH** 2.5 2.5 2.5 2.5ns Data Hold t KHDX** 1.0 1.0 1.0 1.0ns

*TBD

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ORDERING INFORMATION

Part Number Organization Voltage Speed (ns)Package EDI2GG432128V95D*4x128Kx32 3.39.5120 Card Edge DIMM EDI2GG432128V10D*4x128Kx32 3.310120 Card Edge DIMM EDI2GG432128V11D4x128Kx32 3.311120 Card Edge DIMM EDI2GG432128V12D4x128Kx32 3.312120 Card Edge DIMM EDI2GG432128V15D4x128Kx32 3.315120 Card Edge DIMM

*Consult Factory for Availability

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