ACT-F512K32N-090F5I中文资料
General Description
The ACT–F512K32 is a high speed, 16 megabit CMOS flash multichip module (MCM)designed for full temperature range military, space, or high reliability applications.
The MCM can be organized as a 512K x 32bits, 1M x 16bits or 2M x 8bits device and is input TTL and output CMOS compatible. The command register is written by bringing WE to a logic low level (V IL ),while CE is low and OE is at logic high level (V IH ). Reading is accomplished by chip Enable (CE) and Output Enable (OE)being logically active, see Figure 9. Access time grades of 60ns, 70ns, 90ns, 120ns and 150ns maximum are standard. The ACT–F512K32 is packaged in a hermetically
Features
512Kx8
512Kx8
512Kx8
512Kx8
CE 4
OE A 0 – A 18
I/O 0-7
I/O 8-15
I/O 16-23
I/O 24-31
8888CE 3WE 4WE 3WE 2WE 1CE 1CE 2Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)
Pin Description I/O 0-31
Data I/O
A 0–18Address Inputs WE 1-4Write Enables CE 1-4Chip Enables OE Output Enable V CC Power Supply
GND Ground NC
Not Connected
■ 4 Low Power 512K x 8 FLASH Die in One MCM
Package
■ TTL Compatible Inputs and CMOS Outputs ■ Access Times of 60, 70, 90, 120 and 150ns ■ +5V Programing, 5V ±10% Supply ■ 100,000 Erase/Program Cycles ■ Low Standby Current
■ Page Program Operation and Internal Program Control Time
■ Sector Architecture (Each Die)
● 8 Equal size sectors of 64K bytes each
● Any Combination of Sectors can be erased with one command sequence ● Supports full chip erase
■ Embedded Erase and Program Algorithms ■ MIL-PRF-38534 Compliant MCMs Available
■ Industry Standard Pinouts
■ Packaging – Hermetic Ceramic
● 68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint)● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder, Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With Shoulder, Aeroflex code# "P7"
■ Internal Decoupling Capacitors for Low Noise Operation
■ Commercial, Industrial and Military Temperature Ranges
■ DESC SMD# 5962–94612 Released (P3,P7,F5)
ACT–F512K32 High Speed
16 Megabit FLASH Multichip Module
sealed co-fired ceramic 66 pin, 1.08"SQ PG A or a 68 lead, .88"SQ Ceramic Gull Wing CQFP package for operation over the temperature range of -55°C to +125°C and military environment.
Each flash memory die is organized as 512KX8 bits and is designed to be programmed in-system with the standard system 5.0V Vcc supply. A 12.0V V PP is not required for write or erase operations. The MCM can also be reprogrammed with standard EPROM programmers (with the proper socket).
The standard ACT–F512K32 offers access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE) and write enable (WE). The ACT-F512K32 is command set compatible with JEDEC standard 4 Mbit EEPROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from 12.0V Flash or EPROM devices. The ACT-F512K32 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. T ypically, each sector can be programmed and verified in less than one second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array, (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
Each die in the module or any individual sector of the die is typically erased and verified in 1.5 seconds (if already completely preprogrammed).
Each die also features a sector erase architecture. The sector mode allows for 64K byte blocks of memory to be erased and reprogrammed without affecting other blocks. The ACT-F512K32 is erased when shipped from the factory.
The device features single 5.0V power supply operation for both read and write functions. lnternally generated and regulated voltages are provided for the program and erase operations. A low V CC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of D7 or by the T oggle Bit feature on D6. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode.
All bits of each die, or all bits within a sector of a die, are erased via Fowler-Nordhiem tunneling. Bytes are programmed one byte at a time by hot electron injection.
DESC Standard Military Drawing (SMD) numbers are released.
General Description, Cont’d,
z Absolute Maximum Ratings
Parameter Symbol Range Units Case Operating T emperature T C-55 to +125°C Storage Temperature Range T STG-65 to +150°C Supply Voltage Range V CC-2.0 to +7.0V
Signal Voltage Range (Any Pin Except A9) Note 1V G-2.0 to +7.0V
Maximum Lead Temperature (10 seconds)-300°C Data Retention-10Y ears Endurance (Write/Erase cycles)-100,000 Minimum
A9 Voltage for sector protect, Note 2V ID-2.0 to +14.0V
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot V SS to -2.0v for periods of up to 20ns. Maximum DC voltage on input and I/O pins is V CC + 0.5V. During voltage transitions, inputs and I/O pins may overshoot to
V CC + 2.0V for periods up to 20 ns.
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot V SS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.
Normal Operating Conditions
Symbol Parameter Minimum Maximum Units
V CC Power Supply Voltage+4.5+5.5V
V IH Input High Voltage+2.0V CC + 0.5V
V IL Input Low Voltage-0.5+0.8V
T A Operating Temperature (Military)-55+125°C
V ID A9 Voltage for sector protect 11.512.5V
Capacitance
(V IN= 0V, f = 1MHz, Tc = 25°C)
Symbol Parameter Maximum Units
C A
D A0 – A16 Capacitance 50pF
C OE OE Capacitance50pF
C WE Write Enable Capacitance
CQFP(F5) Package20pF
PGA(P3,P7) Package20pF
C CE Chip Enable Capacitance20pF
C I/O I/O0 – I/O31 Capacitance20pF
Parameters Guaranteed but not tested
DC Characteristics – CMOS Compatible
(Vcc = 5.0V, Vss = 0V, T C = -55°C to +125°C, unless otherwise indicated)
Parameter Sym Conditions
Speeds 60, 70, 90, 120 & 150ns Minimum Maximum Units
Input Leakage Current I LI V CC = 5.5V, Vi N = GND to V CC10μA Output Leakage Current I LOX32V CC = 5.5V, Vi N = GND to V CC10μA Active Operating Supply Current for Read (1)I CC1CE = V IL, OE = V IH, f = 5MHz190mA Active Operating Supply Current for Program or Erase (2)I CC2CE = V IL, OE = V IH240mA Standby Supply Current I CC4V CC = 5.5V, CE = V IH, f = 5MHz 6.5mA Static Supply Current (4)I CC3V CC = 5.5V, CE = V IH0.6mA Output Low Voltage V OL I OL = +8.0 mA, V CC = 4.5V0.45V Output High Voltage V OH I OH = –2.5 mA, V CC = 4.5V0.85 x V CC V Low Power Supply Lock-Out Voltage (4)V LKO 3.2 4.2V Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at V IN.
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: V IL = 0.3V, V IH = V CC - 0.3V, unless otherwise indicated
Note 4. Parameter Guaranteed but not tested.
AC Characteristics – Read Only Operations (Vcc = 5.0V, Vss = 0V, T C = -55°C to +125°C)
Parameter
Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max
–120
Min Max
–150
Min Max
Units
Read Cycle Time t AVAV t RC607090120150ns Address Access Time t AVQV t ACC607090120150ns Chip Enable Access Time t ELQV t CE607090120150ns Output Enable to Output Valid t GLQV t OE3035355055ns Chip Enable to Output High Z (1)t EHQZ t DF2020203035ns Output Enable High to Output High Z (1)t GHQZ t DF2020203035ns Output Hold from Address, CE or OE Change, Whichever is First t AXQX t OH00000ns Note 1. Guaranteed by design, but not tested.
AC Characteristics – Write/Erase/Program Operations, WE Controlled
(Vcc = 5.0V, Vss = 0V, T C = -55°C to +125°C)
Parameter
Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max
–120
Min Max
–150
Min Max
Units
Write Cycle Time t AVAC t WC607090120150ns Chip Enable Setup Time t ELWL t CE00000ns Write Enable Pulse Width t WLWH t WP4045455050ns Address Setup Time t AVWL t AS00000ns Data Setup Time t DVWH t DS4045455050ns Data Hold Time t WHDX t DH00000ns Address Hold Time t WLAX t AH4545455050ns Write Enable Pulse Width High t WHWL t WPH2020202020ns Duration of Byte Programming t WHWH114TYP14TYP14TYP14TYP14TYPμs Sector Erase Time t WHWH23030303030Sec Chip Erase Time t WHWH3120120120120120Sec Read Recovery Time before Write (2)t GHWL00000μs Vcc Setup Time (2)t VCE5050505050μs Chip Programming Time5050505050Sec Output Enable Setup Time (2)t OES00000ns Output Enable Hold Time (1) (2)t OEH1010101010ns Notes: 1. For T oggle and Data Polling. 2. Guaranteed by design, but not tested.
AC Characteristics – Write/Erase/Program Operations, CE Controlled
(Vcc = 5.0V, Vss = 0V, T C = -55°C to +125°C)
Parameter
Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max
–120
Min Max
–150
Min Max
Units
Write Cycle Time t AVAC t WC607090120150ns Write Enable Setup Time t WLE L t WS00000ns Chip Enable Pulse Width t ELEH t CP4045455050ns Address Setup Time t AVEL t AS00000ns Data Setup Time t DVEH t DS4045455050ns Data Hold Time t EHDX t DH00000ns Address Hold Time t ELAX t AH4545455050ns Chip Enable Pulse Width High t EHEL t CPH2020202020ns Duration of Byte Programming Operation t WHWH114TYP14TYP14TYP14TYP14TYPμs Sector Erase Time t WHWH23030303030Sec Chip Erase Time t WHWH3120120120120120Sec Read Recovery Time Before Write (1)t GHEL00000μs Chip Programming Time5050505050Sec 1. Guaranteed by design, but not tested.
Device Operation
The ACT-F512K32 MCM is composed of four, four megabit Flash chips. The following description is for the individual flash device, is applicable to each of the four memory chips inside the MCM. Chip 1 is distinguished by CE1 and I/O1-7, Chip 2 by CE2 and I/08-15, Chip 3 by CE3 and I/016-23, and Chip 4 by CE4 and I/024-31. Programming of the ACT-F512K32 is accomplished by executing the program command sequence. The program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell status. Sectors can be programed and verified in less than one second. Erase is accomplished by executing the erase command sequence. The erase algorithm, which is internal, automatically preprograms the array if it is not already programed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell status. The entire memory is typically erased and verified in 1.5 seconds (if pre-programmed). The sector mode allows for 64K byte blocks of memory to be erased and reprogrammed without affecting other blocks. Bus Operation
READ
The ACT-F512K32 has two control functions, both of which must be logically active, to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data to the output pins of the chip selected. Figure 7 illustrates AC read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic high level (V IH), output from the device is disabled. Output pins are placed in a high impedance state.
STANDBY MODE
The ACT-F512K32 standby mode consumes less than 6.5 mA. In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed.
WRITE
Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy an addressable memory location. The register is a latch used to store the command, along with address and data information needed to execute the command. The command register is written by bringing WE to a logic low level (V IL), while CE is low and OE is at V IH. Addresses are latched on the falling edge of WE or CE, whichever happens later. Data is latched on the rising edge of the WE or CE whichever occurs first. Standard microprocessor write timings are used. Refer to AC Program Characteristics and Waveforms, Figures 3, 8and13.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. T able 3 defines these register command sequences. READ/RESET COMMAND
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard Microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Figure 7 for the specific timing parameters.
Table 1 – Bus Operations
Operation CE OE WE A0A1A6A9I/O READ L L H A0A1A6A9DOUT ST ANDBY H X X X X X X HIG
H Z OUTPUT DISABLE L H H X X X X HIG
H Z WRITE L H L A0A1A6A9D IN ENABLE SECTOR
PROTECT
L V ID L X X X V ID X
VERIFY SECTOR
PROTECT L L H L H L V ID Code
Table 2 – Sector Addresses Table
A18A17A16Address Range
SA000000000h – 0FFFFh
SA100110000h – 1FFFFh
SA201020000h – 2FFFFh
SA301130000h – 3FFFFh
SA410040000h – 4FFFFh
SA510150000h – 5FFFFh
SA611060000h – 6FFFFh
SA711170000h – 7FFFFh
timer is reset. Any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous command string. Loading the sector erase buffer may be done in any sequence and with any number of sectors (1 to 8). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. Post Erase data state is all "1"s.
The automatic sector erase begins after the 80μs time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on D7 is “1" at which time the device returns to read mode. During the execution of the Sector Erase command, only the Erase Suspend and Erase Resume commands are allowed. All other commands will reset the device to read mode. Data Polling must be performed at an address within any of the sectors being erased.
Data Protection
The ACT-F512K32 is designed to offer protection against accidental erasure or programming caused by spurious system level singles that may exist during power transitions. During power up the device automatically resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the memory content only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise.
LOW V cc WRITE INHIBIT
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for V CC less than 3.2V (typically 3.7V). If V CC WRITE PULSE GLITCH PROTECTION Noise pulses of less than 5ns (typical) on OE, CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding anyone of OE = V IL, CE =V IH or WE = V IH. T o initiate a write cycle CE and WE must be logical zero while OE is a logical one. POWER-UP WRITE INHIBIT Power-up of the device with WE = CE = V IL and OE= V IH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Write Operation Status D7 DATA POLLING The ACT-F512K32 features Data Polling as a method to indicate to the host that the internal algorithms are in progress or completed. During the program algorithm, an attempt to read the device will produce compliment data of the data last written to D7. During the erase algorithm, an attempt to read the device will produce a "0" at the D7 Output. Upon completion of the erase algorithm an attempt to read the device will produce a "1" at the D7 Output. For chip Erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data polling must be performed at a sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the algorithm operation is close to being completed, data pins (D7) change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on D7 at one instance of time and then that byte's valid data at the next instant of time. Depending on when the system samples the D7 Output, it may read the status or valid data. Even if the device has completed internal algorithm operation and D7 has a valid data, the data outputs on D0 - D6 may be still invalid. The valid data on D0-D7 will be read on the successive read attempts. The Data Polling feature is only active during the programming algorithm, erase algorithm, or sector erase time-out. See Figures 6 and 10 D6 TOGGLE BIT The ACT-F512K32 also features the "Toggle Bit" as a method to indicate to the host system that algorithms are in progress or completed. During a program or erase algorithm cycle, successive attempts to read data from the device will result in D6 toggling between one and zero. Once the program or erase algorithm cycle is completed, D6 Will stop toggling and valid data will be read on successive attempts. During programming the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase the T oggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time out. See Figure 1 and 5. D5 EXCEEDED TIMING LIMITS D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will produce a "1". The Program or erase cycle was not successfully completed. Data Polling is the only operation function of the device under this condition. The CE circuit will partially power down the device under these conditions by approximately 8 mA per chip. The OE and WE pins will control the output disable functions as shown in T able 1. T o reset the device, write the reset command sequence to the device. This allows the system to continue to use the other active sectors in the device. D3 SECTOR ERASE TIMER After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the T oggle Bit indicates the device has been written with a valid erase command, D3 may be used to determine if the sector erase timer window is still open. If D3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3 is low ("0"), the device will accept additional sector erase commands. T o ensure the command has been accepted, the software should check the status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second status check, the command may not have been accepted. See Table 4 Sector Protection Algorithims SECTOR PROTECTION The ACT-F512K32 features hardware sector protection which will disable both program and erase operations to an individual sector or any group of sectors. T o activate this mode, the programming equipment must force V ID on control pin OE and address pin A9. The sector addresses should be set using higher address lines A18, A17, and A16. The protection mechanism begins on the falling edge of the WE pulse and is terminated with the rising edge of the same.To verify programming of the protection circuitry, the programming equipment must force V ID on address pin A9 with CE and OE at V IL and WE at V IH. Scanning the sector addresses (A16, A17, and A18) while (A6, A1, A0) = (0, 1, 0,) will produce a logical "1" code at device output D0 for a protected sector. Otherwise the device will read 00H for unprotected sector. In this mode, the lower order addresses, except for 0, A1, and A6 are don't care. It is also possible to verify if a sector is protected during the sector protection operation. This is done by setting A6 = CE = OE = V IL and WE = V IH (A9 remains high at V ID). Reading the device at address location XXX2H, where the higher order addresses (A L8, A17, and A16) define a particular sector, will produce 01H at data outputs (D0 - D7) for a protected sector. SECTOR UNPROTECT The ACT-F512K32 also features a sector unprotect mode, so that a protected sector may be unprotected to incorporate any changes in the code. All sectors should be protected prior to unprotecting any sector. To activate this mode, the programming equipment must force Vid on control pins OE, CE, and address pin A9. The address pins A6, A16, and A12 should be set to V IH. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. It is also possible to determine if a sector is unprotected in the system by writing the autoselect command and A6 is set at V IH. Performing a read operation at address location XXX2H, where the higher order addresses (A18, A17, and A16) define a particular sector address, will produce 00H at data outputs (D0-D7) for an unprotected sector. Start Read Byte D 0-D 7Address = VA D 6 = Toggle D 5 = 1Read Byte D 0-D 7Address = VA Fail Pass Yes No No Yes No ? D 6 =Toggle?(Note 1) Yes VA = Byte Address for Programming = Any of the Sector Addresses within the sector being erased during sector erase operation = XXXXH during Chip Erase Figure 5 Toggle Bit Algorithm Start Read Byte D 0-D 7Address = VA D 7 = Data D 5 = 1Read Byte D 0-D 7Address = VA Fail Pass Yes No No Yes No D 7 =Toggle?(Note 1) Yes Figure 6 Data Polling Algorithm Note 1. D 6 is rechecked even if D 5 = "1" because D 6 may stop toggling at the same time as D 5 changes to "1".Note 1. D 7 is rechecked even if D 5 = "1" because D 7 may change simultaneously with D 5. VA = Byte Address for Programming = Any of the Sector Addresses within the sector being erased during sector erase operation = XXXXH during Chip Erase ? ? ? Pin Numbers & Functions 66 Pins — PGA Pin#Function Pin#Function Pin#Function Pin#Function 1I/O 818A 1535I/O 2552WE 32I/O 919Vcc 36I/O 2653CE 33I/O 1020CE 137A 754GND 4A 1421NC 38A 1255I/O 195A 1622I/O 339NC 56I/O 316A 1123I/O 1540A 1357I/O 307A 024I/O 1441A 858I/O 298A 1825I/O 1342I/O 1659I/O 289I/O 026I/O 1243I/O 1760A 110I/O 127OE 44I/O 1861A 211I/O 228A 1745V CC 62A 312WE 229WE 146CE 463I/O 2313CE 230I/O 747WE 464I/O 2214GND 31I/O 648I/O 2765I/O 2115I/O 1132I/O 549A 466 I/O 20 16A 1033I/O 450A 517 A 9 34 I/O 24 51 A 6 1.085 SQ 1.000.600 1.000 .100 .020.016 .100 .180TYP 1.0301.040 .160Pin 56 Pin 66 Pin 11 Pin 1 Bottom View (P7 & P3) MAX MAX "P3" — 1.08" SQ PGA Type (without shoulder) Package "P7" — 1.08" SQ PGA Type (with shoulder) Package 1.0301.040 .020.016 .100 .025.185MAX Side View (P7) Side View (P3) .050 .180TYP .035 All dimensions in inches Ordering Information Model Number DESC Drawing Number Speed Package ACT–F512K32N–060P3Q5962–9461205HXX*60 ns PGA ACT–F512K32N–070P3Q5962–9461204HXX70 ns PGA ACT–F512K32N–090P3Q5962–9461203HXX90 ns PGA ACT–F512K32N–120P3Q5962–9461202HXX120 ns PGA ACT–F512K32N–150P3Q5962–9461201HXX150 ns PGA ACT–F512K32N–060P7Q5962–9461205HUX*60 ns PGA ACT–F512K32N–070P7Q5962–9461204HUX70 ns PGA ACT–F512K32N–090P7Q5962–9461203HUX90 ns PGA ACT–F512K32N–120P7Q5962–9461202HUX120 ns PGA ACT–F512K32N–150P7Q5962–9461201HUX150 ns PGA ACT–F512K32N–060F5Q5962–9461205HMX*60 ns CQFP ACT–F512K32N–070F5Q5962–9461204HMX70 ns CQFP ACT–F512K32N–090F5Q5962–9461203HMX90 ns CQFP ACT–F512K32N–120F5Q5962–9461202HMX120 ns CQFP ACT–F512K32N–150F5Q5962–9461201HMX150 ns CQFP * Pending Part Number Breakdown ACT–F512K32N–090F5Q Aeroflex Circuit Technology Memory Type F = FLASH EEPROM Memory Depth Options Memory Width, Bits N = None Memory Speed, ns Package Type & Size Surface Mount Packages Thru-Hole Packages F5 = .88"SQ 68 Lead Single-Cavity CQFP P3 = 1.075"SQ PGA 66 Pins W/O Shoulder P7 = 1.075"SQ PGA 66 Pins With Shoulder C = Commercial T emp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military T emp, -55°C to +125°C M = Military T emp, -55°C to +125°C, Screened * Q = MIL-PRF-38534 Compliant/SMD if applicable Screening *Screened to the individual test methods of MIL-STD-883 Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553 Specification subject to change without notice