ATTINY20-CCU;ATTINY20-MMH;ATTINY20-SSU;ATTINY20-XU;ATTINY20-XUR;中文规格书,Datasheet资料
Features
?High Performance, Low Power AVR? 8-bit Microcontroller ?Advanced RISC Architecture
–112 Powerful Instructions – Most Single Clock Cycle Execution –16 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 12 MIPS Throughput at 12 MHz
?Non-volatile Program and Data Memories
–2K Bytes of In-System Programmable Flash Program Memory
–128 Bytes Internal SRAM
–Flash Write/Erase Cycles: 10,000
–Data Retention: 20 Years at 85o C / 100 Years at 25o C
?Peripheral Features
–One 8-bit Timer/Counter with Two PWM Channels
–One 16-bit Timer/Counter with Two PWM Channels
–10-bit Analog to Digital Converter
?8 Single-ended Channels
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
–Master/Slave SPI Serial Interface
–Slave TWI Serial Interface
?Special Microcontroller Features
–In-System Programmable
–External and Internal Interrupt Sources
–Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes –Enhanced Power-on Reset Circuit
–Internal Calibrated Oscillator
?I/O and Packages
–14-pin SOIC/TSSOP: 12 Programmable I/O Lines
–15-ball UFBGA: 12 Programmable I/O Lines
–20-pad VQFN: 12 Programmable I/O Lines
?Operating Voltage:
–1.8 – 5.5V
?Programming Voltage:
–5V
?Speed Grade
–0 – 4 MHz @ 1.8 – 5.5V
–0 – 8 MHz @ 2.7 – 5.5V
–0 – 12 MHz @ 4.5 – 5.5V
?Industrial Temperature Range
?Low Power Consumption
–Active Mode:
?200 μA at 1 MHz and 1.8V
–Idle Mode:
?25 μA at 1 MHz and 1.8V
–Power-down Mode:
?< 0.1 μA at 1.8V 8-bit Microcontroller
with 2K Bytes
In-System Programmable
ATtiny20
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1.Pin Configurations
Figure 1-1.
Pinout of ATtiny20
1.1
Pin Description
1.1.1
VCC
Supply voltage.
1.1.2GND
Ground.
Table 1-1.
Pinout ATtiny20 in UFBGA.
1
234A PA5
PA6PB2B PA4PA7PB1PB3C PA3PA2PA1PB0D
PA0
GND
GND
VCC
1234567
141312111098
VCC
(PCINT8/TPICLK/T0/CLKI) PB0
(PCINT9/TPIDATA/MOSI/SDA/OC1A) PB1
(PCINT11/RESET) PB3
(PCINT10/INT0/MISO/OC1B/OC0A/CKOUT) PB2(PCINT7/SCL/SCK/T1/ICP1/OC0B/ADC7) PA7
(PCINT6/SS/ADC6) PA6
GND
PA0 (ADC0/PCINT0)
PA1 (ADC1/AIN0/PCINT1)PA2 (ADC2/AIN1/PCINT2)PA3 (ADC3/PCINT3)PA4 (ADC4/PCINT4)PA5 (ADC5/PCINT5)
SOIC/TSSOP
12345
VQFN
1514131211
2019181716678910
NOTE
Bottom pad should be soldered to ground.DNC: Do Not Connect
D N C D N C G N D V C C D N C PA7 (ADC7/OC0B/ICP1/T1/SCL/SCK/PCINT7)PB2 (CKOUT/OC0A/OC1B/MISO/INT0/PCINT10)PB3 (RESET/PCINT11)
PB1 (OC1A/SDA/MOSI/TPIDATA/PCINT9)PB0 (CLKI/T0/TPICLK/PCINT8)
D N C D N C D N C P A 5P A 6
Pin 16: PA6 (ADC6/SS/PCINT6)Pin 17: PA5 (ADC5/PCINT5)
(PCINT4/ADC4) PA4(PCINT3/ADC3) PA3(PCINT2/AIN1/ADC2) PA2(PCINT1/AIN0/ADC1) PA1
(PCINT0/ADC0) PA0
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1.1.3
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min-imum pulse length is given in Table 20-4 on page 175. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.1.4
Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,even if the clock is not running.
Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described in “Alternate Port Functions” on page 49.
1.1.5
Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny20, as listed on page 39.
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2.Overview
ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny20achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.Figure 2-1.
Block Diagram
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
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The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.ATtiny20 provides the following features:?2K bytes of in-system programmable Flash ?128 bytes of SRAM
?Twelve general purpose I/O lines ?16 general purpose working registers
?An 8-bit Timer/Counter with two PWM channels ?A 16-bit Timer/Counter with two PWM channels ?Internal and external interrupts ?An eight-channel, 10-bit ADC
?A programmable Watchdog Timer with internal oscillator ?A slave two-wire interface
?A master/slave serial peripheral interface ?An internal calibrated oscillator
?Four software selectable power saving modes
The device includes the following modes for saving power:
?Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt system to continue functioning
?ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC
?Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset
?Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer.
The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits.
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3.General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at https://www.wendangku.net/doc/6d16578344.html,/avr.
3.2Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.
3.3Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch ? and QMatrix ? acquisi-tion methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors.The application then calls the API to retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more informa-tion and details of implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
3.5Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology.
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4.CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories,perform calculations, control peripherals, and handle interrupts.
4.1Architectural Overview
Figure 4-1.
Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc-tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File – in one clock cycle.
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Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera-tion, the Status Register is updated to reflect information about the result of the operation.Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size and the usage of the SRAM. All user programs must initial-ize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the four different addressing modes supported in the AVR architecture.The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-ters, SPI, and other I/O functions. The I/O memory can be accessed as the data space locations,0x0000 - 0x003F.
4.2ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See document “AVR Instruction Set” and section “Instruction Set Sum-mary” on page 210 for a detailed description.
4.3Status Register
The Status Register contains information about the result of the most recently executed arithme-tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in document “AVR Instruction Set” and section “Instruction Set Summary” on page 210. This will in many cases remove the need for using the dedicated compare instructions,resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
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4.4
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
?One 8-bit output operand and one 8-bit result input ?Two 8-bit output operands and one 8-bit result input ?One 16-bit output operand and one 16-bit result input
Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU.Figure 4-2.
AVR CPU General Purpose Working Registers
Note:
A typical implementation of the AVR register file includes 32 general prupose registers but
ATtiny20 implements only 16 registers. For reasons of compatibility the registers are numbered R16:R31 and not R0:R15.
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.
4.4.1
The X-register, Y-register, and Z-register
Registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.
7
R16R17
General R18Purpose …Working R26X-register Low Byte Registers
R27X-register High Byte R28Y-register Low Byte R29Y-register High Byte R30Z-register Low Byte R31
Z-register High Byte
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Figure 4-3.The X-, Y-, and Z-registers
In different addressing modes these address registers function as automatic increment and automatic decrement (see document “AVR Instruction Set” and section “Instruction Set Sum-mary” on page 210 for details).
4.5Stack Pointer
The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack grows from higher memory locations to lower memory loca-tions. This means that the PUSH instructions decreases and the POP instruction increases the stack pointer value.
The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack space must be defined by the program before any subroutine calls are exe-cuted or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by one when data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack pointer and the number of bits implemented is device dependent. In some AVR devices all data memory can be addressed using SPL, only. In this case, the SPH register is not implemented.
The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of SRAM. See Figure 5-1 on page 16.
4.6Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk CPU , directly generated from the selected clock source for the chip. No internal clock division is used.
15
XH
XL
0X-register 7
7
R27
R2615
YH
YL 0Y-register
7
7
R29
R28
15
ZH
ZL 0Z-register
7
7
R31
R30
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