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HS2-117RH-8中文资料

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FN4560.7

HS-117RH

Radiation Hardened

Adjustable Positive Voltage Regulator

The Radiation Hardened HS-117RH is an adjustable positive voltage linear regulator capable of operating with input voltages up to 40VDC. The output voltage is adjustable from 1.2V to 37V with two external resistors. The device is capable of sourcing from 5mA to 1.25A PEAK (0.5 A PEAK for the TO-39 package). Protection is provided by the on-chip thermal shutdown and output current limiting circuitry.The Intersil HS-117RH has advantages over other industry standard types, in that circuitry is incorporated to minimize the effects of radiation and temperature on device stability.Constructed with the Intersil dielectrically isolated Rad Hard Silicon Gate (RSG) process, the HS-117RH is immune to single event latch-up and has been specifically designed to provide highly reliable performance in harsh radiation environments.

Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering.

Detailed electrical specifications for the HS-117RH are contained in SMD 5962-99547. A “hot-link” is provided on our website for downloading.

Pinouts

HS2-117RH (TO-39 CAN)

BOTTOM VIEW

HS9S-117RH (TO-257AA FLANGE MOUNT)

TOP VIEW

Features

?Electrically Screened to DSSC SMD # 5962-99547?QML Qualified per MIL-PRF-38535 Requirements ?Radiation Environment -300 krad (Si) (Max)-Latch-up Immune ?Superior Temperature Stability

?Overcurrent and Overtemperature Protection

Applications

?Adjustable Linear Voltage Regulators ?Adjustable Linear Current Regulators

HSYE-117RH (SMD.5 CLCC)

BOTTOM VIEW

NOTE:No current JEDEC outline for the SMD.5 package. Refer to SMD for package dimensions. The TO-257 is a totally isolated metal package.

2

13OUT

ADJUST IN ADJUST

OUT IN 321

Ordering Information

ORDERING NUMBER INTERNAL MKT. NUMBER TEMP. RANGE

(o C)5962F9954701VUC HS2-117RH-Q -55 to 1255962F9954701QUC HS2-117RH-8-55 to 1255962F9954701VXC HS9S-117RH-Q -55 to 1255962F9954701QXC HS9S-117RH-8-55 to 1255962F9954701VYC

HSYE-117RH-Q -55 to 1255962F9954701QYC HSYE-117RH-8-55 to 125HS2-117RH/Proto HS2-117RH/Proto -55 to 125HS9S-117RH/Proto HS9S-117RH/Proto -55 to 125HSYE-117RH/Proto

HSYE-117RH/Proto

-55 to 125

1 - ADJUST

2 - IN

3 - OUT

1

2

3

Data Sheet

October 2003

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143|Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright ? Intersil Americas Inc. 2003. All Rights Reserved.

All other trademarks mentioned are the property of their respective owners.

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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at http://www.wendangku.net/doc/6e6eae86cc22bcd126ff0c88.html/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see http://www.wendangku.net/doc/6e6eae86cc22bcd126ff0c88.html

Die Characteristics

DIE DIMENSIONS

2616μm x 2794μm (103 mils x 110 mils)483μm ±25.4μm (19 mils ±1 mil)INTERFACE MATERIALS Glassivation

Type: Silox (SiO 2)

Thickness: 8.0k ? ±1.0k ?Top Metallization Type: AlSiCu

Thickness: 16.0k ? ±2k ?

Substrate

Radiation Hardened Silicon Gate,Dielectric Isolation Backside Finish Gold

ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased (DI)

ADDITIONAL INFORMATION Worst Case Current Density <2.0 x 105 A/cm 2Transistor Count 95

Metallization Mask Layout

HS-117RH

V

HS2-117RH-8中文资料

OUT

V OUT V IN

V IN

ADJ

V OUTK

HS-117RH