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UDG--01112

OUT VDD IN ENBL

VDD PGND

OU T AGND

INPUT/OUTPUT TABLE UCC27321,UCC27322UCC37321,UCC37322

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SINGLE 9-A HIGH SPEED LOW-SIDE MOSFET DRIVER WITH ENABLE

Check for Samples:UCC27321,UCC27322,UCC37321,UCC37322

FEATURES

APPLICATIONS ?Industry-Standard Pin-Out With Addition of

?Switch Mode Power Supplies Enable Funtion

?DC/DC Converters ?High-Peak Current Drive Capability of ±9A at

?Motor Controllers the Miller Plateau Region Using TrueDrive

?Class-D Switching Amplifiers ?Efficient Constant Current Sourcing Using a

?Line Drivers Unique BiPolar &CMOS Output Stage

?Pulse Transformer Driver ?TTL/CMOS Compatible Inputs Independent

of Supply Voltage

DESCRIPTION ?20-ns Typical Rise and Fall Times with 10-nF

The UCC37321/2family of high-speed drivers deliver Load

9A of peak drive current in an industry standard pinout.These drivers can drive the largest of ?Typical Propagation Delay Times of 25ns

MOSFETs for systems requiring extreme Miller With Input Falling and 35ns with Input

current due to high dV/dt transitions.This eliminates Rising

additional external circuits and can replace multiple ?4-V to 15-V Supply Voltage

components to reduce space,design complexity and ?Available in Thermally Enhanced MSOP

assembly cost.Two standard logic options are PowerPAD?Package With 4.7°C/W θjc

offered,inverting (UCC37321)and noninverting (UCC37322).?Rated From –40°C to 105°C

?Pb-Free Finish (NiPdAu)on SOIC-8and

PDIP-8Packages

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UCC27321,UCC27322

UCC37321,UCC37322

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Using a design that inherently minimizes shoot-through current,the outputs of these can provide high gate drive current where it is most needed at the Miller plateau region during the MOSFET switching transition.A unique hybrid output stage paralleling bipolar and MOSFET transistors(TrueDrive)allows efficient current delivery at low supply voltages.With this drive architecture,UCC37321/2/3can be used in industry standard6-A,9-A and many 12-A driver https://www.wendangku.net/doc/6017927779.html,tch up and ESD protection circuitries are also included.Finally,the UCC37321/2 provides an enable(ENBL)function to have better control of the operation of the driver applications.ENBL is implemented on pin3which was previously left unused in the industry standard pin-out.It is internally pulled up to Vdd for active high logic and can be left open for standard operation.

In addition to SOIC-8(D)and PDIP-8(P)package offerings,the UCC37321/2also comes in the thermally enhanced but tiny8-pin MSOP PowerPAD?(DGN)package.The PowerPAD?package drastically lowers the thermal resistance to extend the temperature operation range and improve the long-term reliability.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range(unless otherwise noted)(1)(2)

UCCx732x UNIT Supply voltage,V DD-–0.3to16V Output current(OUT)DC,I OUT_DC0.6A

–0.3V to6V or V DD+0.3

Input voltage(IN),V IN

(whichever is larger)

–0.3V to6V or V DD+0.3

Enable voltage(ENBL)

(whichever is larger)

D package650mW Power dissipation at T A=25°C DGN package3W

P package350mW Junction operating temperature,T J–55to150°C Storage temperature,T stg–65to150°C Lead temperature(soldering,10sec.)300°C (1)Stresses beyond those listed under“absolute maximum ratings”may cause permanent damage to the device.These are stress ratings

only,and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions”is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)All voltages are with respect to GND.Currents are positive into,negative out of the specified terminal.

ORDERING INFORMATION

PACKAGED DEVICES

OUTPUT TEMPERATURE

MSOP-8PowerPAD

CONFIGURATION RANGE T A=T J SOIC-8(D)(1)PDIP-8(P)

(DGN)(1)

–40°C to+105°C UCC27321D UCC27321DGN UCC27321P Inverting

0°C to+70°C UCC37321D UCC37321DGN UCC37321P

–40°C to+105°C UCC27322D UCC27322DGN UCC27322P NonInverting

0°C to+70°C UCC37322D UCC37322DGN UCC37322P

(1)D(SOIC–8)and DGN(PowerPAD–MSOP)packages are available taped and reeled.Add R suffix to device type(e.g.UCC37321DR,

UCC37322DGNR)to order quantities of2,500devices per reel.

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UCC27321,UCC27322

UCC37321,UCC37322 https://www.wendangku.net/doc/6017927779.html, SLUS504G–SEPTEMBER2002–REVISED MAY2013 ELECTRICAL CHARACTERISTICS

V DD=4.5V to15V,T A=–40°C to105°C for UCC2732x,T A=0°C to70°C for UCC3732x,T A=T J,(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input(IN)

V IN_H,logic1input threshold2V

V IN_H,logic1input threshold1V

Input current0V≤V IN≤V DD–10010μA

Output(OUT)

Peak output current(1)(2)V DD=14V,9A

V OH,output high level V OH=V DD–V OUT,I OUT=–10mA150300mV

V OL,output high level I OUT=10mA1125mV

Output resistance high(3)I OUT=–10mA,V DD=14V1525Ω

Output resistance low(3)I OUT=10mA,V V DD=14 1.1 2.2Ω

Latch--up protection(1)500mA

Overall

IN=LO,EN=LO,V DD=15V150225

IN=HI,EN=LO,V DD=15V440650

UCC37321

UCC27321IN=LO,EN=HI,V

=15V370550

IN=HI,EN=HI,V DD=15V370550

I DD,static operating currentμA

IN=LO,EN=LO,V DD=15V150225

IN=HI,EN=LO,V DD=15V450650

UCC37322

UCC27322IN=LO,EN=HI,V

=15V75125

IN=HI,EN=HI,V DD=15V6751000

Enable(ENBL)

V IN_H,high-level input voltage LO to HI transition 1.7 2.2 2.7V

V IN_L,low-level input voltage HI to LO transition 1.1 1.6 2.0

V Hysteresis0.250.550.90

R ENBL,enable impedance V DD=14V,ENBL=GND75100135kΩ

t D3,propagation delay time(4)C LOAD=10nF6090

t D4,propagation delay time(4)C LOAD=10nF6090

Switching Time(5)

t R,rise time(OUT)C LOAD=10nF2070

t F,fall time(OUT)C LOAD=10nF2030

t D1,propagation delay,IN rising(IN to OUT)C LOAD=10nF2570

t D2,propagation delay,IN falling(IN to OUT)C LOAD=10nF3570

(1)Ensured by design.Not tested in production.

(2)The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel.The peak output current rating is the

combined current from the bipolar and MOSFET transistors.

(3)The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel.The output resistance is the R DS(ON)of the

MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

(4)See Figure2.

(5)See Figure1for switching waveforms.

0V OUT V DD

0V 5V

0V IN

OUT

V DD UCC27321,UCC27322UCC37321,UCC37322

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A.The 20%and 80%thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET

transition through the Miller regions of operation.

Figure 1.Switching Waveforms for (a)Inverting Input to (b)Output Times

A.The 20%and 80%thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET

transition through the Miller regions of operation.

Figure 2.Switching Waveform for Enable to Output

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1 2 3 48 7 6 5

VDD

IN ENBL AGND VDD OUT OUT PGND

PDIP(P) PACKAGE (TOP VIEW)

SOIC(D) OR MSOP(DGN)PACKAGE

(TOP

VIEW)

VDD

OUT

PGND

VDD

ENBL

AGND

UCC27321,UCC27322

UCC37321,UCC37322

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POWER DISSIPATION RATING TABLE

Power Rating Derating Factor PACKAGE SUFFIXθjc(°C/W)θja(°C/W)(mW)Above

T A=70°C(1)70°C(mW/°C)(1) SOIC-8D4284–160(2)344–655(2) 6.25–11.9(2)

PDIP-8P491105009

MSOP PowerPAD-8DGN 4.750–59137017.1

(1)125°C operating junction temperature is used for power rating calculations

(2)The range of values indicates the effect of pc-board.These values are intended to give the system designer an indication of the best

and worst case conditions.In general,the system designer should attempt to use larger traces on the pc-board where possible in order to spread the heat away form the device more effectively.For additional information on device temperature management,please refer to Packaging Information section of the Power Supply Control Products Data Book,(Ti Literature Number SLUD003).

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME NO.

The AGND and the PGND should be connected by a single thick trace directly under the device.

There should be a low ESR,low ESL capacitor of0.1μF between VDD(pin8)and PGND and a

seperate0.1-μF capacitor between VDD(pin1)and AGND.The power MOSFETs should be located AGND4–

on the PGND side of the device while the control circuit should be on the AGND side of the device.

The control circuit ground should be common with the AGND while the PGND should be common

with the source of the power FETs.

Enable input for the driver with logic compatible threshold and hysteresis.The driver output can be ENBL3I enabled and disabled with this pin.It is internally pulled up to V DD with100-kΩresistor for active high

operation.The output state when the device is disabled will be low regardless of the input state.

IN2I Input signal of the driver which has logic compatible threshold and hysteresis.

Driver outputs that must be connected together externally.The output stage is capable of providing OUT6,7O

9-A peak drive current to the gate of a power MOSFET.

Common ground for output stage.This ground should be connected very closely to the source of the PGND5–power MOSFET which the driver is driving.Grounds are separated to minimize ringing affects due to

output switching di/dt which can affect the input threshold.

Supply voltage and the power input connections for this device.Three pins must be connected

VDD1,8I

together externally.

UCC27321,UCC27322

UCC37321,UCC37322

SLUS504G–SEPTEMBER2002–REVISED https://www.wendangku.net/doc/6017927779.html,

APPLICATION INFORMATION

General Information

The UCC37321and UCC37322drivers serve as an interface between low-power controllers and power MOSFETs.They can also be used as an interface between DSPs and power MOSFETs.High-frequency power supplies often require high-speed,high-current drivers such as the UCC37321/2family.A leading application is the need to provide a high power buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT switching devices.In other cases,the device drives the power device gates through a drive transformer.Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry.

The inverting driver(UCC37321)is useful for generating inverted gate drive signals from controllers that have only outputs of the opposite polarity.For example,this driver can provide a gate signal for ground referenced, N-channel synchronous rectifier MOSFETs in buck derived converters.This driver can also be used for generating a gate drive signal for a P-channel MOSFET from a controller that is designed for N-channel applications.

MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device directly drive the switching devices for one or more reasons.The PWM device may not have the brute drive capability required for the intended switching MOSFET,limiting the switching performance in the application.In other cases theremay be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load.Also,newer devices that target the highest operating frequencies may not incorporate onboard gate drivers at all.Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC37321/2.Finally,the control device may be under thermal stress due to power dissipation,and an external driver can help by moving the heat from the controller to an external package.

Input Stage

The IN threshold has a3.3-V logic sensitivity over the full range of VDD voltages;yet,it is equally compatible with0V toVDD signals.The inputs of UCC37321/2family of drivers are designed to withstand500-mA reverse current without either damage to the device or logic upset.In addition,the input threshold turn-off of the UCC37321/2has been slightly raised for improved noise immunity.The input stage of each driver should be driven by a signal with a short rise or fall time.This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times(<200ns).The IN input of the driver functions as a digital gate,and it is not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver,the output of the driver may switch repeatedly at a high frequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down(or delay)the signal at the output.If limiting the rise or fall times to the power device is desired,then an external resistance can be added between the output of the driver and the load device,which is generally a power MOSFET gate.The external resistor may also help remove power dissipation from the device package,as discussed in the section on Thermal Considerations.

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UDG--01113

V SUPPLY

5.5V UCC27321,UCC27322UCC37321,UCC37322

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Output Stage

The TrueDrive output stage is capable of supplying ±9-A peak current pulses and swings to both VDD and GND

and can encourage even themost stubborn MOSFETs to switch.The pull-up/pull-down circuits of the driver are

constructed of bipolar and MOSFET transistors in parallel.The peak output current rating is the combined current

from the bipolar and MOSFET transistors.The output resistance is the R DS(ON)of the MOSFET transistor when

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.Each output stage

also provides a very low impedance to overshoot and undershoot due to the body diode of the internal MOSFET.

This means that in many cases,external-schottky-clamp diodes are not required.

This unique BiPolar and MOSFET hybrid output architecture (TrueDrive)allows efficient current sourcing at low

supply voltages.The UCC37321/2family delivers 9A of gate drive where it is most needed during the MOSFET

switching transition –at the Miller plateau region –providing improved efficiency gains.

Source/Sink Capabilities during Miller Plateau

Large power MOSFETs present a significant load to the control circuitry.Proper drive is required for efficient,

reliable operation.The UCC37321/2drivers have been optimized to provide maximum drive to a power MOSFET

during the Miller Plateau Region of the switching transition.This interval occurs while the drain voltage is

swinging between the voltage levels dictated by the power topology,requiring the charging/discharging of the

drain-gate capacitance with current supplied or removed by the driver device.[1]

Two circuits are used to test the current capabilities of the UCC37321/2driver.In each case external circuitry is

added to clamp the output near 5V while the device is sinking or sourcing current.An input pulse of 250ns is

applied at a frequency of 1kHz in the proper polarity for the respective test.In each test there is a transient

period where the current peaked up and then settled down to a steady-state value.The noted current

measurements are made at a time of 200ns after the input pulse is applied,after the initial transient.

The circuit in Figure 3is used to verify the current sink capability when the output of the driver is clamped around

5V,a typical value of gate-source voltage during the Miller Plateau Region.The UCC37321is found to sink 9A

at V DD =15V.

Figure 3.Sink Current Test Circuit

UDG--01114

4.5V D ADJ UCC27321,UCC27322UCC37321,UCC37322

SLUS504G –SEPTEMBER 2002–REVISED MAY https://www.wendangku.net/doc/6017927779.html,

The circuit in Figure 4is utilized to test the current source capability with the output clamped to around 5V with a

string of Zener diodes.The UCC37321is found to source 9A at V DD =15V.

Figure 4.Source Current Test Circuit

It should be noted that the current sink capability is slightly stronger than the current source capability at lower

VDD.This is due to the differences in the structure of the bipolar-MOSFET power output section,where the

current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.

In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the

turn-on capability.This helps to ensure that the MOSFET is held OFF during common power supply transients

which may turn the device back ON.

Operational Circuit Layout

It can be a significant challenge to avoid the overshoot/undershoot and ringing issues that can arise from circuit

layout.The low impedance of these drivers and their high di/dt can induce ringing between parasitic inductances

and capacitances in the circuit.Utmost care must be used in the circuit layout.

In general,position the driver physically as close to its load as possible.Place a 1-μF bypass capacitor as close

to the output side of the driver as possible,connecting it to pins 1and 8.Connect a single trace between the two

VDD pins (pin 1and pin 8);connect a single trace between PGND and AGND (pin 5and pin 4).If a ground

plane is used,it may be connected to AGND;do not extend the plane beneath the output side of the package

(pins 5–8).Connect the load to both OUT pins (pins 7and 6)with a single trace on the adjacent layer to the

component layer;route the return current path for the output on the component side,directly over the output

path.

Extreme conditions may require decoupling the input power and ground connections from the output power and

ground connections.The UCCx7321/2has a feature that allows the user to take these extreme measures,if

necessary.There is a small amount of internal impedance of about 15Ωbetween the AGND and PGND pins;

there is also a small amount of impedance (～30Ω)between the two VDD pins.In order to take advantage of this

feature,connect a 1-μF bypass capacitor between VDD and PGND (pins 5and 8)and connect a 0.1-μF bypass

capacitor between VDD and AGND (pins 1and 4).Further decoupling can be achieved by connecting between

the two VDD pins with a jumper that passes through a 40-MHz ferrite bead and connect bias power only to pin 8.

Even more decoupling can be achieved by connecting between AGND and PGND with a pair of anti-parallel

diodes (anode connected to cathode and cathode connected to anode).

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P 0.432W I ===0.036A V 12V

21P =2CV f 2′2

1E =CV 2UCC27321,UCC27322UCC37321,UCC37322

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VDD

Although quiescent VDD current is very low,total supply current will be higher,depending on OUTA and OUTB

current and the operating frequency.Total VDD current is the sum of quiescent VDD current and the average

OUT current.Knowing the operating frequency and the MOSFET gate charge (Qg),average OUT current can be

calculated from:

I OUT =Qg x f,where f is frequency

For the best high-speed circuit performance,two V DD bypass capacitors are recommended to prevent noise

problems.The use of surface mount components is highly recommended.A 0.1-μF ceramic capacitor should be

located closest to the VDD to ground connection.In addition,a larger capacitor (such as 1-μF)with relatively low

ESR should be connected in parallel,to help deliver the high current peaks to the load.The parallel combination

of capacitors should present a low impedance characteristic for the expected current levels in the driver

application.

Drive Current and Power Requirements

The UCC37321/2family of drivers are capable of delivering 9-A of current to a MOSFET gate for a period of

several hundred nanoseconds.High peak current is required to turn an N-channel device ON quickly.Then,to

turn the device OFF,the driver is required to sink a similar amount of current to ground.This repeats at the

operating frequency of the power device.An N-channel MOSFET is used in this discussion because it is the

most common type of switching device used in high frequency power conversion equipment.

References 1and 2contain detailed discussions of the drive current required to drive a power MOSFET and

other capacitive-input switching devices.Much information is provided in tabular form to give a range of the

current required for various devices at various frequencies.The information pertinent to calculating gate drive

current requirements will be summarized here;the original document is available from the TI website.

When a driver device is tested with a discrete,capacitive load it is a fairly simple matter to calculate the power

that is required from the bias supply.The energy that must be transferred from the bias supply to charge the

capacitor is given by:

,where C is the load capacitor and V is the bias voltage feeding the driver.

There is an equal amount of energy transferred to ground when the capacitor is discharged.This leads to a

power loss given by the following:

,where f is the switching frequency.

This power is dissipated in the resistive elements of the circuit.Thus,with no external resistor between the driver

and gate,this power is dissipated inside the driver.Half of the total power is dissipated when the capacitor is

charged,and the other half is dissipated when the capacitor is discharged.An actual example using the

conditions of the previous gate drive waveform should help clarify this.

With V DD =12V,C LOAD =10nF,and f =300kHz,the power loss can be calculated as:

P =10nF ×(12)2×(300kHz)=0.432W

With a 12-V supply,this would equate to a current of:

UCC27321,UCC27322

UCC37321,UCC37322

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The switching load presented by a power MOSFETcan be converted to an equivalent capacitance by examining the gate charge required to switch the device.This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states.Most manufacturers provide specifications that provide the typical and maximum gate charge,in nC,to switch the device under specified https://www.wendangku.net/doc/6017927779.html,ing the gate charge Qg,one can determine the power that must be dissipated when charging a capacitor.This is done by using the equivalence Qg=CeffV to provide the following equation for power:

P=C×V2×f=Qg×V×f

This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage.

Enable

UCC37321/2provides an Enable input for improved control of the driver operation.This input also incorporates logic compatible thresholds with hysteresis.It is internally pulled up to VDD with100-kΩresistor for active high operation.When ENBL is high,the device is enabled and when ENBL is low,the device is disabled.The default state of the ENBL pin is to enable the device and therefore can be left open for standard operation.The output state when the device is disabled is low regardless of the input state.See the truth table below for the operation using enable logic.

ENBL input is compatible with both logic signals and slow changing analog signals.It can be directly driven or a power-up delay can be programmed with a capacitor between ENBL and AGND.

Table1.Input/Output Table

ENBL IN OUT

000

010

INVERTING

UCC37321101

110

000

NON--010

INVERTING

100

UCC37322

111

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THERMAL INFORMATION

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package.In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits.The UCC37321/2family of drivers is available in three different packages to cover a range of application requirements.

As shown in the power dissipation rating table,the SOIC-8(D)and PDIP-8(P)packages each have a power rating of around0.5W with T A=70°C.This limit is imposed in conjunction with the power derating factor also given in the table.Note that the power dissipation in our earlier example is0.432W with a10-nF load,12VDD, switched at300kHz.Thus,only one load of this size could be driven using the D or P package.The difficulties with heat removal limit the drive available in the D or P packages.

The MSOP PowerPAD-8(DGN)package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction.As illustrated in Reference3,the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package.This pad is soldered to the copper on the PC board directly underneath the device package,reducing theθjc down to4.7°C/W.Data is presented in Reference 3to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages.The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem,as summarized in Reference4.This allows a significant improvement in heatsinking over that available in theDor P packages,and is shown to more than double the power capability of the D and P packages.

Note that the PowerPAD?is not directly connected to any leads of the package.However,it is electrically and thermally connected to the substrate which is the ground of the device.

References.

1.SEM-1400,Topic2,A Design and Application Guide for High Speed Power MOSFET Gate Drive Circuits,TI

Literature No.SLUP133

2.U-137,Practical Considerations in High PerformanceMOSFET,IGBT andMCTGateDrive Circuits,by Bill

Andreycak,TI Literature No.SLUA105

3.Technical Brief,PowerPad Thermally Enhanced Package,TI Literature No.SLMA002

4.Application Brief,PowerPAD Made Easy,TI Literature No.SLMA004