DDU12H-XXMC3中文资料

5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H)

FUNCTIONAL DESCRIPTION The DDU12H-series device is a 10-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by an amount determined by the device dash number (See Table). For dash numbers less than 20, the total delay of the line is measured from T1 to T10. The nominal tap-to-tap delay increment is given by one-ninth of the

total delay, and the inherent delay from IN to T1 is nominally 1.5ns. For dash numbers greater than or equal to 20, the total delay of the line is measured from IN to T10. The nominal tap-to-tap delay increment is given by one-tenth of this number.

SERIES SPECIFICATIONS

? Minimum input pulse width: 10% of total delay ? Output rise time:2ns typical ? Supply voltage:-5VDC ± 5%

? Power dissipation: 400mw typical (no load)? Operating temperature: -30° to 85° C

? Temp. coefficient of total delay: 100 PPM/°C

VCC GND

IN T1T2T3T4T10Functional diagram for dash numbers < 20

T5T6T7T8T9VCC GND

IN T1T2T3T4T10Functional diagram for dash numbers >= 20

T5T6T7T8T9?1997 Data Delay Devices

data delay devices, inc.

?3PIN DESCRIPTIONS

IN Signal Input T1-T10Tap Outputs VEE -5 Volts GND Ground DASH NUMBER SPECIFICATIONS

Part Number Total Delay (ns)Delay Per Tap (ns)DDU12H-109 ± 1.0 * 1.0 ± 0.3DDU12H-2020 ± 2.0 2.0 ± 0.4DDU12H-2525 ± 2.0 2.5 ± 0.4DDU12H-4040 ± 2.0 4.0 ± 0.5DDU12H-5050 ± 2.5 5.0 ± 1.0DDU12H-7575 ± 4.07.5 ± 1.5DDU12H-100100 ± 5.010.0 ± 2.0DDU12H-150150 ± 7.515.0 ± 2.0DDU12H-200200 ± 10.020.0 ± 2.0DDU12H-250250 ± 12.525.0 ± 2.0DDU12H-300300 ± 15.030.0 ± 2.0DDU12H-400400 ± 20.040.0 ± 2.0DDU12H-500500 ± 25.050.0 ± 2.5DDU12H-750750 ± 37.575.0 ± 4.0DDU12H-10001000 ± 50.0100.0 ± 5.0DDU12H-1500

1500 ± 75.0

150.0 ± 7.0

* Total delay is referenced to first tap output Input to first tap = 1.5ns ± 1ns

NOTE:Any dash number between 10 and 1500

not shown is also available.

APPLICATION NOTES

HIGH FREQUENCY RESPONSE

The DDU12H tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 10% of the total delay and periods as small as 20% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.

POWER SUPPLY BYPASSING

The DDU12H relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VEE to GND, located as close as possible to the VEE pin, is recommended. A wide VEE trace and a clean ground plane should be used.

DEVICE SPECIFICATIONS

TABLE 1: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage V EE-7.00.3V

Input Pin Voltage V IN V EE - 0.30.3V

Storage Temperature T STRG-55150C

Lead Temperature T LEAD300C10 sec

TABLE 2: DC ELECTRICAL CHARACTERISTICS

(0C to 75C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

High Level Output Voltage V OH-1.020-0.735V V IH = MAX,50? to -2V Low Level Output Voltage V OL-1.950-1.600V V IL = MIN, 50? to -2V High Level Input Voltage V IH-1.070V

Low Level Input Voltage V IL-1.480V

High Level Input Current I IH475μA V IH = MAX

Low Level Input Current I IL0.5μA V IL = MIN

PACKAGE DIMENSIONS

DDU12H-xx (Commercial DIP)DDU12H-xxM (Military DIP)

.020

DDU12H-xxC4 (Commercial SMD)DDU12H-xxMC4 (Military SMD)

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature:25o C ± 3o C Load:50? to -2V Supply Voltage (Vcc):-5.0V ± 0.1V C load :

5pf ± 10%Input Pulse:Standard 10KH ECL

Threshold:

(V OH + V OL ) / 2levels

(Rising & Falling)

Source Impedance:50? Max.Rise/Fall Time: 2.0 ns Max. (measured

between 20% and 80%)

Pulse Width:PW IN = 1.5 x Total Delay Period:PER IN = 10 x Total Delay

NOTE:The above conditions are for test only and do not in any way restrict the operation of the device.

Test Setup

Timing Diagram For Testing

T RISE

T FALL

PER IN

PW IN

T RISE

T FALL

20%

20%

50%50%80%80%50%

50%

V IH

V IL

V OH

V OL

INPUT SIGNAL

OUTPUT SIGNAL