MIPS32 4ksd

S e c u r e MIPS32?

4KSd

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The MIPS32processor that meets the needs of emerging secure data applications and the stringent power, security and size requirements for smart cards. This core has the performance required to implement software programmable cryptography without the need of a coprocessor, reducing S The 4KSd core is the most secure, licensable, 32-bit processor available.

T H E M O S T S E C U R E C O R E

The MIPS32? 4KSdù secure data core, with the SmartMIPS ?application specific extension (ASE) to the MIPS32 architecture,provides unprecedented performance and security for emerging secure data applications and next generation smart cards.High-performance cryptography and enhanced security features make the 4KSd core the most secure,licensable,32-bit processor.

?Extensive security features disguise processor activity tampering through power analysis and other techniques

?MIPS cryptography enhancements speed public- and secret-key cryptography algorithms

for data security without additional dedicated hardware or coprocessor modules ?Secure memory spaces protect sensitive consumer data by application and prevent unauthorized data access by rogue applications ? CorExtend? capabilities allow expert designers to further differentiate

their secure S o C applications by adding their own instructions to create unique security features ?Meets the high-performance requirements for emerging secure data markets and the small size and low-power consumption necessary for next generation smart cards ? Low interrupt latency allows the core to respond more quickly to external events ?MIPS16e ?code-compression allows usage of smaller memories, reducing power consumption and die size ?Based on the enhanced MIPS32 industry-standard architecture, with hundreds of third-party development tools and applications

At the core of the user experience.?

?core for secure data

? 2005 MIPS Technologies, Inc. All rights reserved. Specifications and information subject to change without notice. The product described in this document is subject to continuous development and improvement. MIPS , MIPS32, MIPS16e, 4KSd, SmartMIPS , CorExtend MIPS Technologies logo, MIPS RISC CERTIFIED POWER logo, "At the core of the user experience.", are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries. All other trademarks mentioned herein are the property of their respective owners. Printed in the USA. 0605/1000/Rev1

MIPS32?

4KSd ?

Secure Data Core

MIPS32? 4KSd ?Secure Data Core:

Low-power,high-performance core for secure data

applications

Execution Core Security

Instruction Cache

Secure Cache Control

Data Cache

EJTAG

B I U

Power Mgmt.Fixed

TLB

Secure MMU The MIPS32? 4KSd?? secure data core is an integrated, fast time-to-market solution for building secure SoCs. It includes the industry-standard SmartMIPS ?ASE that provides advanced software cryptography and data security features.Special anti-tampering features resist external attacks via noninvasive techniques.The 4KSd core sets the standard for low power,software-programmable cryptography and security.

F E A T U R E S

Security Features

?Multiple techniques implemented to disguise

processor activity and resist invasion by power analysis and other non-invasive techniques ?Lowest interrupt latency of any secure 32-bit core allows faster response to external events SmartMIPS Secure ASE

?Speeds public- and secret-key cryptography algorithms and eliminates the need for

coprocessors,reducing die size and total cost ?Supports multiple encryption algorithms ?Secret key:DES,3DES and AES (Rijudael)

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Public key:RSA,elliptic curve (especially GF [2n ]) ? New cryptography standards as they become available

?Increases performance of virtual machines ?Designed to support Sun Microsystems’ Java Card ?technology Memory-Management Unit

?16 dual-entry JTLB with variable page sizes,from 16MB down to 1KB

?Workstation-class virtual memory support ?Read-only,write-only and execute-only page attributes

?Secure memory spaces protect sensitive consumer data by application and prevent unauthorized data access by rogue applications

?Each application resides in a different virtual space User Defined Instruction Set Extensions ?Maintains MIPS32 compatibility

?Supported by industry standard development tools ?Single- or multi-cycle instructions MIPS16e ?Code Compression

? Reduces application code size by up to 40%Fully Integrated Cache Controller ?Improves performance with slow memories ? Individually configurable 0–64KB instruction and data caches

?Direct-mapped,2-,3-,or 4-way set-associative (0KB,1KB,2KB,4KB,8KB,or 16KB per way)?Write-back or write-through Optional EJTAG Debugging

?May be disabled for production silicon ?Supports PC and data trace

S P E C I F I C A T I O N S Process 0.13 μm generic

Frequency

(worst case)90–211 MHz

Performance ? 322 DMIPS @ 200 MHz

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1024-bit RSA signature

generation in less

than 15 ms @ 200 MHz

Power Consumption

0.29-0.32 mW/MHz at 1.2V,excluding caches

Core Size 1.0-1.4 mm 2

, excluding caches

Note:Frequency,power consumption and size depend

upon configuration options,synthesis,silicon vendor,process and cell libraries.Worst case is slow silicon,1.08V,125C.

MIPS Technologies, Inc.1225 Charleston Road

Mountain View, CA 94043-1353phone: (650) 567-5000 fax: (650) 567-5158

MIPS Technologies B.V.Berghauser Strasse 6242859 Remscheid Germany

phone: +49 2191 900 200fax: +49 2191 900 208

MIPS Technologies Japan

Landic Toranomon Bldg. No. 23-7-8, Toranomon, Minato-ku Tokyo 105-0001 Japan phone: +81 3 5733 9541fax: +81 3 5733 9545

At the core of the user experience.?