CORESCOMM_ZB-BPSK

essential integration requirements.

To meet the -92 dBm receiver sensitivity requirement, the maximum allowable noise figure of the RF

analog front end is estimated to be 21 dB or 24 dB for the 915 or 868 MHz PHY respectively. This is based on VHDL simulation assuming AWGN channel.

Small area: 2.4k and 14.5k equivalent gate counts (using a standard cell library) for the transmitter and receiver respectively.

Low power consumption: 1.5mW (in 0.18u) when receiving a packet.

Transmitter Pin Out

ce: One bit input, the chip enable. The transmitter is active only when ce is '1'.

clk: One bit input, the transmitter clock. All synchronous logic and digital-to-analog convertors act on the rising edge of clk. The clock frequency is required to be five times the chip rate.

reset: One bit input. This pin has two functions. Together with the frame_length input described below, it may be used to reset the transmitter or to force a packet transmission.

frame_length: Seven bit input. The transmitter should be reset at power up by maintaining reset='1' and frame_length="0000000" during a rising edge of clk. On the other hand, the transmitter can be forced to transmit a packet by maintaining reset='1' with nonzero frame_length during a rising edge of clk. Then that nonzero frame_length value will be interpreted as the number of octets in the PHY payload. In

addition, after such a rising edge of clk, the tx_busy output will be '1' until the packet transmission is

completed.

bit_in: One bit input representing the subsequent data bits of the PHY payload. During tx_busy='1', the transmitter will read bit_in eight times the number of octets in the PHY payload, according to the timing provided by the bit_clk output described below.

bit_clk: One bit output. During tx_busy='1', there will be a number of positive pulses at bit_clk. The pulse duration equals one clock cycle, while the number of pulses equals the number of bits in the PHY payload.

The transmitter will read bit_in for a single data bit when clk'Event and clk='1' and bit_clk='1'.

tx_busy: One bit output indicating a packet is being transmitted. When tx_busy='1', the external circuit is required not to maintain reset='1'.

a_out: Six bit output representing the baseband pulse-shaped BPSK signal in two's complement format. Receiver Pin Out

ce: One bit input, the chip enable. The receiver is active only when ce is '1'.

clk: One bit input, the receiver clock. All synchronous logic and analog-to-digital convertors act on the rising edge of clk. The clock frequency is required to be five times the chip rate.

reset: One bit input, the synchronous reset. After enabled by ce, the receiver is required to be reset by setting reset high for one clock period.

I: Four bit input representing the quantized I-phase IF signal in two's complement format.

Q: Four bit input representing the quantized Q-phase IF signal in two's complement format.

bit_out: One bit output. Detected bits are read here.

bit_out_valid: One bit output. A rising edge of bit_out_valid indicates that a start-of-frame delimiter

immediately following a synchronization symbol has been detected, and hence the subsequent bits

detected will represent the frame length and frame data respectively. After the rising edge, there will be approximately one bit duration (i.e., 50000 or 25000 ns for the 868 or 915 MHz band respectively) until the next detected bit (i.e., the LSB of the frame length representation) is available by the receiver. A falling edge of bit_out_valid indicates that the last bit of a frame has been detected. Indeed bit_out_valid='1'

indicates presence of a data frame.

clk_out: One bit output. The waveform of clk_out is a quasi-periodic pulse train - the pulse duration

equals one clock cycle, while the duration between the rising edges of two adjacent pulses varies around one bit duration due to a timing-tracking process of the receiver. When bit_out_valid is '1', external circuit must read bit_out once every period of one bit duration for a detected bit that is available between one clock cycle before and after the rising edge of clk_out. A working example is to read bit_out when

clk'Event and clk='1' and bit_out_valid='1' and clk_out='1'.

Deliverables