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ktf16c256_512_1gx64hz_DDR3L_EDJ

1.35V DDR3L SDRAM SODIMM

EBJ81UG8EFU0Features

?DDR3L functionality and operations supported as defined in the component data sheet

ktf16c256_512_1gx64hz_DDR3L_EDJ

?204-pin, small-outline dual in-line memory module (SODIMM)

?Fast data transfer rates: PC3-12800, PC3-10600?8GB (1 Gig x 64)

?V DD = 1.35V (1.283–1.45V)?V DD = 1.5V (1.425–1.575V)

?Backward compatible with standard 1.5V (±0.075V)DDR3 systems ?V DDSPD = 3.0–3.6V

?Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals ?Dual rank

?Fixed burst chop (BC) of 4 and burst length (BL) of 8via the mode register set (MRS)

?On-board I 2C serial presence-detect (SPD) EEPROM ?Gold edge contacts ?Halogen-free ?Fly-by topology

?Terminated control, command, and address bus Figure 1: 204-Pin SODIMM (MO-268 R/C F3)

Options

Marking

?Operating temperature

–Commercial (0°C ≤ T A ≤ +70°C)None ?Package

–204-pin DIMM (lead-free/halogen-free)

F ?Frequency/CAS latency

– 1.25ns @ CL = 11 (DDR3-1600)-GN – 1.5ns @ CL = 9 (DDR3-1333)

-DJ

Table 1: Key Timing Parameters

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Table 2: Addressing

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Table 3: Part Numbers and Timing Parameters

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Pin Assignments Table 4: Pin Assignments

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Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 5: Pin Descriptions

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Table 5: Pin Descriptions (Continued)

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DQ Map

Table 6: Component-to-Module DQ Map, R/C F3 (Front)

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Table 7: Component-to-Module DQ Map, R/C F3 (Back)

ktf16c256_512_1gx64hz_DDR3L_EDJ

Functional Block Diagram Figure 2: Functional Block Diagram

ktf16c256_512_1gx64hz_DDR3L_EDJ

ktf16c256_512_1gx64hz_DDR3L_EDJ

ktf16c256_512_1gx64hz_DDR3L_EDJ

ktf16c256_512_1gx64hz_DDR3L_EDJ

ktf16c256_512_1gx64hz_DDR3L_EDJ

ktf16c256_512_1gx64hz_DDR3L_EDJ

S1#

BA[2:0]

A[14:0]

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#

CAS#: DDR3 SDRAMs

CKE1: Rank 1

ODT0: Rank 0

ODT1: Rank 1

RESET#: DDR3 SDRAMs

V

V

V

V DDSPD

V

V

Command, address and clock line terminations

CK[1:0]

CK#[1:0]

Rank 0 = U2, U3, U6, U7, U8, U11, U12, U15

Rank 1 = U4, U5, U7, U19, U13, U14, U16, U18

DD

Note: 1.The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output

driver.

8GB (x64, DR) 204-Pin 1.35V DDR3L SODIMM

Functional Block Diagram

General Description

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-

ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-

tially an 8n-prefetch architecture with an interface designed to transfer two data words

per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-

ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-

nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers

at the I/O pins.

DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals.

Fly-By Topology

DDR3 modules use faster clock speeds than earlier DDR technologies, making signal

quality more important than ever. For improved signal quality, the clock, control, com-

mand, and address buses have been routed in a fly-by topology, where each clock, con-

trol, command, and address pin on each DRAM is connected to a single trace and ter-

minated (rather than a tree structure, where the termination is off the module near the

connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-

nals can be easily accounted for by using the write-leveling feature of DDR3.

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with

JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM

Modules." These bytes identify module-specific timing parameters, configuration infor-

mation, and physical attributes. The remaining 128 bytes of storage are available for use

by the customer. System READ/WRITE operations between the master (system logic)

and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL

(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, per-

manently disabling hardware write protection. For further information refer to Micron

technical note TN-04-42, "Memory Module Serial Presence-Detect."

Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in each device's data sheet is not implied. Exposure to ab-

solute maximum rating conditions for extended periods may adversely affect reliability. Table 8: Absolute Maximum Ratings

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Table 9: Operating Conditions

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Notes: 1.Module is backward-compatible with 1.5V operation. Refer to device specification for

details and operation guidance.

2.V TT termination voltage in excess of the stated limit will adversely affect the command

and address signals’ voltage margin and will reduce timing margins.

3.T A and T C are simultaneous requirements.

4.For further information, refer to technical note TN-00-08: “Thermal Applications,”

available on Micron’s web site.

5.The refresh rate is required to double when 85°C < T C≤ 95°C.

6.The normal temperature range specifies temperatures at which all DRAM specifications

will be supported. The DRAM case temperature must be maintained at 0oC to +85oC un-

der all operating conditions.

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR3 component data sheets.

Component specifications are available on Micron’s web site. Module speed grades cor-

relate with component speed grades, as shown below.

Table 10: Module and Component Speed Grades

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Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to simulate the signal characteristics of the system's

memory bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

I DD Specifications

Table 11: DDR3 I DD Specifications and Conditions (Die Revision F)

Values are for the EDJ4208EFBG-L DDR3L SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8)

ktf16c256_512_1gx64hz_DDR3L_EDJ

Notes: 1.One module rank in the active I DD; the other rank in I DD2P0 (slow exit).

2.All ranks in this I DD condition.

3.Always fast exit.

Serial Presence-Detect EEPROM

For the latest SPD data, refer to Micron's SPD page: http://www.wendangku.net/doc/757d6316a1c7aa00b52acbde.html/SPD .

Table 12: Serial Presence-Detect EEPROM DC Operating Conditions

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Table 13: Serial Presence-Detect EEPROM AC Operating Conditions

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Notes:

1.Guaranteed by design and characterization, not necessarily tested.

2.To avoid spurious start and stop conditions, a minimum delay is placed between the fall-ing edge of SCL and the falling or rising edge of SDA.

3.For a restart condition, or following a WRITE cycle.

8GB (x64, DR) 204-Pin 1.35V DDR3L SODIMM

Serial Presence-Detect EEPROM

Module Dimensions

Figure 3: 204-Pin DDR3 SODIMM

3.8 (0.150)

ktf16c256_512_1gx64hz_DDR3L_EDJ

ktf16c256_512_1gx64hz_DDR3L_EDJ

1.8 (0.071)

2.0 (0.079) R

Front view

TYP

Notes:

1.All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2.The dimensional diagram is for reference only.

8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

http://www.wendangku.net/doc/757d6316a1c7aa00b52acbde.html/products/support Sales inquiries: 800-932-4992Micron and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.Although considered final, these specifications are subject to change, as further product development and data characterization some-times occur.

8GB (x64, DR) 204-Pin 1.35V DDR3L SODIMM

Module Dimensions

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