CY7C1020CV33-10ZXC中文资料
512K (32K x 16) Static RAM
CY7C1020CV33
Features
?Pin- and function-compatible with CY7C1020V33?Temperature Ranges —Commercial: 0°C to 70°C —Industrial: –40°C to 85°C —Automotive: –40°C to 125°C ?High
speed
—t AA = 10 ns
?CMOS for optimum speed/power ?Low active power —325 mW (max.)
?Automatic power-down when deselected ?Independent control of upper and lower bits ?Available in Pb-free and non Pb-free 44-pin TSOP II package
Functional Description
The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 1 through I/O 8), is written into the location specified on the address pins (A 0through A 14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 9 through I/O 16) is written into the location specified on the address pins (A 0 through A 14).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,then data from the memory location specified by the address pins will appear on I/O 1 to I/O 8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 9 to I/O 16. See the truth table at the back of this data sheet for a complete description of read and write modes.
The input/output pins (I/O 1 through I/O 16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).
The CY7C1020CV33 is available in standard 44-pin TSOP Type II package.
WE Logic Block Diagram
12345678910111431323635343337403938Top View
TSOP II
12134144434216152930V CC A 14A 13A 12NC
NC A 3OE V SS A 5I/O 16A 2CE I/O 3I/O 1I/O 2BHE NC A 1A 018172019I/O 42728252622
2123
24NC
V SS I/O 7I/O 5I/O 6I/O 8A 6A 7BLE V CC I/O 15I/O 14I/O 13I/O 12I/O 11I/O 10I/O 9A 8A 9A 10A 1132K × 16RAM Array
I/O 1–I/O 8R O W D E C O D E R
A 7A 6A 5A 4A 3A 0
COLUMN DECODER
A 9
A 10
A 11
A 12
A 13
A 14
S E N S E A M P S
DATA IN DRIVERS
OE A 2A 1I/O 9–I/O 16
CE WE BLE
BHE A 8
A 4Note:
1.NC pins are not connected on the die
Pin Configuration [1]
Selection Guide
-10-12-15Unit Maximum Access Time101215ns Maximum Operating Current Com’l/Ind’l908580mA
Automotive--85mA Maximum CMOS Standby Current Com’l/Ind’l555mA
Automotive--10mA Pin Definitions
Pin Name TSOP - Pin Number I/O Type Description
A0–A145, 4, 3, 2, 18, 44, 43, 42, 27,
Input Address Inputs used to select one of the address locations.
26, 25, 24, 21, 20, 19
I/O1–I/O167-10, 13-16, 29-32, 35-38Input/Output Bidirectional Data I/O lines. Used as input or output lines
depending on operation.
NC1, 22, 23, 28No Connect No Connects. Not connected to the die.
WE17Input/Control Write Enable Input, active LOW. When selected LOW, a Write is
conducted. When deselected HIGH, a Read is conducted.
CE6Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE40, 39Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9,
BLE controls I/O8–I/O1.
OE41Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
V SS12, 34Ground Ground for the device.Should be connected to ground of the
system.
V CC11, 33Power Supply Power Supply inputs to the device.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C Ambient Temperature with
Power Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND[1]....–0.5V to +4.6V DC Voltage Applied to Outputs
in High-Z State[2]....................................–0.5V to V CC + 0.5V DC Input Voltage[2].................................–0.5V to V CC + 0.5V Current into Outputs (LOW).........................................20 mA Static Discharge Voltage...........................................> 2001V (per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA Operating Range
Range Ambient Temperature V CC Commercial0°C to +70°C 3.3V
± 10% Industrial–40°C to +85°C 3.3V ± 10% Automotive–40°C to +125°C 3.3V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
-10-12-15
Unit Min.Max.Min.Max.Min.Max.
V OH Output HIGH
Voltage
V CC = Min., I OH = –4.0 mA 2.4 2.4 2.4V
V OL Output LOW
Voltage
V CC = Min., I OL = 8.0 mA0.40.40.4V
V IH Input HIGH
Voltage
2.0V CC + 0.3 2.0V CC + 0.3 2.0V CC + 0.3V
V IL Input LOW
Voltage[2]
?0.30.8–0.30.8–0.30.8V
I IX Input Leakage
Current GND < V I < V CC Com’l/Ind’l?1+1–1+1–1+1μA Auto–20+20μA
I OZ Output Leakage
Current GND < V I < V CC,
Output Disabled
Com’l/Ind’l?1+1–1+1–1+1μA
Auto–20+20μA
I CC V CC Operating
Supply Current V CC = Max.,
I OUT = 0 mA,
f = f MAX = 1/t RC
Com’l/Ind’l908580mA
Auto85mA
I SB1Automatic CE
Power-down
Current
—TTL Inputs Max. V CC, CE > V IH
V IN > V IH or V IN < V IL,
f = f MAX
Com’l/Ind’l151515mA
Auto20mA
I SB2Automatic CE
Power-down
Current
—CMOS Inputs Max. V CC,
CE > V CC – 0.3V,
V IN > V CC – 0.3V,
or V IN < 0.3V, f = 0
Com’l/Ind’l555mA
Auto10mA
Capacitance[3]
Parameter Description Test Conditions Max.Unit
C IN Input Capacitance T A = 25°C, f = 1 MHz,
V CC = 3.3V 8pF
C OUT Output Capacitance8pF Thermal Resistance[3]
Parameter Description Test Conditions44-pin TSOP-II Unit
ΘJA Thermal Resistance
(Junction to Ambient)Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
76.92°C/W
ΘJC Thermal Resistance
(Junction to Case)
15.86°C/W
Notes:
2.V IL (min.) = –2.0V and V IH(max) = V CC + 0.5V for pulse durations of less than 20 ns.
3.Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms [4]
Switching Characteristics Over the Operating Range [4]
Parameter Description
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle t RC Read Cycle Time 10
12
15
ns t AA Address to Data Valid
10
12
15
ns t OHA Data Hold from Address Change 3
3
3
ns t ACE CE LOW to Data Valid 101215ns t DOE OE LOW to Data Valid 5
6
7
ns t LZOE OE LOW to Low-Z [5]0
ns t HZOE OE HIGH to High-Z [5, 6]5
6
7
ns t LZCE CE LOW to Low-Z [5]3
3
3
ns t HZCE CE HIGH to High-Z [5, 6]5
6
7
ns t PU [7]CE LOW to Power-up 0
ns t PD [7]CE HIGH to Power-down 101215ns t DBE Byte Enable to Data Valid 5
6
7
ns t LZBE Byte Enable to Low-Z 0
ns t HZBE
Byte Disable to High-Z
5
6
7
ns
Write Cycle [8]t WC Write Cycle Time 101215ns t SCE CE LOW to Write End 8910ns t AW Address Set-up to Write End 7810ns t HA Address Hold from Write End 000ns t SA Address Set-up to Write Start 000ns t PWE WE Pulse Width 7810ns t SD Data Set-up to Write End 568ns t HD Data Hold from Write End 000ns t LZWE WE HIGH to Low-Z [5]3
3
3
ns t HZWE WE LOW to High-Z [5, 6]5
6
7
ns t BW
Byte Enable to End of Write
789ns
Notes:
4.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5.At any given temperature and voltage condition, t HZCE is less than t LZCE , t HZOE is less than t LZOE , and t HZWE is less than t LZWE for any given device.
6.t HZOE , t HZBE , t HZCE , and t HZWE are specified with a load capacitance of 5 pF as in part (c) of AC T est Loads. Transition is measured ± 500 mV from steady-state voltage.
7.This parameter is guaranteed by design and is not tested.
8.The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
90%10%
3.0V
GND
90%10%
ALL INPUT PULSES
3.3V OUTPUT
30 pF
R 317?
R2351?
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
(a) 3.3V OUTPUT
5 pF
(c)
R 317?
R2351?
High-Z characteristics:
Switching Waveforms
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
9.Device is continuously selected. OE, CE, BHE and/or BHE = V IL .10.WE is HIGH for Read cycle.
11.Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID
DATA VALID
t RC
t AA
t OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t RC
t ACE
t DOE t LZOE t LZCE t PU
HIGH IMPEDANCE
t HZOE
t HZBE
t PD
HIGH
OE CE
ICC ISB IMPEDANCE
ADDRESS
DATA OUT V CC SUPPLY t DBE t LZBE
t HZCE BHE,BLE
CURRENT
I CC
I SB
Write Cycle No. 1 (CE Controlled)[12, 13]
Write Cycle No. 2 (BLE or BHE Controlled)
Notes:
12.Data I/O is high impedance if OE or BHE and/or BLE = V IH .
13.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
t HD
t SD
t SCE
t SA t HA
t AW
t PWE
t WC
BW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
t t HD
t SD
t BW
t SA t HA
t AW
t PWE
t WC
t SCE
DATA I/O
ADDRESS
BHE,BLE
WE
CE
Write Cycle No. 3 (WE Controlled, OE LOW)
Truth Table
CE OE WE BLE BHE I/O 1–I/O 8I/O 9–I/O 16Mode
Power
H X X X X High-Z High-Z Power-down Standby (I SB )L
L
H
L L Data Out Data Out Read—All bits Active (I CC )L H Data Out High-Z Read—Lower bits only Active (I CC )H
L High-Z Data Out Read—Upper bits only Active (I CC )L
X
L
L L Data In Data In Write—All bits Active (I CC )L H Data In High-Z Write—Lower bits only Active (I CC )H
L High-Z Data In Write—Upper bits only Active (I CC )L H H X X High-Z High-Z Selected, Outputs Disabled Active (I CC )L
X
X
H
H
High-Z
High-Z
Selected, Outputs Disabled
Active (I CC )
Ordering Information
Speed (ns)Ordering Code
Package Diagram Package Type
Operating Range 10CY7C1020CV33-10ZC 51-85087
44-pin TSOP Type II
Commercial
CY7C1020CV33-10ZXC 44-pin TSOP Type II (Pb-Free)12CY7C1020CV33-12ZC 44-pin TSOP Type II Commercial 15
CY7C1020CV33-15ZC 44-pin TSOP Type II Commercial CY7C1020CV33-15ZE 44-pin TSOP Type II
Automotive
CY7C1020CV33-15ZSXE
44-pin TSOP Type II (Pb-Free)
Switching Waveforms (continued)
t HD
t SD
t SCE
t HA
t AW
t PWE
t WC
t BW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
t SA
t LZWE
t HZWE
Package Diagrams
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Document #: 38-05133 Rev. *E Page 8 of 9
Document History Page
Document Title: CY7C1020CV33 512K (32K x 16) Static RAM Document Number: 38-05133
REV.ECN NO.Issue Date Orig. of
Change Description of Change
**10942812/16/01HGK New Data Sheet
*A11504505/30/02HGK I CC and I SB1 data modified
*B11761508/14/02DFP Pin 1= NC Pin 18 = A4; remove SOJ package option; remove 8ns option. *C262949See ECN RKF Added Automotive Specs to Data sheet
*D334398See ECN SYT Added Lead-Free Product Information
*E493543See ECN NXR Added note #1 on page #1
Changed the description of I IX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed I OS parameter from DC Electrical Characteristics table
Updated Ordering Information Table