固定占空比PWM波形输出程序

程序一：系统初试化程序

#include "DSP28_Device.h"

void InitSysCtrl(void)

{

Uint16 i;

EALLOW;

DevEmuRegs.M0RAMDFT = 0x0300;

DevEmuRegs.M1RAMDFT = 0x0300;

DevEmuRegs.L0RAMDFT = 0x0300;

DevEmuRegs.L1RAMDFT = 0x0300;

DevEmuRegs.H0RAMDFT = 0x0300;

SysCtrlRegs.WDCR= 0x0068;

SysCtrlRegs.PLLCR = 0xA; for(i= 0;

i< 5000; i++){}

SysCtrlRegs.HISPCP.all = 0x0001;

SysCtrlRegs.LOSPCP.all = 0x0002;

SysCtrlRegs.PCLKCR.bit.EV AENCLK=1;

SysCtrlRegs.PCLKCR.bit.EVBENCLK=1;

EDIS;

}

void KickDog(void)

{

EALLOW;

SysCtrlRegs.WDKEY = 0x0055;

SysCtrlRegs.WDKEY = 0x00AA;

EDIS;

}

程序二：Gpio 口初始化#include

"DSP28_Device.h" void InitGpio(void)

{

EALLOW

GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6=1; GpioMuxRegs.GPAMUX.bit.T2PWM_GPIOA7=1; GpioMuxRegs.GPAMUX.bit.PWM1_GPIOA0=1; GpioMuxRegs.GPAMUX.bit.PWM2_GPIOA1=1; GpioMuxRegs.GPAMUX.bit.PWM3_GPIOA2=1; GpioMuxRegs.GPAMUX.bit.PWM4_GPIOA3=1; GpioMuxRegs.GPAMUX.bit.PWM5_GPIOA4=1; GpioMuxRegs.GPBMUX.bit.T3PWM_GPIOB6=1; GpioMuxRegs.GPBMUX.bit.T4PWM_GPIOB7=1; GpioMuxRegs.GPBMUX.bit.PWM7_GPIOB0=1; GpioMuxRegs.GPBMUX.bit.PWM8_GPIOB1=1; GpioMuxRegs.GPBMUX.bit.PWM9_GPIOB2=1; GpioMuxRegs.GPBMUX.bit.PWM10_GPIOB3=1; GpioMuxRegs.GPBMUX.bit.PWM11_GPIOB4=1; GpioMuxRegs.GPBMUX.bit.PWM12_GPIOB5=1; EDIS;

}程序四：主程序

#include "DSP28_Device.h"

#include "DSP28_Globalprototypes.h"

void main(void)

{

InitSysCtrl();

DINT;

IER = 0x0000;

IFR = 0x0000;

InitPieCtrl();

InitPieVectTable();

InitGpio();

InitEv();

EvaRegs.T1CON.bit.TENABLE=1;

EvaRegs.T2CON.bit.TENABLE=1;

EvbRegs.T3CON.bit.TENABLE=1;

EvbRegs.T4CON.bit.TENABLE=1;

while(1){ }

}

程序说明

本程序实现的是在PWM1 , PWM3 , PWM 5三个口输出占空比为5 0%,频率为5KHZ的对称方波。本程序参照书上固定占空比PWM波形产生程序改写而成。

程序三：EV 初始化

#include "DSP28_Device.h"

void InitEv(void)

{

EvaRegs.T1CON.bit.TMODE=1; EvaRegs.T1CON.bit.TPS=1; EvaRegs.T1CON.bit.TENABLE=0; EvaRegs.T1CON.bit.TCLKS10=0; EvaRegs.T1CON.bit.TECMPR=1; EvaRegs.T2CON.bit.TMODE=1; EvaRegs.T2CON.bit.TPS=1; EvaRegs.T2CON.bit.TENABLE=0; EvaRegs.T2CON.bit.TCLKS10=0; EvaRegs.T2CON.bit.TECMPR=1; EvaRegs.GPTCONA.bit.TCOMPOE=1; EvaRegs.GPTCONA.bit.T1PIN=1; EvaRegs.GPTCONA.bit.T2PIN=2; EvaRegs.T1PR= 7499;

EvaRegs.T1CMPR=3750; EvaRegs.T1CNT=0;

EvaRegs.T2PR=7499;

EvaRegs.T2CMPR=3750; EvaRegs.T2CNT=0;

https://www.wendangku.net/doc/7910817960.html,CONA.bit.CENABLE=1; https://www.wendangku.net/doc/7910817960.html,CONA.bit.FCOMPOE=1; https://www.wendangku.net/doc/7910817960.html,CONA.bit.CLD=2; EvaRegs.DBTCONA.bit.DBT=10; EvaRegs.DBTCONA.bit.EDBT1=1; EvaRegs.DBTCONA.bit.EDBT2=1; EvaRegs.DBTCONA.bit.EDBT3=1; EvaRegs.DBTCONA.bit.DBTPS=4, EvaRegs.ACTR.all=0x0999; EvaRegs.CMPR1=7499; EvaRegs.CMPR2=7499; EvaRegs.CMPR3=7499; EvbRegs.T3CON.bit.TMODE=1; EvbRegs.T3CON.bit.TPS=1; EvbRegs.T3CON.bit.TENABLE=0; EvbRegs.T3CON.bit.TCLKS10=0; EvbRegs.T3CON.bit.TECMPR=1; EvbRegs.T4CON.bit.TMODE=1; EvbRegs.T4CON.bit.TPS=1; EvbRegs.T4CON.bit.TENABLE=0; EvbRegs.T4CON.bit.TCLKS10=0; EvbRegs.T4CON.bit.TECMPR=1; EvbRegs.GPTCONB.bit.TCOMPOE=1; EvbRegs.GPTCONB.bit.T3PIN=1; EvbRegs.GPTCONB.bit.T4PIN=2; EvbRegs.T3PR=0x493E; EvbRegs.T3CMPR=0x1D4C; EvbRegs.T3CNT=0;

EvbRegs.T4PR=0x493E; EvbRegs.T4CMPR=0x2BF2; EvbRegs.T4CNT=0;

https://www.wendangku.net/doc/7910817960.html,CONB.bit.CENABLE=1; https://www.wendangku.net/doc/7910817960.html,CONB.bit.FCOMPOE=1; https://www.wendangku.net/doc/7910817960.html,CONB.bit.CLD=2; EvbRegs.DBTCONB.bit.DBT=10; EvbRegs.DBTCONB.bit.EDBT1=1; EvbRegs.DBTCONB.bit.EDBT2=1; EvbRegs.DBTCONB.bit.EDBT3=1; EvbRegs.DBTCONB.bit.DBTPS=4, EvbRegs.ACTRB.all=0x0999; EvbRegs.CMPR4=0x1D4C; EvbRegs.CMPR5=0x1D4C; EvbRegs.CMPR6=0x1D4C;

}