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基于FSEZ13X7的开关电源设计

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Application Note AN-8033

Design Guideline for Primary Side Regulated (PSR) Flyback Converter Using FAN103 and FSEZ13X7

1. Introduction

More than half of the external power supplies are used for portable electronics such as laptops, cellular phones, and MP3 players and; therefore, have output voltage and output current regulation capabilities for battery charging. In applications where precise output current regulation is required, current sensing in the secondary side is always necessary, which results in additional sensing loss. For power supply designers struggling in an environment of increasing regulatory pressures, the output current sensing is a daunting design challenge.

Primary-side regulation (PSR) for power supplies can be an optimal solution for alleviating the burden of achieving international energy efficiency regulations (California Energy Commission (CEC) and Energy Star) in charger designs. The primary-side regulation controls the output voltage and current precisely with the information in the primary side of the power supply only, not only removing the output current sensing loss, but also eliminating all secondary-feedback circuitry. This facilitates a higher efficiency power supply design without incurring tremendous costs. Fairchild Semiconductor PWM PSR controller FAN103 and Fairchild Power Switch (FPS) (MOSFET + Controller, EZ-PSR) FSEZ13X7 significantly simplify the challenge of meeting tighter efficiency requirements while eliminating external components. FAN103 and FSEZ13x7 also have an integrated output cable voltage drop compensation and external component temperature variation compensation circuit, which allows high accuracy even at the end of the output cable for charger applications.

This application note presents practical design considerations for battery chargers employing Fairchild Semiconductor PWM PSR controller FAN103 and Power Switch (MOSFET + Controller, EZ-PSR) FSEZ13X7. It includes designing the transformer and output filter, selecting the components, and implementing constant- current / constant-voltage control. The step-by-step design procedure described helps engineers design a power supply more easily. The design procedure is verified through an experimental prototype converter using FSEZ1317. Figure 1 shows the typical application circuit of primary-side controlled flyback converter using FSEZ1317.

Figure 1. Typical Application Circuit of FSEZ1317

2. Operation Principle of Primary- Side Regulation

Figure 2 shows the simplified circuit diagram of a primary- side regulated flyback converter and its typical waveforms are shown in Figure 3. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation since it allows better output regulation. The key of primary-side regulation is how to obtain output voltage and current information without directly sensing them. Once these values are obtained, the control can be accomplished by the conventional feedback compensation method.

The operation principles of DCM flyback converter are as follows:

? During the MOSFET ON time (t ON ), input voltage

(V DL ) is applied across the primary-side inductor (L m ). Then, MOSFET current (I ds ) increases linearly from zero to the peak value (I pk ). During this time, the energy is drawn from the input and stored in the

inductor.

When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to be turned on. During the diode conduction time (t D ), the output voltage (V o ), together with diode forward-voltage drop (V F ), are applied across the secondary-side inductor (L m ×N s2/ N p2) and the diode current (I D ) decreases linearly from the peak value (I pk × N p /N s ) to zero. At the end of t D , all the energy stored in the inductor has

been delivered to the output.

When the diode current reaches zero, the transformer auxiliary winding voltage (V w ) begins to oscillate by the resonance between the primary-side inductor (L m ) and the MOSFET output capacitor.

During the diode conduction time, the sum of output voltage and diode forward-voltage drop is reflected to the auxiliary winding side as (V o +V F )× N a /N s . Since the diode forward-voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the diode conduction time (t D ) and switching period (t s ). These output information is compared with internal precise reference to generate error voltage (V COMI ), which determines the duty cycle of the MOSFET, as shown in the block diagram of Figure 2. Among the two error voltages, V COMV and V COMI , the smaller one actually determines the duty cycle. Therefore, during constant voltage regulation mode, V COMV determines the duty cycle while V COMI is saturated to HIGH. During constant current regulation mode, V COMI determines the duty cycle while V COMV is saturated to HIGH.

Figure 2. Primary-Side Regulated Flyback Converter

I pk

N p

I pk ?

at the end of diode conduction time where the diode N s

current diminishes to zero. By sampling the winding I

= I

voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to V ? N

D avg a

generate an error voltage (V COMV ), which determines the duty cycle of the MOSFET, as shown in Figure 2.

Meanwhile, the output current can be estimated through calculation. Assuming that output current is same as the average of the diode current in steady state, the output current can be estimated as:

N P t D

N s

N V O ?

N s

I O

= I

PK N ?

S (1)

2t S

Figure 3. Key Waveforms of Primary-Side Regulated

Flyback Converter

3. Design Consideration

Converters with Constant Current (CC) output require more design consideration than the conventional power supply design with a fixed output voltage. In CC operation, the voltage for control IC (V DD), which is usually obtained with an auxiliary winding of the transformer, changes with the output voltage. Thus, the V DD operation range determines the constant current control range. FAN103 and FSEZ13X7 have a wide supply voltage (V DD) operation range from 5V up to 24V, which allows stable CC regulation even with output voltage lower than a quarter of its nominal value.

Another important design consideration for CC operation is that the transformer should be designed to guarantee DCM operation in all operation range since the output information is properly obtained only in DCM operation, as described in Section 2. As seen in Figure 4, the MOSFET conduction time (t ON) decreases as output voltage decreases in CC mode. Meanwhile, the diode conduction time (t D) increases as the output voltage decreases. Since the increase of t ON is dominant to the decrease of t ON in determining the sum of t ON and t D, the converter tends to enter CCM as output voltage decreases. FAN103 and FSEZ13X7 have a frequency reduction function to prevent CCM operation by extending the The transformer should be designed for DCM both at 70% of nominal output voltage and minimum output voltage. Once the converter is designed to operate in DCM at 70% of nominal output voltage and minimum output voltage, DCM operation is guaranteed for entire load range.

V ds

I PK

I ds

t ON t D

V ds

I ds I PKCC

t ONCC t DCC

T CC =T / k

switching period, which is activated when the output CC

O = V / k

ON ON

T = T ?k

voltage drops below 70% of its nominal value, as depicted in Figure 5. Therefore, 70% of output voltage and minimum output voltage are the two worst cases for the transformer design.

D D

Figure 4. t ON and t D Change as Output Voltage

Decreases

Figure 5. Operation Range of Charger with CC/CV

N N 4. Design Procedure

In this section, a design procedure is presented using the schematic of Figure 6 as a reference. An offline charger with 3.75W/5V output has been selected as a design example. The design specifications are as follows:

? Line voltage range: 90~264V AC and 60Hz ? Nominal output voltage and current: 5V/0.75A ?

Output voltage ripple: less than 150mV

? Minimum output voltage in CC mode: 25% of

nominal output (1.25V)

Table 1. Typical Efficiency of Flyback Converter

Output Typical Efficiency Typical Efficiency Voltage

for Universal Input

for European Input

3.3~6V 65~70% 67~72% 6~12V 70~77% 72~79% 12~24V 77~82% 79~84%

Figure 7. Definition of Primary- and Secondary-

Side Efficiency

With the estimated overall efficiency, the input power at nominal output is given as:

V I

O O

Figure 6. Output Voltage and Current Operating Area

[STEP-1] Estimate the Efficiencies

A charger application has output voltage and current that

change over wide range as shown in Figure 6. To optimize the power stage design, the efficiencies and input powers should be specified for operating point A (nominal output P IN =

(4)

where V ON and I ON are the nominal output voltage and current, respectively.

Then, the input power of transformer at nominal output is given as:

V N N I

O O

voltage and current), B (70% of nominal output voltage), P

IN T

and C (minimum output voltage), respectively.

= (5)

ηS

As mentioned in previous section, when the output voltage … Estimated overall efficiency (η) for operating points A,

B, and C: The overall power conversion efficiency should be estimated to calculate the input power. If no reference data is available, use the typical efficiency in Table 1.

… Estimated primary-side efficiency (ηP ) and secondary-

side efficiency (ηS ) for operating points A, B, and C.

Figure 7 shows the definition of primary-side and secondary-side efficiencies, where the primary-side efficiency is for the power transfer from AC line input to the transformer primary side, while the secondary- drops below 70% of its nominal value, the frequency is reduced to 33kHz to prevent CCM operation. Thus, the transformer should be designed for DCM both at 70% of nominal output voltage and minimum output voltage.

As output voltage reduces in CC mode, the efficiency also drops. To optimize the transformer design, it is required to estimate the efficiencies properly at 70% of nominal output voltage and minimum output voltage conditions.

The overall efficiency at 70% of nominal output voltage (operating point B) can be approximated as:

0.7 ?V

V +V

side efficiency is for the power transfer from the η

η? O ?

transformer primary side to the power supply output.

The typical values for the primary-side and secondary- O

@ B

N 0.7 ?V

O +V F

where V F is diode forward-voltage drop.

(6)

side efficiencies are given as:

1 2 3 3 (2) The secondary-side efficiency at 70% of nominal output voltage (operating point B) can be approximated as:

η P ? η , ηS ? η : output voltage < 10V 2 1 η S @B ? ηS ?

N N

0.7 ?V O

V O + V F

(7)

Then, the power supply input power and transformer input power at 70% nominal output voltage (operating point B) are given as:

P IN @ B =

N N

0.7 ?V ?O O I

η@B

N N

0.7 ?V ?I

(8)

P IN T @ B =O O

ηS @ B

(9) The overall efficiency at the minimum output voltage (operating point C) can be approximated as:

η?η?

min N

V O V O + V F

?(10)

@C min N

V +V V

O F O

where Vo min is the minimum output voltage.

The secondary-side efficiency at minimum output voltage (operating point C) can be approximated as:

ηS @C ?ηS ?

min

V O

min

O + V

V O + V F

?(11)

F V O

Then, the power supply input power and transformer input power at the minimum output voltage (operating point C) are given as:

min N

V ?I [STEP-2] Determine the DC Link Capacitor (C DL) and the DC Link Voltage Range

It is typical to select the DC link capacitor as 2-3μF per

P IN @ C = P IN T @ C

O O

η@ C

min N

V O ?I O

ηS @ C

(12)

(13)

watt of input power for universal input range (90-265V RMS)

and 1μF per watt of input power for European input range

(195V~265V RMS). With the DC link capacitor chosen, the

minimum DC link voltage is obtained as:

min min 2 P IN (1 ?D ch )

V = 2 ?( V ) ?(14)

DL LINE C DL L ?f

where V LINEmin is the minimum line voltage, C DL is the DC link

capacitor, f L is the line frequency, and D ch is the DC link

capacitor charging duty ratio defined as shown in Figure 8,

which is typically about 0.2.

The maximum DC link voltage is given as:

V max max

= 2?V (15)

DL LINE

where V LINEmax is the maximum line voltage.

The minimum input DC link voltage at 70% nominal

output voltage are given as:

V DL @

min = 2 ?( V

P IN @ B (1 ?D ch )

min 2

LINE ) ?(16)

C ?f

DL L

The minimum input DC link voltage at minimum output

voltage are given as:

P (1?D )

min min 2 IN @

V = 2 ?( V ) C ch

?(17)

DL @ C LINE C ?f

DL L

AN-8033

nom D

N S V N P

max

DL + V O (20)

As observed in Equations (6) and (7), increasing the transformer turns ratio (N p /N s ) results in increased voltage of MOSFET, while it leads to reduced voltage stress of rectifier diode. Therefore, the transformer turns ratio (N p /N s ) should be determined by the compromise between Figure 8. DC Link Voltage Waveforms

MOSFET and diode voltage stresses. When determining the transformer turns ratio, the voltage overshoot on drain voltage should be also considered. The maximum voltage stress of MOSFET is given as:

max

= V

+V +V

(21)

For reasonable snubber design, voltage overshoot (V OS ) is typically 1~1.5 times of the reflected output voltage. It is also typical to have a margin of 15~20% of breakdown voltage for maximum MOSFET voltage stress.

[STEP-3] Determine the Transformer Turns Ratio

Figure 9 shows the MOSFET drain-to-source voltage waveforms. When the MOSFET is turned off, the sum of the input voltage (V DL ) and the output voltage reflected to the primary is imposed across the MOSFET as:

nom

max

N P ( V O + V F ) N S

= V +V

(18)

where V RO is reflected output voltage defined as:

N p Figure 9. Transformer Turns Ratio and Voltage Stress

on MOSFET and Diode

The transformer turns ratio between the auxiliary winding

V =

( V +V )

(19)

and secondary winding (N a /N s ) should be determined by s

where V F is the diode forward voltage drop and N P and N S are number of turns for primary side and secondary side, respectively.

When the MOSFET is turned on, the output voltage, together with input voltage reflected to the secondary, are imposed across the diode as: considering the permissible IC supply voltage (V DD ) range and minimum output voltage in CC mode. When the power supply operates in constant current (CC) mode, V DD changes, together with the output voltage, as seen in Figure 10. The overshoot of auxiliary winding voltage caused by the leakage inductance also affects the V DD . V DD voltage at light-load condition, where the overshoot of auxiliary winding voltage is negligible, is given as:

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AN-8033

min1

DD = N a

N S

( V o + V F )? V F a

(22)

The actual V DD voltage at heavy load is higher than Equation (8) due to the overshoot by the leakage inductance, which is proportional to the voltage overshoot of MOSFET drain-to-source voltage shown in Figure 10. Considering the effect of voltage overshoot, the V DD voltages for nominal output voltage and minimum output voltage are given as:

N N

max

V ?

( V + V +

V ) ? V

N O

S OS

(23) V

min 2

N a min

N S

( V

+ V +

V ) ? V (24)

N O

OS Fa

where V Fa is the diode forward-voltage drop of auxiliary winding diode.

[STEP-4] Design the Transformer

Figure 11 shows the definition of MOSFET conduction time (t ON ), diode conduction time (t D ) and non-conduction time (t OFF ). The sum of MOSFET conduction time and diode conduction time at 70% of nominal output voltage is obtained as:

T ON + T D = T ON (1 +

N S N P

V DL @ B min

? 0.7 ? V O + V )

(25)

The first step to design the transformer is to determine how much non-conduction time (t OFF ) is allowed in DCM operation.

Once the t OFF is determined by considering the frequency variation caused by frequency hopping and its own tolerance, the MOSFET conduction time is obtained as:

1/ f ? T Figure 10. V DD and Winding Voltage

T ON @B =

(1 + N

S S

OFF

min

V DL @ B

? N )

(26)

N P 0.7 ?V O +V F

Figure 11. Definition of t ON , t D , and t OFF

The transformer primary-side inductance can be calculated as:

( V min

? T

)

L =

DL @ B

ON @B

? f

(27)

2P IN T @B

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The maximum peak drain current can be obtained at the nominal output condition as:

Then, the non-conduction time at minimum output voltage is given as:

min

2P 1

IN T

(28)

= ? T

DL @ C

? ) (33)

L ? f

OFF @ C

ON @C

min

N V + V

m S

The MOSFET conduction time at the nominal output condition is obtained as:

L m SR

The non-conduction time should be larger than 3μs (10% of

switching period), considering the tolerance of switching frequency.

T ON = I DS V min (29)

Table 2. Typical Cores for Battery Charger Application The minimum number of turns for the transformer primary side to avoid the core saturation is given by:

(for Universal Input Range, DCM Operation, and

fs=50kHz)

Core Cross-sectional Area Rated Input Power

min

= L I m DS

B A

(30)

EE13-Z 17.1mm 2 4~7W sat e

where A e is the cross-sectional area of the core in m 2 and EI16-Z 19.8mm 2

4~7W B sat is the saturation flux density in Tesla. Figure 12 shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (B sat ) decreases as the temperature rises, the high-temperature characteristics should be considered when it comes to charger in enclosed case. If there is no reference data, use B sat =0.25~0.3 T. Table 2 shows the commonly used cores for battery chargers with output power under 10W. The cores recommended in Table 2 are typical for the universal input range and 50kHz switching frequency.

Once the turns ratio is obtained, determine the proper integer for N s so that the resulting N p is larger than N pmin obtained from Equation (30).

Figure 12. Typical B-H Curves of Ferrite Core

(TDK/PC40)

DCM operation at minimum output voltage should be also checked. The MOSFET conduction time at minimum output voltage is given as:

2 P

EE16-Z 19.0mm 2 7~14W EI19-Z

24.0mm 2

7~14W

ON @C

1 =

V DL @

min

IN T @ C m

(31)

f SR

where f SR is the reduced switching frequency to prevent CCM operation.

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[STEP-6] Output Voltage and Current Setting

The nominal output current is determined by the sensing resistor value and transformer turns ratio as:

N P

SENSE

N I S O N × 8.5

(37)

The voltage divider R S1 and R S2 should be determined so

that V S is 2.5V at the end of diode current conduction time, as shown in Figure 9.

R S

R S 2

= ( N a O V ? 1) N S 2.5

(38)

[STEP-5] Calculate the Voltage and Current of the Switching Devices

Primary-Side MOSFET : The voltage stress of the MOSFET was discussed when determining the transformer turns ratio in STEP-3. Assuming that drain voltage overshoot is the same as the reflected output voltage, the maximum drain voltage is given as:

max

Select 1% tolerance resistor for better output regulation.

= V

+V + V

(33)

The rms current though the MOSFET is given as:

rms DS PK

T = I

ON s f (34)

It is recommended to place a bypass capacitor of 22~68pF

Secondary-Side diode : The maximum reverse voltage and

the rms current of the rectifier diode are obtained respectively, as:

N S max

closely between the V S pin and the GND pin to bypass the switching noise and keep the accuracy of the sampled voltage for CV regulation. The value of the capacitor affects the load regulation and constant current regulation. V = V +

(35) Figure 13 illustrates the measured waveform on the V S pin I D

rms O = I N P rms V DL

min

DL ? N P

(36)

with a different V S capacitor. If a higher value V S capacitor is used, the charging time becomes longer and the sampled voltage is higher than the actual value.

D DS

V N

higher Vs Cap Vs pin waveform

lower Vs Cap sampling voltage

sampling voltage

No -Load

Figure 13. Effect on Sampling Voltage with

Different V S Capacitor

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[STEP-7] Determine the Output Filter Stage The peak to peak ripple of capacitor current is given as:

ΔI = N P PK

CAP N S DS (39) The voltage ripple on the output is given by:

ΔI ?T ΔI ?I N

ΔV O = C D C O 2

?( ) + ΔI

2 C ΔI ?C C R (40)

O C

Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. Then, additional LC filter stages (post filter) can be used. When using the post filters, be

careful not to place the corner frequency too low. Too low a corner frequency may make the system unstable or limit the control bandwidth. It is typical to set the corner frequency of the post filter at around 1/10~1/5 of the switching frequency.

[STEP-8] Cable Voltage Drop Compensation When it comes to cellular phone charger application, the actual battery is located at the end of cable, which causes typically several percentage of voltage drop on the actual battery voltage. FAN103 and FSEZ13X7 have cable voltage drop compensation that can be programmed by a resistor on the COMR pin, as shown in Table 3. The [STEP-9] Design RCD Snubber in Primary Side

When the power MOSFET is turned off, there is a high- voltage spike on the drain due to the transformer leakage inductance. This excessive voltage on the MOSFET may lead to an avalanche breakdown and eventually failure of the device. Therefore, it is necessary to use an additional network to clamp the voltage. The RCD snubber circuit and MOSFET drain voltage waveform are shown in Figure 14. The RCD snubber network absorbs the current in the leakage inductance by turning on the snubber diode (D sn) once the MOSFET drain voltage exceeds the voltage of node X as depicted in Figure 14. In the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching cycle. The snubber capacitor should be ceramic or a material that offers low ESR. Electrolytic or tantalum capacitors are unacceptable due to these reasons.

N p: N s I D I o

- C sn1 +

resistances of the standard 1.8m cable for different AWG are summarized in Table 4.

Table 3. Cable Compensation

Percentage of Voltage Drop

V DL

- V D + L V SN L m O

R sn1 V O A + D

D sn L lk

Compensation

5% COMR Resistor

I ds Infinite (Open) +

V ds 900k?V gs

- 380k?

4% 230k?I

dspk 3% 380k?

2% 145k?I ds

1% 100k?

0% 45k?

Table 4. Resistance of 1.8M Cable for Different AWG

Resistance for 1.8m

15~20% of BVdss V OS V sn

N P ( V O +V F)

N S

AWG ?/m 24 0.084 Cable

BVdss

0.30?V DL

25 0.106 0.38?V ds

26 0.134 0.48?Figure 14. Snubber Circuit and its Waveforms

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The snubber capacitor voltage at full load condition (V SN) is given as:

V = V + V (41) SN RO OS

The power dissipated in the snubber network is obtained as: V 2 1 V

P SN =SN

= f

R 2

PK 2 SN

S LK DS L ( I ) (42)

V ?V

SN SN RO

where I DSPK is peak drain current at full load, L LK is the leakage inductance, V SN is the snubber capacitor voltage at

full load and R SN is the snubber resistor.

The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted. Then, the snubber resistor with proper rated wattage should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as:

ΔV sn =

V SN

C R f

SN SN s

(43)

In general, 5~20% ripple of the selected capacitor voltage is reasonable.

In the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered. In the actual converter, the loss in the snubber network is less than the designed value due to this effect.

5. Print Circuit Board Layout

Print circuit board layout and design are very important for switching power supply where the voltage and current change with high dv/dt and di/dt. Good PCB layout minimizes excessive EMI and prevents the power supply from being disrupted during surge/ESD tests Guidelines:

? The numbers in the following guidelines refer to Figure 15 and Figure 16.

? To improve EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors C DL2 and C DL1 first, then to the primary switching circuits.

? The primary high-frequency current loop is in C

DL1 -

Transformer - MOSFET - R CS - C DL1. The area enclosed by this current loop should be kept as short as possible.

? Place R

START

for protect the inrush spike (100k? is recommended).

? R

should be connected C DL1’s ground directly. Keep it short and wide (Trace 4→1) and place it close the CS pin for reducing switching noise. High-voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heat sink is used for the MOSFET, connect this heat sink to ground. ? A s indicated by 2, the area enclosed by the transformer aux winding, D DD and C DD, should also be kept short path.

? P lace C

, C S, R S2, and C COMR close to each pin of PSR controller for good decoupling and to reduce the switching noise.

? A s indicated by 3, the ground of the control circuits should be connected first, then to other circuitry.

? G ND 3→2→4→1: May make it possible to avoid common impedance interference for the sense signal.

? R egarding the ESD discharge path, put in the shortcut pad between AC line and DC output (which is the best way). The other method is to discharge the ESD energy to AC line through the

primary main ground 1. Because ESD energy is delivered from secondary to primary though the transformer stray capacitor, the controller circuit

should not be placed on the discharge path. 5

shows places where the point-discharge route can be placed to bypass the static electricity energy. it is suggested to map out this discharge route in

Figure 15 and Figure 16.

? F or the surge path, select fusible resistor type with wire wound type to reduce inrush current and surge energy, use π input filter ( two bulk capacitor and one inductance) to share the surge energy.

Figure 15. EZ-PSR FSEZ13X7 Layout Consideration

Figure 16. PSR PWM FAN103 Layout Consideration

6. Final Schematic of Design Example

Figure 17 shows the final schematic of the 3.75W charger design example. EE16core is used for the transformer. Figure 18 shows the transformer information.

Figure 17. Final Schematic of the EZ-PSR FSEZ1317 3.75W Design Example

Core: EE16 PC40

Bobbin: EE16 (10 pins) Horizontal type

Figure 18. Transformer Structure

Notes:

1. When W4R’s winding is reversed winding, it must wind one layer.

2. When W2 is winding, it must wind three layers and put one layer of tape after winding the first layer.

TERMINAL INSULATION BARRIER TAPE NO WIRE t s

S F t s Primary Seconds W1 4 5 2UEW 0.23*1 15 2

41 1

W2 3 1 2UEW 0.18*1 39 0

37 2

W3 1 COPPER SHIELD 1.2 3

W4 7 9 TEX-E 0.55*1 9 3

CORE ROUNDING TAPE 3

Pin Specification Remark Primary-Side Inductance 1－3 2.25mH ± 5% 100kHz, 1V

7. Test Result of Design Example

To show the validity of the design procedure presented in this application note, the converter of the design example has been built and tested. All the circuit components are used as designed in the design example.

Figure 19 shows the operation waveforms at 70% of nominal output voltage and minimum line voltage condition. As designed in STEP-4, the non-conduction time is 4μs before frequency reduction occurs, which guarantees DCM operation. Figure 20 shows the operation waveforms at minimum output voltage and minimum line voltage condition. As designed in STEP-4, the non-conduction time is about 6.8μs, which guarantees DCM operation.

Figure 21 shows the measured efficiency for different load

conditions. The average efficiencies at 115V AC and 230V AC condition are higher than 68%. Figure 22 shows the measured no-load power consumption at different line voltage. As can be seen in the figures, even in the 264V AC AC line, the no-load standby power consumption is still less than 30mW, meeting the five-star level of new power consumption regulation for charger.

Figure 23 shows the measured output voltage and output current curve. CV regulation achieves 1.38% for entire line and load condition. The CC regulation can achieve 3.6% with a fold-back voltage of 1.5V.

Figure 19. Operation Waveforms at 70% of Nominal Output Voltage and Minimum Line Voltage Condition Figure 20. Operation Waveforms at Minimum Output Voltage and Minimum Line Voltage Condition

Figure 21. Measured Efficiency

Figure 22. Measured No-Load Power Consumption Figure 23. Measured Output Voltage and Output

Current Curve