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ADS7804U;ADS7804P;ADS7804PB;ADS7804U1K;ADS7804U1KG4;中文规格书,Datasheet资料

FEATURES

q 100kHz min SAMPLING RATE q STANDARD ±10V INPUT RANGE q 72dB min SINAD WITH 45kHz INPUT q ±0.45 LSB max INL

q DNL: 12 Bits “No Missing Codes”q SINGLE +5V SUPPLY OPERATION

q PIN-COMPATIBLE WITH 16-BIT ADS7805q USES INTERNAL OR EXTERNAL REFERENCE

q COMPLETE WITH S/H, REF, CLOCK, ETC.q FULL PARALLEL DATA OUTPUT q 100mW max POWER DISSIPATION

q

28-PIN 0.3" PLASTIC DIP AND SO PACKAGES

ADS7804

DESCRIPTION

The ADS7804 is a complete 12-bit sampling analog-to-digital (A/D) converter using state-of-the-art CMOS structures. It contains a complete 12-bit, capacitor-based, SAR A/D con-verter with S/H, reference, clock, interface for microproces-sor use, and three-state output drivers.

The ADS7804 is specified at a 100kHz sampling rate, and guaranteed over the full temperature range. Laser-trimmed scaling resistors provide an industry-standard ±10V input range, while the innovative design allows operation from a single +5V supply, with power dissipation under 100mW.

The 28-pin ADS7804 is available in plastic 0.3" DIP and SO packages, both fully specified for operation over the indus-trial –40°C to +85°C range.

12-Bit 10μs Sampling CMOS ANALOG-to-DIGITAL CONVERTER

±10V Input

REF

CAP

A D S

780

4

A D S

780

4

SBAS019A – JANUARY 1992 – REVISED MAY 2003

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PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright ? 1992-2003, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ADS7804

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SBAS019A

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ABSOLUTE MAXIMUM RATINGS

Analog Inputs: V IN (25)

CAP ...................................+V ANA +0.3V to AGND2 –0.3V REF ..........................................Indefinite Short to AGND2

Momentary Short to V ANA

Ground Voltage Differences: DGND, AGND1, AGND2.................±0.3V V ANA .......................................................................................................7V V DIG to V ANA .....................................................................................

+0.3V V DIG .......................................................................................................7V Digital Inputs...........................................................–0.3V to +V DIG +0.3V Maximum Junction Temperature...................................................+165°C Internal Power Dissipation.............................................................825mW Lead Temperature (soldering, 10s)...............................................+300°C

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper han-dling and installation procedures can cause damage.ESD damage can range from subtle performance degrada-tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

MAXIMUM MINIMUM LINEARITY SIGNAL-TO-SPECIFIED ERROR (NOISE+DISTORTION)

PACKAGE-LEAD TEMPERATURE

PACKAGE ORDERING TRANSPORT PRODUCT (LSB)

RATIO (LSB)

(DESIGNATOR)(1)

RANGE MARKING NUMBER MEDIA, QUANTITY

ADS7804P ±0.970DIP-28 (NT)–40°C to +85°C ADS7804P ADS7804P Tube, 13ADS7804PB ±0.4572DIP-28 (NT)–40°C to +85°C ADS7804PB ADS7804PB Tube, 13ADS7804U

±0.9

70

SO-28 (DW)

–40°C to +85°C

ADS7804U

ADS7804U Tube, 28

"

"

"

"

"

"

ADS7804U/1K Tape and Reel, 1000ADS7804UB

±0.45

72

SO-28 (DW)

–40°C to +85°C

ADS7804UB

ADS7804UB Tube, 28

""""""

ADS7804UB/1K

Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at https://www.wendangku.net/doc/7511707780.html,.

ELECTRICAL CHARACTERISTICS

At T A = –40°C to +85°C, f S = 100kHz, and V DIG = V ANA = +5V, using internal reference, unless otherwise specified.

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ADS7804

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SBAS019A

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ELECTRICAL CHARACTERISTICS (Cont.)

At T

= –40°C to +85°C, f = 100kHz, and V = V = +5V, using internal reference, unless otherwise specified.

NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7804, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures. (3) As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage.

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ADS7804

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SBAS019A

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1V IN Analog Input. See Figure 7.

2AGND1Analog Ground. Used internally as ground reference point.3REF Reference Input/Output. 2.2μF tantalum capacitor to ground.4CAP Reference Buffer Capacitor. 2.2μF tantalum capacitor to ground.5AGND2Analog Ground.

6D11 (MSB)

O Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.7D10O Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.8D9O Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.9D8O Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.10D7O Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.11D6O Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.12D5O Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.13D4O Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.14DGND Digital Ground.

15D3O Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.16D2O Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.17D1O Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.

18D0 (LSB)O Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.19DZ O LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.20DZ O LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.21DZ O LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.22DZ O LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.23BYTE I Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).

24R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C enables the parallel output.

25CS I Internally OR ’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.

26BUSY O

At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs have been updated.

27V ANA Analog Supply Input. Nominally +5V. Decouple to ground with 0.1μF ceramic and 10μF tantalum capacitors.28

V DIG

Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ V ANA .

DIGITAL PIN #NAME I/O

DESCRIPTION

TABLE I. Pin Assignments.

PIN CONFIGURATION

V DIG V ANA BUSY CS R/C BYTE DZ DZ DZ DZ D0 (LSB)D1D2D3

V IN

AGND1

REF CAP AGND2D11 (MSB)

D10D9D8

D7D6D5D4DGND 123456789

1011121314

2827262524232221201918171615

ADS7804

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ADS7804

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SBAS019A

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BASIC OPERATION

Figure 1 shows a basic circuit to operate the ADS7804 with a full parallel data output. Taking R/C (pin 24) LOW for a minimum of 40ns (6μs max) will initiate a conversion. BUSY (pin 26) will go LOW and stay LOW until the conversion is completed and the output registers are updated. Data will be output in Binary Two ’s Complement with the MSB on pin 6.BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW.

The ADS7804 will begin tracking the input signal at the end of the conversion. Allowing 10μs between convert com-mands assures accurate acquisition of a new signal.The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compen-sate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section).

STARTING A CONVERSION

The combination of CS (pin 25) and R/C (pin 24) LOW for a minimum of 40ns immediately puts the sample/hold of the ADS7804 in the hold state and starts conversion ‘n ’. BUSY (pin 26) will go LOW and stay LOW until conversion ‘n ’ is completed and the internal output register has been updated.All new convert commands during BUSY LOW will be ig-nored. CS and/or R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal.

The ADS7804 will begin tracking the input signal at the end of the conversion. Allowing 10μs between convert com-mands assures accurate acquisition of a new signal. Refer to Table II for a summary of CS, R/C, and BUSY states and Figures 3 through 5 for timing diagrams.

CS and R/C are internally OR ’d and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion ‘n ’, be sure the less critical input is LOW at least 10ns prior to the initiating input.

To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. This will have no effect when using the internal data clock in the serial output mode. However, the parallel output will become active whenever R/C goes HIGH. Refer to the Reading Data sec-tion.

FIGURE 1. Basic Operation.

CS R/C BUSY OPERATION

1X X None. Databus is in Hi-Z state.

↓01Initiates conversion ‘n ’. Databus remains in Hi-Z state.

0↓1Initiates conversion ‘n ’. Databus enters Hi-Z state.

01↑Conversion ‘n ’ completed. Valid data from conversion ‘n ’ on the databus.↓11Enables databus with valid data from conversion ‘n ’.

↓10Enables databus with valid data from

conversion ‘n-1’(1). Conversion n in process.0↑0Enables databus with valid data from

conversion ‘n-1’(1). Conversion ‘n ’ in process.0

New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH.X X 0

New convert commands ignored. Conversion

‘n ’ in process.

NOTE: (1) See Figures 2 and 3 for constraints on data valid from conversion “n-1”.

Table II. Control Line Functions for Read and Convert.https://www.wendangku.net/doc/7511707780.html,/

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READING DATA

The ADS7804 outputs full or byte-reading parallel data in Binary Two ’s Complement data output format. The parallel output will be active when R/C (pin 24) is HIGH and CS (pin 25) is LOW. Any other combination of CS and R/C will tri-state the parallel output. Valid conversion data can be read in a full parallel, 12-bit word or two 8-bit bytes on pins 6-13and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table III for ideal output codes and Figure 2 for bit locations relative to the state of BYTE.

FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).

PARALLEL OUTPUT (During a Conversion)

After conversion ‘n ’ has been initiated, valid data from con-version ‘n-1’ can be read and will be valid up to 16μs after the start of conversion ‘n ’. Do not attempt to read data from 16μs after the start of conversion ‘n ’ until BUSY (pin 26) goes HIGH; this may result in reading invalid data. Refer to Table IV and Figures 3 and 5 for timing specifications.

Note! For the best possible performance, data should not be read during a conversion. The switching noise of the asyn-chronous data transfer can cause digital feedthrough de-grading the converter ’s performance.

The number of control lines can be reduced by tieing CS LOW while using R/C to initiate conversions and activate the output mode of the converter. See Figure 3.

DIGITAL OUTPUT

BINARY TWO ’S COMPLEMENT

DESCRIPTION ANALOG INPUT

BINARY CODE

HEX CODE

Full Scale Range ±10V Least Significant 4.88mV Bit (LSB)+Full Scale 9.99512V

0111 1111 11117FF (10V – 1LSB)Midscale 0V 0000 0000 0000000One LSB below –4.88mV 1111 1111 1111FFF Midscale –Full Scale

10V

1000 0000 0000

800

Table III. Ideal Input Voltages and Output Codes.

PARALLEL OUTPUT (After a Conversion)

After conversion ‘n ’ is completed and the output registers have been updated, BUSY (pin 26) will go HIGH. Valid data from conversion ‘n ’ will be available on D11-D0 (pin 6-13 and 15-18 when BYTE is LOW). BUSY going HIGH can be used to latch the data. Refer to Table IV and Figures 3 and 5 for timing specifications.

SYMBOL

DESCRIPTION MIN TYP MAX UNITS t 1Convert Pulse Width 40

6000ns t 2Data Valid Delay after R/C LOW 8μs t 3BUSY Delay from R/C LOW

65ns t 4BUSY LOW

8

μs t 5BUSY Delay after 220ns End of Conversion t 6Aperture Delay 40ns t 7Conversion Time 7.6

8μs t 8Acquisition Time 2

μs t 9Bus Relinquish Time 103583

ns t 10BUSY Delay after Data Valid

50

200ns t 11Previous Data Valid 7.4μs after R/C LOW t 7 + t 6Throughput Time 9

10μs t 12R/C to CS Setup Time 10ns t 13Time Between Conversions

10μs t 14

Bus Access Time 10

83ns

and BYTE Delay

TABLE IV. Conversion Timing.

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ADS7804

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SBAS019A https://www.wendangku.net/doc/7511707780.html,

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INPUT RANGES

The ADS7804 offers a standard ±10V input range. Figure 6shows the necessary circuit connections for the ADS7804with and without hardware trim. Offset and full scale error (1)specifications are tested and guaranteed with the fixed resistors shown in Figure 6b. Adjustments for offset and gain are described in the Calibration section of this data sheet.

The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compen-sate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section).

The nominal input impedance of 23kW results from the combination of the internal resistor network shown on the front page of the product data sheet and the external resis-tors. The input resistor divider network provides inherent overvoltage protection guaranteed to at least ±25V. The 1%resistors used for the external circuitry do not compromise the accuracy or drift of the converter. They have little influ-ence relative to the internal resistors, and tighter tolerances are not required.

NOTE: (1) Full scale error includes offset and gain errors measured at both +FS and –FS.

CALIBRATION

The ADS7804 can be trimmed in hardware or software. The offset should be trimmed before the gain since the offset directly affects the gain. To achieve optimum performance,several iterations may be required.

HARDWARE CALIBRATION

To calibrate the offset and gain of the ADS7804, install the proper resistors and potentiometers as shown in Figure 6a. The calibra-tion range is ±15mV for the offset and ±60mV for the gain.

SOFTWARE CALIBRATION

To calibrate the offset and gain of the ADS7804 in software,no external resistors are required. See the No Calibration section for details on the effects of the external resistors.Refer to Table V for range of offset and gain errors with and without external resistors.

NO CALIBRATION

See Figure 6b for circuit connections. The external resistors shown in Figure 6b may not be necessary in some applications.These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply.The nominal transfer function of the ADS7804 will be bound by the shaded region seen in Figure 7 with a typical offset of –30mV and a typical gain error of –1.5%. Refer to Table V for range of offset and gain errors with and without external resistors.

WITH WITHOUT EXTERNAL EXTERNAL RESISTORS

RESISTORS UNITS BPZ –10 < BPZ < 10–45 < BPZ < 5mV –2 < BPZ < 2–8 < BPZ < 1LSBs Gain –0.5 < error < 0.5–0.6 < error < –0.55% of FSR

Error

–0.25 < error < 0.25(1)

–0.45 < error < –0.3(1)

NOTE: (1) High Grade.

TABLE VII. Bipolar Offset and Gain Errors With and Without External Resistors.

FIGURE 6. Circuit Diagram With and Without External Resistors.

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FIGURE 7. Full Scale Transfer Function.

REFERENCE

The ADS7804 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4).

The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full scale error (FSE = ±0.5% for low grade, ±0.25% for high grade).

REF

REF (pin 3) is an input for an external reference or the output for the internal 2.5V reference. A 2.2μF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrad-ing the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads.

The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full scale range and the LSB size of the converter which can improve the SNR.

CAP

CAP (pin 4) is the output of the internal reference buffer. A 2.2μF capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the internal buffer. Using a capacitor any smaller than 1μF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2μF will have little affect on improving performance.The output of the buffer is capable of driving up to 2mA of current to a DC load. DC loads requiring more than 2mA of current from the CAP pin will begin to degrade the linearity of the ADS7804. Using an external buffer will allow the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This will cause performance degra-dation of the converter.

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LAYOUT

POWER

For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ADS7804 uses 90% of its power for the analog circuitry. The ADS7804 should be considered as an analog component.The +5V power for the A/D should be separate from the +5V used for the system ’s digital logic. Connecting V DIG (pin 28)directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best perfor-mance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both V DIG and V ANA should be tied to the same +5V source.

GROUNDING

Three ground pins are present on the ADS7804. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more suscep-tible to current induced voltage drops and must have the path of least resistance back to the power supply.

All the ground pins of the A/D should be tied to the analog ground plane, separated from the system ’s digital logic ground,to achieve optimum performance. Both analog and digital ground planes should be tied to the “system ” ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground.

SIGNAL CONDITIONING

The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injec-tion which can cause the driving op amp to oscillate. The FET switch on the ADS7804, compared to the FET switches on other CMOS A/D converters, releases 5%-10% of the charge.There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias filter on the front end. Any op amp sufficient for the signal in an application will be sufficient to drive the ADS7804.

The resistive front end of the ADS7804 also provides a guaranteed ±25V overvoltage protection. In most cases, this eliminates the need for external input protection circuitry.

INTERMEDIATE LATCHES

The ADS7804 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversion, the tri-state outputs can be used to isolate the A/D from other peripherals on the same bus. Tri-state outputs can also be used when the A/D is the only peripheral on the data bus.

Intermediate latches are beneficial on any monolithic A/D converter. The ADS7804 has an internal LSB size of 610μV.Transients from fast switching signals on the parallel port,even when the A/D is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. The effects of this phenomenon will be more obvious when using the pin-compatible ADS7805 or any of the other 16-bit converters in the ADS Family. This is due to the smaller internal LSB size of 38μV.

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分销商库存信息:

TI

ADS7804U ADS7804P ADS7804PB ADS7804U/1K ADS7804U/1KG4ADS7804PG4 ADS7804UE4ADS7804UG4ADS7804UBE4 ADS7804PBG4ADS7804UB ADS7804UB/1K

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