WV3EG264M72ESFR335D4-MG中文资料
WV3EG264M72ESFR-D4
ADVANCED*
White Electronic Designs
1GB – 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
DESCRIPTION
The WV3EG264M72ESFR is a 2x64Mx72 Double Data Rate DDR SDRAM high density module. This memory module consists of eighteen 64Mx8 bit with 4 banks DDR Synchronous DRAMs in FBGA packages, mounted on a 200-pin SO-DIMM FR4 substrate.
* T his product is under development, is not quali? ed or characterized and is subject to
change or cancellation without notice.NOTE: C onsult factory for availability of:
? RoHS compliant products ? Vendor source control options ? Industrial temperature option
FEATURES
200-pin SO-DIMM, dual in-line memory module Fast data transfer rates: PC2100 and PC2700 Utilizes 266 and 333 Mb/s DDR SDRAM
components V CC = V CCQ = 2.5V ±0.2V
Bidirectional data strobe (DQS) option Differential clock inputs (CK and CK#) DLL to align DQ and DQS transitions with CK Programmable burst: length (2, 4, 8)
Programmable READ# latency (CL): 2 and 2.5
(clock) Serial Presence Detect (SPD) with EEPROM Auto and self refresh: 64ms/ 8,192 cycle refresh Gold edge contacts Dual Rank Package option
? 200 Pin SO-DIM M
? PCB – 31.75mm (1.25") Max
OPERATING FREQUENCIES
DDR333@CL = 2.5
DDR266@CL = 2
DDR266@CL = 2.5
Clock Speed 166MHz 133MHz 133MHz CL-t RCD -t RP
2.5-3-3
2-2-2
2.5-3-3
WV3EG264M72ESFR-D4
ADVANCED
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PIN NAMES
Pin Name Function
A0-A12Address Inputs
BA0, BA1SDRAM Bank Address DQ0-DQ63Data Input/Output CB0-CB7Check Bits DQS0-DQS8Data strobes
CK0,CK0#Clock inputs, positive/negative CKE0, CKE1Clock enable input CS0#, CS1#Chip select input RAS#Row Address Strobe CAS#Column Address Strobe WE#Write Enable V CC Core Power V CCQ I/O Power V SS
Ground
SA0-SA2EEPROM address
SDA Serial Data Input/Output V REF
Input/Output Reference DM0-DM8Data-in mask
V CCSPD Serial EEPROM power supply
SCL Serial Presence Detect(SPD) Clock Input RESET#Reset enable
NC Spare pins, No connect
PIN CONFIGURATION
Pi n No.
Symbol
Pi n No.
Symbol
Pi n No.
Symbol
Pi n No.
Symbol
1V REF 51V SS 101A9151
DQ422V REF 52V SS 102A8152DQ463V SS 53DQ19103V SS 153DQ434V SS 54DQ23104V SS 154DQ475DQ055DQ24105A7155V CC 6DQ456DQ28106A6156V CC 7DQ157V CC 107A5157V CC 8DQ558V CC 108A4158NC 9V CC 59DQ25109A3159V SS 10V CC 60DQ29110A2160NC 11DQS061DQS3111A1161V SS 12DM062DM3112A0162V SS 13DQ263V SS 113V CC 163DQ4814DQ664V SS 114V CC 164DQ5215V SS 65DQ26115A10/AP 165DQ4916V SS 66DQ30116BA1166DQ5317DQ367DQ27117BA0167V CC 18DQ768DQ31118RAS#168V CC 19DQ869V CC 119WE#169DQS620DQ1270V CC 120CAS#170DM621V CC 71CB0121CS0#171DQ5022V CC 72CB4122CS1#172DQ5423DQ973CB1123NC 173V SS 24DQ1374CB5124NC 174V SS 25DQS175V SS 125V SS 175DQ5126DM176V SS 126V SS 176DQ5527V SS 77DQS8127DQ32177DQ5628V SS 78DM8128DQ36178DQ6029DQ1079CB2129DQ33179V CC 30DQ1480CB6130DQ37180V CC 31DQ1181V CC 131V CC 181DQ5732DQ1582V CC 132V CC 182DQ6133V CC 83CB3133DQS4183DQS734V CC 84CB7134DM4184DM735CK085NC 135DQ34185V SS 36V CC 86RESET#136DQ38186V SS 37CK0#87V SS 137V SS 187DQ5838V SS 88V SS 138V SS 188DQ6239V SS 89NC 139DQ35189DQ5940V SS 90V SS 140DQ39190DQ6341DQ1691NC 141DQ40191V CC 42DQ2092V CC 142DQ44192V CC 43DQ1793V CC 143V CC 193SDA 44DQ2194V CC 144V CC 194SA045V CC 95CKE1145DQ41195SCL 46V CC 96CKE0146DQ45196SA147DQS297NC 147DQS5197V CCSPD 48DM298NC 148DM5198SA249DQ1899A12149V SS 199NC 50DQ22100A11150V SS
200
NC
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WV3EG264M72ESFR-D4
ADVANCED FUNCTIONAL BLOCK DIAGRAM
White Electronic Designs
WV3EG264M72ESFR-D4
ADVANCED
DC OPERATING CONDITIONS
0°C T A 70°C
Parameter Symbol Min Max Unit Note Supply voltage (for device with a nominal V CC of 2.5V)V CC 2.3 2.7
I/O Supply voltage V CCQ 2.3 2.7V
I/O Reference voltage V REF0.49*V CCQ0.51*V CCQ V1
I/O Termination voltage (system)V TT V REF-0.04V REF+0.04V2
Input logic high voltage V IH(DC)V REF+0.15V CCQ+0.3V4
Input logic low voltage V IL(DC)-0.3V REF-0.15V4
Input Voltage Level, CK and CK# inputs V IN(DC)-0.3V CCQ+0.3V
Input Differential Voltage, CK and CK# inputs V ID(DC)0.3V CCQ+0.6V3
Input leakage current I I-22uA
Output leakage current I OZ-55uA
Output High Current(Normal strengh driver); V OUT = V TT + 0.84V I OH-16.8mA
Output High Current(Normal strengh driver); V OUT = V TT - 0.84V I OL16.8mA
Output High Current(Half strengh driver); V OUT = V TT + 0.45V I OH-9mA
Output High Current(Half strengh driver); V OUT = V TT - 0.45V I OL9mA
Notes:
1. Includes ± 25mV margin for DC offset on V REF, and a combined total of ± 50mV margin for all AC noise and DC offset on V REF, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on V REF and internal DRAM noise coupled to V REF, both of which may result in V REF noise. V REF should be de-coupled with an inductance of ≤ 3nH.
2. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to V REF, and must track variations in the DC level of V REF
3. V ID is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input speci? cations are relative
to a V REF envelop that has been bandwidth limited to 200MHz.
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to V SS V IN, V OUT-0.5 ~ 3.3V
Voltage on V CC & V CCQ pin relative to V SS V CC, V CCQ-1.0 ~ 3.6V
Storage Temperature T STG-55 ~ +150°C Operating Temperature T A0 ~ +70°C
Power dissipation – 1GB single mezzanine memory P D18W
Short circuit current I OS50mA
NOTE:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE
V CC 2.5V, V CCQ = 2.5V ±0.2V, T A = 25°C, f = 1MHz
Parameter Symbol Min Max Units
Input capacitance (A0 ~ A12, BA0 ~ BA1,RAS#,CAS#, WE# )C IN1911pF
Input capacitance (CKE0, CKE1)C IN2911pF
Input capacitance ( CS0#, CS1#)C IN3911pF
Input capacitance ( CLK0, CLK0#)C IN41112pF
Input capacitance ( DM0 ~ DM8)C IN51011pF
Data & DQS input/output capacitance (DQ0~DQ63)C OUT11011pF
Data input/output capacitance (CB0 ~ CB7)C OUT21011pF
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WV3EG264M72ESFR-D4
ADVANCED
DDR I DD SPECIFICATIONS AND CONDITIONS
0°C ≤ T CASE < +70°C; V CCQ = +2.5V ± 0.2V, V CC = +2.5V ± 0.2V
Symbol Conditions335262265Unit
1,2151,2151,080mA
I DD0Operating current - One bank Active-Precharge;
t RC = t RC(min); t CK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
I DD1Operating current - One bank operation;
1,4851,4851,350mA One bank open, BL = 4, Reads - Refer to the following page for detailed test condition
909090mA
I DD2P Percharge power-down standby current;
All banks idle; power - down mode; CKE = DDR266A & DDR266B; V IN = V REF for DQ, DQS and DM I DD2F Precharge Floating standby current; 810810720mA CS# > = V IH(min);All banks idle; CKE > = V IH(min); t CK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; V IN = V REF for DQ, DQS and DM 630630540mA I DD3P Active power - down standby current; one bank active; power-down mode; CKE = < V IL(max); t CK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; V IN = V REF for DQ, DQS and DM 900900810mA I DD3N Active standby current; CS# > = V IH(min); CKE> = V IH(min); one bank active; active - precharge; t RC = t RAS max; t CK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 1.530 1.5301,350mA I DD4R Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL = 2 at t CK = 100Mhz for DDR200, CL = 2 at t CK = 133Mhz for DDR266A, CL = 2.5 at t CK = 133Mhz for DDR266B ; 50% of data changing at every burst; l OUT = 0 m A 1,4401,4401,260mA I DD4W Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL = 2 at t CK = 100Mhz for DDR200, CL = 2 at t CK = 133Mhz for DDR266A, CL = 2.5 at t CK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst 5,2205,2205,040mA I DD5Auto refresh current; t RC = t RFC(min) - 8*t CK for DDR200 at 100Mhz, 10*t CK for DDR266A & DDR266B at 133Mhz; distributed refresh 909090mA I DD6Self refresh current; CKE = < 0.2V; External clock should be on; t CK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B 3,6903,6453,195mA I DD7A Orerating current - Four bank operation; Four bank interleaving with BL = 4 -Refer to the following page for detailed test condition Typical case: V CC = 2.5V, T = 25°C Worst case: V CC = 2.7V, T = 10°C Note: I DD speci? cations are based on Micron components. Other DRAM manufacturers speci? caitons may be different. WV3EG264M72ESFR-D4 ADVANCED White Electronic Designs AC TIMING PARAMETERS 0°C ≤ T CASE < +70°C; V CCQ = +2.5V ± 0.2V, V CC = +2.5V ± 0.2V Parameter Symbol 335262265 Unit Min Max Min Max Min Max Row cycle time t RC606565ns Refresh row cycle time t RFC727575ns Row active time t RAS4270K45120K45120K ns RAS# to CAS# delay t RCD182020ns Row precharge time t RP182020ns Row active to Row active t RRD121515ns Write recovery time t WR151515ns Last data in to Read command t WTR111t CK Col. address to Col. address t CCD111t CK Clock cycle time CL=2.0 t CK 7.5127.5121012ns CL=2.56127.5127.512ns Clock high level width t CH0.450.550.450.550.450.55t CK Clock low level width t CL0.450.550.450.550.450.55t CK DQS-out access time from t DQSCK-0.6+0.6-0.75+0.75-0.75+0.75ns Output data access time t AC-0.7+0.7-0.75+0.75-0.75+0.75ns Data strobe edge to ouput t DQSQ—0.4—0.5—0.5ns Read Preamble t RPRE0.9 1.10.9 1.10.9 1.1t CK Read Postamble t RPST0.40.60.40.60.40.6t CK CK to valid DQS-in t DQSS0.75 1.250.75 1.250.75 1.25t CK DQS-in setup time t WPRE000ns DQS-in hold time t WPRE0.250.250.25t CK DQS falling edge to CK ris-t DSS0.20.20.2t CK DQS falling edge from CK t DSH0.20.20.2t CK DQS-in high level width t DQSH0.350.350.35t CK DQS-in low level width t DQSL0.350.350.35t CK DQS-in cycle time t DSC0.9 1.10.9 1.10.9 1.1t CK Address and Control Input t IS0.750.90.9ns Address and Control Input t IH0.750.90.9ns Address and Control Input t IS0.8 1.0 1.0ns Address and Control Input t IH0.8 1.0 1.0ns Data-out high impedence time from CK/CK#t HZ+0.7+0.75+0.75ns Data-out low impedence time from CK/CK#t LZ-0.7+0.7-0.75+0.75-0.75+0.75ns Input Slew Rate (for input)t SL(I)0.50.50.5V/ns Input Slew Rate (for I/O pins)t SL(IO)0.50.50.5V/ns Output Slew Rate (x4,x8) Output Slew Rate Matching t SL(O) 1.0 4.5 1.0 4.5 1.0 4.5V/ns t SLMR0.67 1.50.67 1.50.67 1.5 Note: A C speci? cations are based on Micron components. Other DRAM manufacturers speci? caitons may be different. WV3EG264M72ESFR-D4 ADVANCED White Electronic Designs AC TIMING PARAMETERS 0°C ≤ T CASE < +70°C; V CCQ = +2.5V ± 0.2V, V CC = +2.5V ± 0.2V Parameter Symbol 335262265 Unit Min Max Min Max Min Max Mode register set cycle time t MRD121515ns DQ & DM setup time to DQS t DS0.450.50.5ns DQ & DM hold time to DQS t DH0.450.50.5ns Control & Address input t IPW 2.2 2.2 2.2ns DQ & DM input pulse width t DIPW 1.75 1.75 1.75ns Power down exit time t PDEX67.57.5ns Exit self refresh to non-Read t XSNR757575ns Exit self refresh to read command t XSRD200200200tCK Refresh interval time t REFI7.87.87.8us Output DQS valid window t QH t HP-t QHS—t HP-t QHS—t HP-t QHS—ns Clock half period t HP t CL min or t CH min — t CL min or t CH min — t CL min or t CH min —ns Data hold skew factor t QHS0.50.750.75ns DQS write postamble time t WPST0.40.60.40.60.40.6t CK Active to Read with Auto precharge command t RAP151520 Autoprecharge write recovery + Precharge time t DAL(t WR/t CK) + (t RP/t CK) (t WR/t CK) + (t RP/t CK) (t WR/t CK) + (t RP/t CK) t CK Note: A C speci? cations are based on Micron components. Other DRAM manufacturers speci? caitons may be different. SERIAL PRESENT DETECT INFORMATION Byte #Function described Function Supported Hex value 265262335265262335 0De? nes # of Bytes written into serial memory at module manufacturer128bytes80h 1Total # of Bytes of SPD memory device256bytes (2K-bit)08h 2Fundamental memory type SDRAM DDR07h 3# of row address on this assembly130Dh 4# of column address on this assembly110Bh 5# of module Rows on this assembly 2 Row02h 6Data width of this assembly64 bits48h 7 Data width of this assembly—00h 8VDDQ and interface standard of this assembly SSTL 2.5V04h 9DDR SDRAM cycle time at CAS Latency =2.57.5ns7ns6ns75h70h60h 10DDR SDRAM Access time from clock at CL=2.5±0.75±0.75±0.775h75h70h 11DIMM con? guration type(Non-parity, Parity, ECC)ECC02h 12Refresh rate & type7.8us & Self refresh82h White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED SERIAL PRESENT DETECT INFORMATION (cont'd) Byte #Function described Function Supported Hex value 265262335265262335 13Primary DDR SDRAM width x808h 14Error checking DDR SDRAM data width x808h 15Minimum clock delay for back-to-back random column address t CCD = 1CLK01h 16DDR SDRAM device attributes: Burst lengths supported2,4,80Eh 17DDR SDRAM device attributes: # of banks on each DDR SDRAM 4 banks04h 18DDR SDRAM device attributes: CAS Latency supported2,2.50Ch 19DDR SDRAM device attributes: CS Latency0CLK01h 20DDR SDRAM device attributes: WE Latency1CLK02h 26h 21DDR SDRAM module attributes Registered address & control inputs and On-card DLL 22DDR SDRAM device attributes: General+/-0.2V voltage tolerance C0h 23DDR SDRAM cycle time at CL =210ns7.5ns7.5ns A0h75h75h 24DDR SDRAM Access time from clock at CL =2±0.75±0.75±0.775h75h70h 25DDR SDRAM cycle time at CL =1.5———00h 26DDR SDRAM Access time from clock at CL =1.5———00h 27Minimum row precharge time (=t RP)20ns20ns18ns50h50h48h 28Minimum row activate to row active delay (=t RRD)15ns15ns12ns3Ch3Ch30h 29Minimum RAS to CAS delay (=t RCD)20ns20ns18ns50h50h48h 30Minimum active to precharge time (=t RAS)45ns45ns42ns2Dh2Dh2Ah 31Module ROW density512MB80h 32Command and address signal input setup time0.9ns0.9ns0.8ns A0h A0h80h 33Command and address signal input hold time0.9ns0.9ns0.8ns A0h A0h80h 34Data signal input setup time0.5ns0.5ns0.45ns50h50h45h 35Data signal input hold time0.5ns0.5ns0.45ns50h50h45h 36-40Superset information (may be used in future)—00h 41DDR SDRAM Minimum Active to Active/Auto Refresh Time (t RC)65ns65ns60ns41h41h3Ch 75ns75ns72ns4Bh4Bh48h 42DDR SDRAM Minimim Auto-Refresh to Active/Auto-Refresh Commmand Period (t RFC) 43DDR SDRAM Maximum Device Cycle Time (t CK max)13ns13ns12ns34h34h30h 44DDR SDRAM DQS-DQ Skew for DQS and associated DQ signals 0.50ns0.50ns0.45ns50h50h45h (t DQSQmax) 45DDR SDRAM Read Data Hold Skew Factor (t QHS)0.75ns0.75ns0.50ns75h75h50h 46Reserved00000000h00h00h 47DIMM Height Standard/Low pro? le01h 48-61Superset information (may be used in future)—00h 62SPD data revision code Initial release10h 63Checksum for Bytes 0 ~ 62—69h39h6Fh 64 - 127Manufacturer INFO—00h WV3EG264M72ESFR-D4 ADVANCED White Electronic Designs PACKAGE DIMENSIONS FOR D4 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)Tolerances: 0.15 (0.006) unless otherwise speci? ed ORDERING INFORMATION FOR D4 Part Number Speed CAS Latency t RCD t RP Height*WV3EG264M72ESFR335D4-x 166MHz/333Mb/s 2.53331.75mm (1.25")WV3EG264M72ESFR262D4-x 133MHz/266Mb/s 22231.75mm (1.25")WV3EG264M72ESFR265D4-x 133MHz/266Mb/s 2.5 3 3 31.75mm (1.25") NOTES: ? Consult Factory for availability of RoHS compliant products. (“G” = RoHS Compliant) ? V endor speci? c part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "-x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for quali? ed sourcing options. (M = Micron, S = Samsung & consult factory for others) ? Consult factory for availability of industrial temperature (-40°C to 85°C) option White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED PART NUMBERING GUIDE WV 3 E G 264M 72 E S F R xxx D4 -x G WEDC MEMORY DDR 2 GOLD DEPTH (Dual Rank) BUS WIDTH x8 2.5V FBGA REGISTERED SPEED (MHz) PACKAGE 200 PIN SO-DIMM COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED Document Title 1GB – 2x64Mx72 DDR SDRAM REGISTERED, w/PLL Revision History Rev #History Release Date Status Rev 0Created August 2005Advanced