Lab1_Verilog

Laboratory Exercise1

Switches,Lights,and Multiplexers

The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these devices.We will use the switches SW17?0on the DE2board as inputs to the circuit.We will use light emitting diodes(LEDs)and7-segment displays as output devices.

Preparation

You are required to write the Verilog code for Parts I to V.(Part VI is not required,and is provided only as suggested work.)For marking by the teaching assistants,you need to bring with you(pasted into your lab book) your Verilog code for Parts III,IV,and V.

In-lab Work

You are required to implement and test all of Parts I to V of the lab(not Part VI).But you only need to demonstrate to the teaching assisants Parts III,IV,and V.Your mark will be based on these three parts of the lab.

Part I

The DE2board provides18toggle switches,called SW17?0,that can be used as inputs to a circuit,and18red lights,called LEDR17?0,that can be used to display output values.Figure1shows a simple Verilog module that uses these switches and shows their states on the LEDs.Since there are18switches and lights it is convenient to represent them as vectors in the Verilog code,as shown.We have used a single assignment statement for all18 LEDR outputs,which is equivalent to the individual assignments

assign LEDR[17]=SW[17];

assign LEDR[16]=SW[16];

...

assign LEDR[0]=SW[0];

The DE2board has hardwired connections between its FPGA chip and the switches and lights.To use SW17?0 and LEDR17?0it is necessary to include in your Quartus II project the correct pin assignments,which are given in the DE2User Manual.For example,the manual speci?es that SW0is connected to the FPGA pin N25and LEDR0is connected to pin AE23.A good way to make the required pin assignments is to import into the Quartus II software the?le called DE2pin assignments.csv,which has been uploaded to the BlackBoard site for ECE241, in the labs section.The procedure for making pin assignments is described in the tutorial Quartus II Introduction using Verilog Design,which you have performed previously.

It is important to realize that the pin assignments in the DE2pin assignments.csv?le are useful only if the pin names given in the?le are exactly the same as the port names used in your Verilog module.The?le uses the names SW[0]...SW[17]and LEDR[0]...LEDR[17]for the switches and lights,which is the reason we used these names in Figure1.

//Simple module that connects the SW switches to the LEDR lights module part1(SW,LEDR);input [17:0]SW;//toggle switches output [17:0]LEDR;//red LEDs assign LEDR =SW;endmodule

Figure 1.Verilog code that uses the DE2board switches and lights.

Perform the following steps to implement a circuit corresponding to the code in Figure 1on the DE2board.1.Create a new Quartus II project for your circuit.Select Cyclone II EP2C35F672C6as the target chip,which is the FPGA chip on the Altera DE2board.2.Create a Verilog module for the code in Figure 1and include it in your project.

3.Include in your project the required pin assignments for the DE2board,as discussed https://www.wendangku.net/doc/7313405895.html,pile the project.

4.Download the compiled circuit into the FPGA chip.Test the functionality of the circuit by toggling the switches and observing the LEDs.Part II

Figure 2a shows a sum-of-products circuit that implements a 2-to-1multiplexer with a select input s .If s =0the multiplexer’s output m is equal to the input x ,and if s =1the output is equal to y .Part b of the ?gure gives a truth table for this multiplexer,and part c shows its circuit symbol.

x

s y

m

m

s m 01

x y

a) Circuit

b) Truth table c) Symbol

Figure 2.A 2-to-1multiplexer.

The multiplexer can be described by the following Verilog statement:

assign m =(～s &x)|(s &y);

You are to write a Verilog module that includes eight assignment statements like the one shown above to describe the circuit given in Figure 3a .This circuit has two eight-bit inputs,X and Y ,and produces the eight-bit output M .If s =0then M =X ,while if s =1then M =Y .We refer to this circuit as an eight-bit wide 2-to-1multiplexer.It has the circuit symbol shown in Figure 3b ,in which X ,Y ,and M are depicted as eight-bit wires.Perform the steps shown below.

s

a) Circuit b) Symbol

m 0

m 6

m 7

x 6x 0y 6

y 0

y 7

x 7s

M

Y

X Figure 3.An eight-bit wide 2-to-1multiplexer.

1.Create a new Quartus II project for your circuit.

2.Include your Verilog ?le for the eight-bit wide 2-to-1multiplexer in your https://www.wendangku.net/doc/7313405895.html,e switch SW 17on the DE2board as the s input,switches SW 7?0as the X input and SW 15?8as the Y input.Connect the SW switches to the red lights LEDR and connect the output M to the green lights LEDG 7?0.

3.Include in your project the required pin assignments for the DE2board.As discussed in Part I,these assignments ensure that the input ports of your Verilog code will use the pins on the Cyclone II FPGA that are connected to the SW switches,and the output ports of your Verilog code will use the FPGA pins connected to the LEDR and LEDG lights.

https://www.wendangku.net/doc/7313405895.html,pile the project.

5.Download the compiled circuit into the FPGA chip.Test the functionality of the eight-bit wide 2-to-1multiplexer by toggling the switches and observing the LEDs.Part III

In Figure 2we showed a 2-to-1multiplexer that selects between the two inputs x and y .For this part consider a circuit in which the output m has to be selected from ?ve inputs u ,v ,w ,x ,and y .Part a of Figure 4shows how we can build the required 5-to-1multiplexer by using four 2-to-1multiplexers.The circuit uses a 3-bit select input s 2s 1s 0and implements the truth table shown in Figure 4b .A circuit symbol for this multiplexer is given in part c of the ?gure.

Recall from Figure 3that an eight-bit wide 2-to-1multiplexer can be built by using eight instances of a 2-to-1multiplexer.Figure 5applies this concept to de?ne a three-bit wide 5-to-1multiplexer.It contains three instances of the circuit in Figure 4a .

a) Circuit

x v

m

s s s y

m

s 1s 2s 0x v u y

c) Symbol

m 00u v b) Truth table s 1s 0s 2000100w x 10111y 00110110111

y y y

Figure 4.A 5-to-1multiplexer.

M

s 1s 2s 0X V Y

Figure 5.A three-bit wide 5-to-1multiplexer.

Perform the following steps to implement the three-bit wide5-to-1multiplexer.

1.Create a new Quartus II project for your circuit.

2.Create a Verilog module for the three-bit wide5-to-1multiplexer.Connect its select inputs to switches

SW17?15,and use the remaining15switches SW14?0to provide the?ve3-bit inputs U to Y.Connect the SW switches to the red lights LEDR and connect the output M to the green lights LEDG2?0.

3.Include in your project the required pin assignments for the https://www.wendangku.net/doc/7313405895.html,pile the project.

4.Download the compiled circuit into the FPGA chip.Test the functionality of the three-bit wide5-to-1

multiplexer by toggling the switches and observing the LEDs.Ensure that each of the inputs U to Y can be properly selected as the output M.

Part IV

Figure6shows a7-segment decoder module that has the three-bit input c2c1c0.This decoder produces seven outputs that are used to display a character on a7-segment display.Table1lists the characters that should be displayed for each valuation of c2c1c0.To keep the design simple,only four characters are included in the table (plus the‘blank’character,which is selected for codes100?111).

The seven segments in the display are identi?ed by the indices0to6shown in the?gure.Each segment is illuminated by driving it to the logic value0.You are to write a Verilog module that implements logic functions that represent circuits needed to activate each of the seven https://www.wendangku.net/doc/7313405895.html,e only simple Verilog assign statements in your code to specify each logic function using a Boolean expression.

c2

c1

c0

Figure6.A7-segment decoder.

c2c1c0Character

000H

001E

010L

011O

100

101

110

111

Table1.Character codes.

Perform the following steps:

1.Create a new Quartus II project for your circuit.

2.Create a Verilog module for the 7-segment decoder.Connect the c 2c 1c 0inputs to switches SW 2?0,and connect the outputs of the decoder to the HEX0display on the DE2board.The segments in this display are called HEX00,HEX01,...,HEX06,corresponding to Figure 6.You should declare the 7-bit port

output [0:6]HEX0;

in your Verilog code so that the names of these outputs match the corresponding names in the DE2User Manual and the DE2pin assignments.csv ?le.

3.After making the required DE2board pin assignments,compile the project.

4.Download the compiled circuit into the FPGA chip.Test the functionality of the circuit by toggling the SW 2?0switches and observing the 7-segment display.Part V

Consider the circuit shown in Figure 7.It uses a three-bit wide 5-to-1multiplexer to enable the selection of ?ve characters that are displayed on a 7-segment https://www.wendangku.net/doc/7313405895.html,ing the 7-segment decoder from Part IV this circuit can display any of the characters H,E,L,O,and ‘blank’.The character codes are set according to Table 1by using the switches SW 14?0,and a speci?c character is selected for display by setting the switches SW 17?15.

An outline of the Verilog code that represents this circuit is provided in Figure 8.Note that we have used the circuits from Parts III and IV as subcircuits in this code.You are to extend the code in Figure 8so that it uses ?ve 7-segment displays rather than just one.You will need to use ?ve instances of each of the subcircuits.The purpose of your circuit is to display any word on the ?ve displays that is composed of the characters in Table 1,and be able to rotate this word in a circular fashion across the displays when the switches SW 17?15are toggled.As an example,if the displayed word is HELLO,then your circuit should produce the output patterns illustrated in Table 2.

SW 17SW 16SW 15SW 1412–SW 119–SW 86–SW 53–SW 20

–Figure 7.A circuit that can select and display one of ?ve characters.

module part5(SW,HEX0);

input[17:0]SW;//toggle switches

output[0:6]HEX0;//7-seg displays

wire[2:0]M;

mux3bit5to1M0(SW[17:15],SW[14:12],SW[11:9],SW[8:6],SW[5:3],SW[2:0],M);

char7seg H0(M,HEX0);

endmodule

//implements a3-bit wide5-to-1multiplexer

module mux3bit5to1(S,U,V,W,X,Y,M);

input[2:0]S,U,V,W,X,Y;

output[2:0]M;

...code not shown

endmodule

//implements a7-segment decoder for H,E,L,O,and‘blank’

module char7seg(C,Display);

input[2:0]C;//input code

output[0:6]Display;//output7-seg code

...code not shown

endmodule

Figure8.Verilog code for the circuit in Figure7.

SW17SW16SW15Character pattern

000H E L L O

001E L L O H

010L L O H E

011L O H E L

100O H E L L

Table2.Rotating the word HELLO on?ve displays.

Perform the following steps.

1.Create a new Quartus II project for your circuit.

2.Include your Verilog module in the Quartus II project.Connect the switches SW17?15to the select inputs of

each of the?ve instances of the three-bit wide5-to-1multiplexers.Also connect SW14?0to each instance of the multiplexers as required to produce the patterns of characters shown in Table2.Connect the outputs of the?ve multiplexers to the7-segment displays HEX4,HEX3,HEX2,HEX1,and HEX0.

3.Include the required pin assignments for the DE2board for all switches,LEDs,and7-segment displays.

Compile the project.

4.Download the compiled circuit into the FPGA chip.Test the functionality of the circuit by setting the proper

character codes on the switches SW14?0and then toggling SW17?15to observe the rotation of the characters.

Part VI

Extend your design from Part V so that is uses all eight7-segment displays on the DE2board.Your circuit should be able to display words with?ve(or fewer)characters on the eight displays,and rotate the displayed word when the switches SW17?15are toggled.If the displayed word is HELLO,then your circuit should produce the patterns shown in Table3.

SW17SW16SW15Character pattern

000H E L L O

001H E L L O

010H E L L O

011H E L L O

100E L L O H

101L L O H E

110L O H E L

111O H E L L

Table3.Rotating the word HELLO on eight displays.

Perform the following steps:

1.Create a new Quartus II project for your circuit and select as the target chip the Cyclone II EP2C35F672C6.

2.Include your Verilog module in the Quartus II project.Connect the switches SW17?15to the select inputs of

each instance of the multiplexers in your circuit.Also connect SW14?0to each instance of the multiplexers as required to produce the patterns of characters shown in Table3.(Hint:for some inputs of the multiplexers you will want to select the‘blank’character.)Connect the outputs of your multiplexers to the7-segment displays HEX7,...,HEX0.

3.Include the required pin assignments for the DE2board for all switches,LEDs,and7-segment displays.

Compile the project.

4.Download the compiled circuit into the FPGA chip.Test the functionality of the circuit by setting the proper

character codes on the switches SW14?0and then toggling SW17?15to observe the rotation of the characters. Copyright c 2006Altera Corporation.