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ACPL-332J

2.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (V CE ) Desaturation Detection, UVLO Fault Status Feedback and Active Miller Clamping

Data Sheet

Features

x Under Voltage Lock-Out Protection (UVLO)with Hysteresis x D esaturation D etection x Miller Clamping

x Open Collector Isolated fault feedback x “Soft”IGBT Turn-o?

x Fault Reset by next LED turn-on (low to high)after fault mute period x Available in SO-16package

x Safety approvals:UL approved,3750V RMS for 1minute,CSA approved,IEC/EN/DIN-EN 60747-5-2approved V IORM =891V PEAK

Speci?cations

x 2.5 A maximum peak output current x 2.0 A minimum peak output current

x 250 ns maximum propagation delay over temperature range

x 100 ns maximum pulse width distortion (PWD)x 15 kV/μs minimum common mode rejection (CMR) at V CM = 1500 V x I CC(max) < 5 mA maximum supply current x Wide V CC operating range: 15 V to 30 V over temperature range x 1.7 A Miller Clamp. Clamp pin short to V EE if not used x Wide operating temperature range: –40°C to 105°C

Applications

x Isolated IGBT/Power MOSFET gate drive x AC and brushless DC motor drives

x Industrial inverters and Uninterruptible Power Supply (UPS)

Description

The ACPL-332J is an advanced 2.5A output current,easy-to-use,intelligent gate driver which makes IGBT V CE fault protection compact,a?ordable,and easy-to implement.Features such as integrated V CE detection,under voltage lockout (UVLO),“soft”IGBT turn-o?,isolated open collector fault feedback and active Miller clamping provide maximum design ?exibility and circuit protec-tion.

The ACPL-332J contains a GaAsP LED.The LED is optically coupled to an integrated circuit with a power output stage.ACPL-332J is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications.The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200V and 150A.For IGBTs with higher ratings,the ACPL-332J can be used to drive a discrete power stage which drives the IGBT gate.The ACPL-332J has an insulation voltage of V IORM =891V PEAK .

Block Diagram

CC2

OUT CLAMP EE

LED

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

Lead (Pb) Free RoHS 6 fully compliant

R o H S 6 f u lly comp -xxxE denotes a

Pin Description

1 2 3 4 5 6 7 8

V E

V LED

DESAT

V CC2

V EE

V OUT

V CLAMP

V EE

V S

V CC1

FAULT

V S

CATHODE

ANODE

CATHODE

Pin Symbol Description

1V S Input Ground

2V CC1Positive input supply voltage. (4.5 V to 5.5 V)

3FAULT Fault output. FAULT changes from a high impedance state

to a logic low output within 5 μs of the voltage on the

DESAT pin exceeding an internal reference voltage of 7 V.

FAULT output is an open collector which allows the FAULT

outputs from all ACPL-332J in a circuit to be connected

together in a “wired OR” forming a single fault bus for inter-

facing directly to the micro-controller.

4V S Input Ground

5CATHODE Cathode

6ANODE Anode

7ANODE Anode

8CATHODE Cathode

9V EE Output supply voltage.

10V CLAMP Miller clamp

11V OUT Gate drive voltage output

12V EE Output supply voltage.

13V CC2Positive output supply voltage

14D ESAT D esaturation voltage input. When the voltage on D ESAT

exceeds an internal reference voltage of 6.5 V while the

IGBT is on, FAULT output is changed from a high impedance

state to a logic low state within 5 μs.

15V LED LED anode. This pin must be left unconnected for guaran-

teed data sheet performance. (For optical coupling testing

only)

16V E Common (IGBT emitter) output supply voltage.

Ordering Information

ACPL-332J is UL Recognized with 3750 Vrms for 1 minute per UL1577.

Part number

Option

Package

Surface

Mount Tape& Reel

IEC/EN/DIN EN

60747-5-2Quantity RoHS Compliant

ACPL-332J-000E SO-16X X45 per tube

-500E X X X850 per reel

To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry.

Example 1:

ACPL-332J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.

Example 2:

ACPL-332J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-

2 Safety Approval and RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘.

Package Outline Drawings

ACPL-332J 16-Lead Surface Mount Package

Dimensions in inches (millimeters)

Notes: Initial and continued variation in the color of the ACPL-332J’s white mold compound is normal and does note a?ect device performance or reliability.

Floating Lead Protrusion is 0.25 mm (10 mils) max.

0.0180.050TYPE NUMBER DATE CODE

0.025 (0.64)

LAND PATTERN RECOMMENDATION

Solder Re?ow Thermal Pro?le

Recommended Pb-Free IR Pro?le

Note: Non-halide ?ux should be used.

TIME (SECONDS)

T E M P E R A T U R E (°C )

ROOM T L

T smax T smin

T p TIME

T E M P E R A T U R E

NO TES:

THE TIME FROM 25°C to PEAK TEMPERATURE = 8 MINUTES MAX.T smax = 200 °C, T smin = 150°C Note: Non-halide ?ux should be used.

Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*

Description

Symbol Characteristic

Unit

Installation classi?cation per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 V rms for rated mains voltage ≤ 300 V rms for rated mains voltage ≤ 600 V rms I – IV I – IV I – III Climatic Classi?cation

55/100/21Pollution Degree (DIN VDE 0110/1.89)2Maximum Working Insulation Voltage

V IORM 891V peak Input to Output Test Voltage, Method b**,

V IORM x 1.875=V PR , 100% Production Test with t m =1 sec, Partial discharge < 5 pC V PR 1670V peak Input to Output Test Voltage, Method a**,

V IORM x 1.5=V PR , Type and Sample Test, t m =60 sec, Partial discharge < 5 pC V PR 1336V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 10 sec)V IOTM

6000

V peak

Safety-limiting values – maximum values allowed in the event of a failure.Case Temperature T S 175q C Input Current I S, INPUT 400mA Output Power

P S, OUTPUT 1200mW Insulation Resistance at T S , V IO = 500 V

R S

>109

* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classi?cation is class A in accordance with CECCOO802.

** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/

DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test pro?les.Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)

Regulatory Information

The ACPL-332J is approved by the following organizations:

IEC/EN/DIN EN 60747-5-2

Approval under:

IEC 60747-5-2 :1997 + A1:2002 EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01

Approval under UL 1577, component recognition program up to V ISO = 3750 V RMS . File E55361.

CSA

Approval under CSA Component Acceptance Notice #5, File CA 88324.

Table 2. Insulation and Safety Related Speci?cations

Parameter Symbol ACPL-332J Units Conditions

Minimum External Air Gap (Clearance)L(101)8.3Mm Measured from input terminals to output terminals,

shortest distance through air.

Minimum External Tracking (Creepage)L(102)8.3Mm Measured from input terminals to output terminals,

shortest distance path along body.

Minimum Internal Plastic Gap (Internal Clearance)0.5Mm Through insulation distance conductor to conductor,

usually the straight line distance thickness between

the emitter and detector.

Tracking Resistance

(Comparative Tracking Index)

CTI>175V DIN IEC 112/VDE 0303 Part 1

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings

Parameter Symbol Min.Max.Units Note Storage Temperature T S-55125°C

Operating Temperature T A-40105°C2 Output IC Junction Temperature T J125°C2 Average Input Current I F(AVG)25mA1

Peak Transient Input Current,

(<1 μs pulse width, 300pps)

I F(TRAN) 1.0A

Reverse Input Voltage V R5V

“High” Peak Output Current I OH(PEAK) 2.5A3“Low” Peak Output Current I OL(PEAK) 2.5A3 Positive Input Supply Voltage V CC1-0.5 5.5V

FAULT Output Current I FAULT8.0mA

FAULT Pin Voltage V FAULT-0.5V CC1V

Total Output Supply Voltage(V CC2 - V EE)-0.533V

Negative Output Supply Voltage(V E - V EE)-0.515V6 Positive Output Supply Voltage(V CC2 - V E)-0.533 - (V E - V EE)V

Gate Drive Output Voltage V O(PEAK)-0.5V CC2V

Peak Clamping Sinking Current I Clamp 1.7A

Miller Clamping Pin Voltage V Clamp-0.5V CC2V

DESAT Voltage V DESAT V E V E + 10V

Output IC Power Dissipation P O600mW2

Input IC Power Dissipation P I150mW2 Solder Re?ow Temperature Pro?le See Package Outline Drawings section

Table 4. Recommended Operating Conditions

Parameter Symbol Min.Max.Units Note Operating Temperature T A- 40105°C2

Total Output Supply Voltage(V CC2 - V EE)1530V7 Negative Output Supply Voltage(V E - V EE)015V4 Positive Output Supply Voltage(V CC2 - V E)1530 - (V E - V EE)V

Input Current (ON)I F(ON)812mA

Input Voltage (OFF)V F(OFF)- 3.60.8V

A CC2EE E EE

all Minimum/Maximum speci?cations are at Recommended Operating Conditions. Positive Supply Voltage used. Parameter Symbol Min.Typ.Max.Units Test Conditions Fig.Note

FAULT Logic Low Output Voltage V FAULTL0.10.4V I FAULT = 1.1 mA, V CC1 = 5.5V

0.10.4V I FAULT = 1.1 mA, V CC1 = 3.3V

FAULT Logic High Output Current I FAULTH0.020.5μA V FAULT = 5.5 V, V CC1 = 5.5V

0.0020.3μA V FAULT = 3.3 V, V CC1 = 3.3V

High Level Output Current I OH-0.5-1.5A V O = V CC2 - 42, 4,

5 -2.0A V O = V CC2 – 153

Low Level Output Current I OL0.5 1.5A V O = V EE + 2.53, 5,

2.0A V O = V EE + 153

Low Level Output Current

During Fault Condition

I OLF90140230mA V OUT - V EE = 14 V6

High Level Output Voltage V OH V CC-2.9V CC-2.0V I O = -650 μA4, 6,

7, 8, 9

Low Level Output Voltage V OL0.170.5V I O = 100 mA5, 7,

Clamp Pin

Threshold Voltage

V tClamp 2.0V

Clamp Low Level

Sinking Current

I CL0.35 1.1A V O = V EE + 2.58

High Level Supply Current I CC2H 2.55mA I O = 0 mA9, 10,

25,

Low Level

Supply Current

I CC2L 2.55mA I O = 0 mA

Blanking Capacitor

Charging Current

I CHG-0.13-0.24-0.33mA V DESAT = 2 V11, 279, 10

Blanking Capacitor

Discharge Current

I DSCHG1030mA V DESAT = 7.0 V28

DESAT Threshold V DESAT6 6.57.5V V CC2 -V E >V UVLO-129 UVLO Threshold V UVLO+10.511.612.5V V O > 5 V7, 9,

V UVLO-9.210.311.1V V O < 5 V7, 9,

12 UVLO Hysteresis(V UVLO+

- V UVLO-)

0.4 1.3V

Threshold Input Current

Low to High

I FLH 2.08mA I O = 0 mA, V O > 5 V

Threshold Input Voltage

High to Low

V FHL0.8V

Input Forward Voltage V F 1.2 1.6 1.95V I F = 10 mA

Temperature Coe?cient

of Input Forward Voltage

'V F/'T A-1.3mV/°C

Input Reverse

Breakdown Voltage

BV R5V I R = 10 P A

Input Capacitance C IN70pF f = 1 MHz, V F = 0 V

A CC2EE E EE

all Minimum/Maximum speci?cations are at Recommended Operating Conditions. Only Positive Supply Voltage used. Parameter Symbol Min.Typ.Max.Units Test Conditions Fig.Note

Propagation Delay Time to High Output Level t PLH100180250ns R g = 10 :,

C g = 10 nF,

f = 10 kHz,

Duty Cycle = 50%,

I F = 10 mA,

V CC2 = 30 V

1, 13,

14, 15,

16, 29

13, 15

Propagation Delay Time to Low Output Level t PHL100180250ns1, 13,

14, 15,

16, 29

Pulse Width Distortion PWD-10020100ns14, 17

Propagation Delay

Di?erence Between

Any Two Parts or Channels (t PHL - t PLH)

PDD

-350350ns17, 16

Rise Time t R50ns Fall Time t F50ns

DESAT Sense to 90%VO Delay t DESAT(90%)0.150.5μs C DESAT = 100pF, R g = 10 :,

C g = 10 nF, V CC2 = 30 V

17, 30,

DESAT Sense to 10% VO Delay t DESAT(10%)23μs C DESAT = 100pF, R g = 10 :,

C g = 10 nF, V CC2 = 30 V

18, 19,

20, 30,

DESAT Sense to Low Level FAULT Signal Delay t DESAT(FAULT)0.250.5μs C DESAT = 100pF, R F = 2.1 k:,

R g = 10 :, C g = 10 nF,

V CC2 = 30 V

30, 3718

DESAT Sense to DESAT Low Propagation Delay t DESAT(LOW)0.25μs C DESAT = 100pF, R F = 2.1 k:,

R g = 10 :, C g = 10 nF,

V CC2 = 30 V

30, 3719

DESAT Input Mute t DESAT(MUTE)5μs3720

RESET to High Level FAULT Signal Delay t RESET(FAULT)0.31 2.0μs C DESAT = 100pF, RF = 2.1 k:,

Rg = 10 :, Cg = 10 nF,

V CC1 = 5.5V, V CC2 = 30 V

0.8 1.5 2.5μs C DESAT = 100pF, R F = 2.1 k:,

Rg = 10 :, Cg = 10 nF,

V CC1 = 3.3V, V CC2 = 30 V

Output High Level Common Mode Transient Immunity |CM H|1525kV/μs T A = 25°C, I F = 10 mA

V CM = 1500 V, V CC2 = 30 V

31, 32,

33, 34

Output Low Level Common Mode Transient Immunity |CM L|1525kV/μs T A = 25°C, V F = 0 V

V CM = 1500 V, V CC2 = 30 V

31, 32,

33, 34

Table 7. Package Characteristics

Parameter Symbol Min.Typ.Max.Units Test Conditions Fig.Note

Input-Output Momentary Withstand Voltage V ISO3750V rms RH < 50%, t = 1 min.,

T A = 25°C

6, 7

Input-Output Resistance R I-O> 109:V I-O = 500 V7

Input-Output Capacitance C I-O 1.3pF freq=1 MHz

Output IC-to-Pins 9 &10

Thermal Resistance

T09-1030°C/W T A = 25°C

Notes:

1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.

2. In order to achieve the absolute maximum power dissipation speci?ed, pins 4, 9, and 10 require ground plane connections and may require

air?ow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air ?ow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating.

3. Maximum pulse width = 10 μs. This value is intended to allow for component tolerances for designs with I O peak minimum = 2.0 A. Derate

linearly from 3.0 A at +25°C to 2.5 A at +105°C. This compensates for increased I OPEAK due to changes in V OL over temperature.

4. This supply is optional. Required only when negative gate drive is implemented.

5. Maximum pulse width = 50 μs.

6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.

7. 15 V is the recommended minimum operating positive supply voltage (V CC2 - V E) to ensure adequate margin in excess of the maximum V UVLO+

threshold of 12.5V. For High Level Output Voltage testing, V OH is measured with a dc load current. When driving capacitive loads, V OH will approach V CC as I OH approaches zero units.

8. Maximum pulse width = 1.0 ms.

9. Once V O of the ACPL-332J is allowed to go high (V CC2 - V E > V UVLO+), the DESAT detection feature of the ACPL-332J will be the primary source of

IGBT protection. UVLO is needed to ensure DESAT is functional. Once V CC2 is increased from 0V to above V UVLO+, DESAT will remain functional until V CC2 is decreased below V UVLO-. Thus, the DESAT detection and UVLO features of the ACPL-332J work in conjunction to ensure constant IGBT protection.

10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.

11. This is the “increasing” (i.e. turn-on or “positive going” direction) of V CC2 - V E

12. This is the “decreasing” (i.e. turn-o? or “negative going” direction) of V CC2 - V E

13. This load condition approximates the gate load of a 1200 V/150A IGBT.

14. Pulse Width Distortion (PWD) is de?ned as |t PHL - t PLH| for any given unit.

15. As measured from I F to V O.

16. The di?erence between t PHL and t PLH between any two ACPL-332J parts under the same test conditions.

17. As measured from ANODE, CATHODE of LED to V OUT

18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.

19. This is the amount of time the DESAT threshold must be exceeded before V OUT begins to go low, and the FAULT output to go low. This is supply

voltage dependent.

20. Auto Reset: This is the amount of time when V OUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation (Auto

Reset) topic in the application information section.

21. Common mode transient immunity in the high state is the maximum tolerable dV CM/dt of the common mode pulse, V CM, to assure that the

output will remain in the high state (i.e., V O > 15 V or FAULT > 2 V). A 100 pF and a 2.1 kΩ pull-up resistor is needed in fault detection mode.

22. Common mode transient immunity in the low state is the maximum tolerable dV CM/dt of the common mode pulse, V CM, to assure that the

output will remain in a low state (i.e., V O < 1.0 V or FAULT < 0.8 V).

23. To clamp the output voltage at V CC - 3 V BE, a pull-down resistor between the output and V EE is recommended to sink a static current of 650 μA

while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used.

Figure 2. I OH vs. temperature Figure 3. I OL vs. temperature

Figure 4. V OH vs. temperature Figure 5. V OL

vs. temperature

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Figure 1. VOUT propagation delay waveforms

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Figure 8. I CL

vs. temperature

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2.25

2.35

2.55

V CC2 - OUTPUR SUPPLY VOLTAGE - V

I C C 2 - O U T P U T S U P P L Y C U R R E N T - m A

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Figure 10. I CC2 vs. V CC2Figure 11. I CHG vs. temperature

Figure 6. V OH vs. I OH Figure 7. V OL vs. I OL

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Figure 14. Propagation delay vs. supply voltage

Vcc - SUPPLY VOLTAGE - V

T P - P R O P A G A T I O N D E L A Y - n s

100

150

200

250

300

LOAD RESISTANCE - ohm

T P - P R O P A G A T I O N D E L A Y - m s

Figure 15. Propagation delay vs. load resistance

Figure 16. Propagation delay vs. load capacitance

010********

LOAD CAPACITANCE - nF

T P - P R O P A G A T I O N D E L A Y - m s

Figure 12. DESAT threshold vs. temperature

Figure 13. Propagation delay vs. temperature

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Figure 18. DESAT sense to 10% VOUT delay vs. temperature

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Figure 19. DESAT sense to 10% VOUT delay vs. load resistance 0.01.0

2.0

3.0

4.0

LOAD RESISTANCE - ohm

T D E S A T 10% - D E S A T S e n s e t o 10% V o D e l a y - u s

0.000

0.004

0.008

0.012

010********

LOAD CAPACITANCE - nF

T D E S A T 10% - D E S A T S e n s e t o 10% V o D e l a y - m s

Figure 20. DESAT sense to 10% VOUT delay vs. load capacitance

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Figure 17. DESAT sense to 90% VOUT delay vs. temperature

Figure 21. I OH Pulsed test circuit Figure 22. I OL Pulsed test circuit

Figure 23. V OH Pulsed test circuit

Figure 24. V OL Pulsed test circuit

Figure 25. I CC2H test circuit

Figure 26. I CC2L test circuit

Figure 27. I CHG Pulsed test circuit

Figure 28. I DSCHG test circuit

Figure 29. t PLH, t PHL, t f, t r, test circuit

V CM

Figure 30. t DESAT fault test circuit

V Figure 31. CMR Test circuit LED2 o?

Figure 32. CMR Test Circuit LED2 on

V CM Figure 33. CMR Test circuit LED1 o?

V CM Figure 34. CMR Test Circuit LED1 on

Application Information

Product Overview Description

The ACPL-332J is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT / MOSFET gate drive circuit with fault protection and feedback into one SO-16 package. Active Miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. An optically isolated power output stage drives IGBTs with power ratings of up to 150 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage di?erences that are common in industrial motor drives and other power switching applications. An output IC provides local protection for the IGBT to prevent damage during over current, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in “watchdog” circuit, UVLO

monitors the power stage supply voltage to prevent IGBT caused by insu?cient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design.

Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input control circuitry, the output power stage, and two optical channels. The output D etector IC is designed manufac-tured on a high voltage BiCMOS/Power D MOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal.

Under normal operation, the LED1 directly controls the IGBT gate through the isolated output detector IC, and LED2 remains o?. When an IGBT fault is detected, the output detector IC immediately begins a “soft” shutdown sequence, reducing the IGBT current to zero in a con-trolled manner to avoid potential IGBT damage from inductive over voltages. Simultaneously, this fault status is transmitted back to the input via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller.

D uring power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insu?cient gate voltage to the IGBT, by forcing the ACPL-332J’s output low. Once the output is in the high state, the DESAT (VCE) detection feature of the ACPL-332J provides IGBT pro-tection. Thus, UVLO and D ESAT work in conjunction to provide constant IGBT protection.Recommended Application Circuit

The ACPL-332J has an LED input gate control, and an open collector fault output suitable for wired ‘OR’ ap-plications. The recommended application circuit shown in Figure 36 illustrates a typical gate drive implementa-tion using the ACPL-332J. The following describes about driving IGBT. However, it is also applicable to MOSFET. Depending upon the MOSFET or IGBT gate threshold re-quirements, designers may want to adjust the VCC supply voltage (Recommended V CC = 17.5V for IGBT and 12.5V for MOSFET).

The two supply bypass capacitors (0.1 μF) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5mA) power supply su?ces. The desaturation diode D DESAT 600V/1200V fast recovery type, t rr below 75ns (e.g. ERA34-10) and capacitor C BLANK are necessary external components for the fault detection circuitry. The gate resistor R G serves to limit gate charge current and controls the IGBT collector voltage rise and fall times. The open collector fault output has a passive pull-up resistor R F (2.1 k:) and a 330 pF ?ltering capacitor, C F. A 47 k: pull down resistor R PULL-DOWN on V OUT provides a predictable high level output voltage (V OH). In this application, the IGBT gate driver will shut down when a fault is detected and fault reset by next cycle of IGBT turn on. Application notes are mentioned at the end of this datasheet.

Figure 35. Block Diagram of ACPL-332J

CC2

OUT

CLAMP

LED

Description of Operation Normal Operation

During normal operation, V OUT of the ACPL-332J is con-trolled by input LED current IF (pins 5, 6, 7 and 8), with the IGBT collector-to-emitter voltage being monitored through DDESAT. The FAULT output is high. See Figure 37.

Fault Condition

The DESAT pin monitors the IGBT V ce voltage. When the voltage on the DESAT pin exceeds 6.5 V while the IGBT is on, V OUT is slowly brought low in order to “softly” turn-o? the IGBT and prevent large di/dt induced voltages. Also

Figure 37. Fault Timing diagram

Figure 36. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp

activated is an internal feedback channel which brings the FAULT output low for the purpose of notifying the micro-controller of the fault condition.

Fault Reset

Once fault is detected, the output will be muted for 5 μs (minimum). All input LED signals will be ignored during the mute period to allow the driver to completely soft shut-down the IGBT. The fault mechanism can be reset by the next LED turn-on after the 5us (minimum) mute time. See Figure 37.

+ HVDC

-HVDC