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CY7C1399BL-20VC中文资料

32K x 8 3.3V Static RAM

CY7C1399B

Features

?Single 3.3V power supply

?Ideal for low-voltage cache memory applications ?High speed —10/12/15 ns ?Low active power —216 mW (max.)

?Low-power alpha immune 6T cell ?Plastic SOJ and TSOP packaging

Functional Description [1]

The CY7C1399B is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory ex-active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O 0through I/O 7) is written into the memory location addressed by the address present on the address pins (A 0 through A 14).Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the con-tents of the location addressed by the information on address pins is present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399B is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages.

Note:

1.For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at https://www.wendangku.net/doc/7216757352.html,.

Logic Block Diagram

Pin Configurations

123456789101114

162019181721242322Top View

SOJ 121325282726GND

A 6A 7A 8A 9A 10A 11A 12A 13WE V CC A 4A 3A 2A 1I/O 7I/O 6I/O 5I/O 4A 14A 5I/O 0I/O 1I/O 2CE OE A 0I/O 3

A 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODER

R O W D E C O D E R

S E N S E A M P S

INPUT BUFFER

POWER DOWN

WE OE

I/O 0CE I/O 1

I/O 2

I/O 332K x 8ARRAY

I/O 7

I/O 6I/O 5

I/O 4A 9

A 0A 11

A 13

A 12

A 14

A 10

Selection Guide

1399B-10

1399B-12

1399B-15

1399B-20

Maximum Access Time (ns)10121520Maximum Operating Current (mA)60555045Maximum CMOS Standby Current (μA)

500500500500L

元器件交易网https://www.wendangku.net/doc/7216757352.html,

Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature .................................–65°C to +150°C Ambient Temperature with

Power Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND [2]....–0.5V to +4.6V DC Voltage Applied to Outputs

in High Z State [2]....................................–0.5V to V CC + 0.5V DC Input Voltage [2].................................–0.5V to V CC + 0.5V

Output Current into Outputs (LOW).............................20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Pin Configuration

2223242526272812510111514131216191817Top View

TSOP 3420217

9OE A 1A 2A 3A 4WE V CC A 5A 6A 7A 8A 9A 0CE I/O 7I/O 6I/O 5GND I/O 2I/O 1I/O 4I/O 0A 14A 10A 11

A 13A 12

I/O 3Operating Range

Range Ambient Temperature V CC Commercial 0°C to +70°C 3.3V ±300 mV Industrial

–40°C to +85°C

3.3V ±300 mV

Electrical Characteristics Over the Operating Range [1]

7C1399B-10

7C1399B-12Parameter Description

Test Conditions

Min.Max.

Unit V OH Output HIGH Voltage V CC = Min., I OH = –2.0 mA 2.4

2.4

V V OL Output LOW Voltage V CC = Min., I OL = 4.0 mA

0.40.4V V IH Input HIGH Voltage 2.2V CC +0.3V 2.2V CC +0.3V V V IL Input LOW Voltage [2]–0.30.8–0.30.8V I IX Input Load Current –1+1–1+1μA I OZ Output Leakage Current GND ≤ V I ≤ V CC ,Output Disabled

–5+5–5

+5μA I OS Output Short Circuit Current [3]V CC = Max., V OUT = GND –300–300mA I CC V CC Operating Supply Current

V CC = Max., I OUT = 0 mA, f = f MAX = 1/t RC

6055mA I SB1Automatic CE Power-Down Current — TTL Inputs Max. V CC , CE ≥ V IH ,

V IN ≥ V IH , or V IN ≤ V IL ,f = f MAX 55mA L 44mA I SB2

Automatic CE Power-Down Current — CMOS Inputs [4]

Max. V CC , CE ≥ V CC – 0.3V , V IN ≥ V CC – 0.3V , or V IN ≤ 0.3V ,

WE ≥V CC – 0.3V or WE ≤0.3V , f =f MAX

500500μA L

50μA

Notes:

2.Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.

3.Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

4.Device draws low standby current regardless of switching on the addresses.

Electrical Characteristics Over the Operating Range (continued)

1399B-15

1399B-20Parameter Description

Test Conditions

Min.Max.

Unit V OH Output HIGH Voltage V CC = Min., I OH = –2.0 mA 2.4

2.4

V V OL Output LOW Voltage V CC = Min., I OL = 4.0 mA

0.40.4V V IH Input HIGH Voltage 2.2V CC +0.3V 2.2V CC +0.3V V V IL Input LOW Voltage –0.30.8–0.30.8V I IX Input Load Current –1+1–1+1μA I OZ Output Leakage Current GND ≤ V I ≤ V CC ,Output Disabled

–5+5–5

+5μA I OS Output Short Circuit Current [3]V CC = Max., V OUT = GND –300–300mA I CC V CC Operating Supply Current

V CC = Max., I OUT = 0 mA, f = f MAX = 1/t RC

5045mA I SB1

Automatic CE Power-Down Current — TTL Inputs Max. V CC , CE ≥ V IH , V IN ≥ V IH , or V IN ≤ V IL ,

f = f MAX

55mA L

44mA I SB2

Automatic CE Power-Down Current — CMOS Inputs [4]Max. V CC , CE ≥ V CC –0.3V , V IN ≥ V CC – 0.3V , or V IN ≤ 0.3V ,

WE ≥V CC –0.3V or WE ≤ 0.3V , f=f MAX

500500μA L

50μA

Capacitance [5]

Parameter

Description Test Conditions

Max.Unit C IN : Addresses Input Capacitance

T A = 25°C, f = 1 MHz, V CC = 3.3V

5pF C IN : Controls 6pF C OUT

Output Capacitance

AC Test Loads and Waveforms

Note:

5.Tested initially and after any design or process changes that may affect these parameters.

3.0V 3.3V OUTPUT

R1 317?

R2351?

C L

INCLUDING JIG AND SCOPE

GND

90%

10%

90%10%

≤3ns

OUTPUT

1.73V Equivalent to:

THéVENIN EQUIVALENT

ALL INPUT PULSES 167?

Switching Characteristics Over the Operating Range[6]

1399B-101399B-12 Parameter Description Min.Max.Min.Max.Unit Read Cycle

t RC Read Cycle Time1012ns

t AA Address to Data Valid1012ns

t OHA Data Hold from Address Change33ns

t ACE CE LOW to Data Valid1012ns

t DOE OE LOW to Data Valid55ns

t LZOE OE LOW to Low Z[7]00ns

t HZOE OE HIGH to High Z[7, 8]55ns

t LZCE CE LOW to Low Z[7]33ns

t HZCE CE HIGH to High Z[7, 8]56ns

t PU CE LOW to Power-Up00ns

t PD CE HIGH to Power-Down1012ns Write Cycle[9, 10]

t WC Write Cycle Time1012ns

t SCE CE LOW to Write End88ns

t AW Address Set-Up to Write End78ns

t HA Address Hold from Write End00ns

t SA Address Set-Up to Write Start00ns

t PWE WE Pulse Width78ns

t SD Data Set-Up to Write End57ns

t HD Data Hold from Write End00ns

t HZWE WE LOW to High Z[9]77ns

t LZWE WE HIGH to Low Z[7]33ns Notes:

6.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

I OL/I OH and capacitance C L = 30 pF.

7.At any given temperature and voltage condition, t HZCE is less than t LZCE, t HZOE is less than t LZOE, and t HZWE is less than t LZWE for any given device.

8.t HZOE, t HZCE, t HZWE are specified with C L = 5 pF as in AC T est Loads. Transition is measured ±500 mV from steady state voltage.

9.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

10.The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t HZWE and t SD.

Switching Characteristics Over the Operating Range[6] (Continued)

1399B-151399B-20 Parameter Description Min.Max.Min.Max.Unit Read Cycle

t RC Read Cycle Time1520ns t AA Address to Data Valid1520ns t OHA Data Hold from Address Change33ns t ACE CE LOW to Data Valid1520ns t DOE OE LOW to Data Valid67ns t LZOE OE LOW to Low Z[7]00ns t HZOE OE HIGH to High Z[7, 8]66ns t LZCE CE LOW to Low Z[7]33ns t HZCE CE HIGH to High Z[7, 8]77ns t PU CE LOW to Power-Up00ns t PD CE HIGH to Power-Down1520ns Write Cycle[9, 10]

t WC Write Cycle Time1520ns t SCE CE LOW to Write End1012ns t AW Address Set-Up to Write End1012ns t HA Address Hold from Write End00ns t SA Address Set-Up to Write Start00ns t PWE WE Pulse Width1012ns t SD Data Set-Up to Write End810ns t HD Data Hold from Write End00ns t HZWE WE LOW to High Z[9]77ns t LZWE WE HIGH to Low Z[7]33ns

Data Retention Characteristics (Over the Operating Range - L version only)

Parameter Description Conditions Min.Max.Unit V DR V CC for Data Retention 2.0V

I CCDR Data Retention Current Com’l V CC = V DR = 2.0V,

CE > V CC – 0.3V,

V IN > V CC – 0.3V or

V IN < 0.3V 020μA

t CDR Chip Deselect to Data

Retention Time

0ns t R Operation Recovery Time t RC ns

Data Retention Waveform

3.0V 3.0V t CDR

V DR >2V

DATA RETENTION MODE

t R

V CC

Switching Waveforms

Notes:

11.Device is continuously selected. OE, CE = V IL .12.WE is HIGH for read cycle.

13.Address valid prior to or coincident with CE transition LOW.

ADDRESS

DATA OUT

PREVIOUS DATA VALID

DATA VALID

t RC

t AA

t OHA

Read Cycle No. 1[11, 12]

50%

DATA VALID

t RC

t ACE

t DOE

t LZOE

t LZCE

t PU

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

ICC

ISB

t HZOE t HZCE

t PD

HIGH V CC SUPPLY CURRENT

Read Cycle No. 2[12, 13]

Notes:

14.Data I/O is high impedance if OE = V IH .

15.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.16.During this period, the I/Os are in the output state and input signals should not be applied.

Switching Waveforms (continued)

t HD

t SD

t PWE

t SA

t HA

t AW

t WC

DATA I/O

ADDRESS

t HZOE

DATA IN VALID

Write Cycle No. 1 (WE Controlled)[9, 14, 15]

NOTE 16

t WC

t AW

t SA

t HA

t HD

t SD

t SCE

DATA I/O

ADDRESS

DATA IN VALID

Write Cycle No. 2 (CE Controlled)[9, 14, 15]

DATA I/O

ADDRESS

t HD

t SD

t LZWE

t SA

t HA

t AW

t WC

t HZWE

DATA IN VALID

Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15]

NOTE 16

l product and comany names mentioned in this document may be the trademarks of their respective holders.

Truth Table

CE WE OE Input/Output Mode

Power

H X X High Z Deselect/Power-Down

Standby (I SB )L H L Data Out Read Active (I CC )L L X Data In Write

Active (I CC )L

High Z

Deselect, Output Disabled

Active (I CC )

Ordering Information

Speed (ns)Ordering Code Package Name Package Type

Operating Range 10

CY7C1399B-10VC V2128-Lead Molded SOJ

Commercial

CY7C1399B-10ZC Z2828-Lead Thin Small Outline Package CY7C1399BL-10VC V2128-Lead Molded SOJ

CY7C1399BL-10ZC

Z2828-Lead Thin Small Outline Package 12

CY7C1399B-12VC V2128-Lead Molded SOJ

CY7C1399B-12ZC Z2828-Lead Thin Small Outline Package CY7C1399BL-12VC V2128-Lead Molded SOJ

CY7C1399BL-12ZC Z2828-Lead Thin Small Outline Package CY7C1399B-12VI V2128-Lead Molded SOJ

Industrial CY7C1399B-12ZI

Z2828-Lead Thin Small Outline Package 15

CY7C1399B-15VC V2128-Lead Molded SOJ

Commercial CY7C1399B-15ZC Z2828-Lead Thin Small Outline Package CY7C1399BL-15VC V2128-Lead Molded SOJ

CY7C1399BL-15ZC Z2828-Lead Thin Small Outline Package CY7C1399B-15VI V2128-Lead Molded SOJ

Industrial CY7C1399B-15ZI

Z2828-Lead Thin Small Outline Package 20

CY7C1399B-20VC V2128-Lead Molded SOJ

Commercial CY7C1399B-20ZC Z2828-Lead Thin Small Outline Package CY7C1399BL-20VC V2128-Lead Molded SOJ

CY7C1399BL-20ZC Z2828-Lead Thin Small Outline Package CY7C1399B-20VI V2128-Lead Molded SOJ

Industrial CY7C1399B-20ZI

Z28

28-Lead Thin Small Outline Package

Package Diagrams

28-Lead(300-Mil)Molded SOJ V21

51-85031-B

Document History Page

Document Title: CY7C1399B 32K x 8 3.3V Static RAM Document Number: 38-05071

REV.ECN NO.ISSUE

DATE

ORIG. OF

CHANGE DESCRIPTION OF CHANGE

**10726405/25/01SZV Change from Spec #: 38-01102 to 38-05071

*A10753306/28/01MAX Add Low Power

*B11647209/17/02CEA Add applications foot note to data sheet, page 1.

*C224340See ECN RKF Option 1 of the Orientation ID on TSOP-I Package Diagram [Page #9]

removed