DM1105_datasheet_EN
DVB Receiving IC with PCI Interface
DM1105
Product Datasheet
Shenzhen SDMC Microelectronics Co.,LTD
ADD: Rm202,2/F,Block W1-B Bldg,Hi-tech
Industrial Park,Shenzhen,518057,
China
TEL: 86-755-26733992
FAX: 86-755-26733982
WEBSITE: https://www.wendangku.net/doc/7716885979.html,
Lable of Contents
1、 FEATURES (2)
2、 BLOCK DIAGRAM (3)
3、 SUMMARY (3)
4、 PIN CONNECTIONS (4)
5、 PINOUTS DESCRIPTION (4)
5.1 PCI Interface（50 pins） (4)
5.2 TS stream（19 pins） (6)
5.3 GPIO（18 pins） (7)
5.4 I2C Signal（2 pins） (7)
5.5 IR Input（1 pin） (7)
5.6 HOST Control（4 pins） (8)
5.7 Valid Data Indication Signal（1 pin） (8)
5.8 JTAG Signal（5 pins） (8)
5.9 Modules Test（4 pins） (8)
5.10 Descrambling Clock（1 pin） (9)
5.11 Power Supply（23 pins） (9)
6、 FUNCTIONAL DESCRIPTION (10)
6.1 PCI Bus (10)
6.2 I2C Control (10)
6.2.1 I2C write (11)
6.2.2 I2C read (11)
6.3 IR Receiving (12)
6.4 GPIO (12)
6.5 HOST Interface Modules (12)
6.6 Input Data Select (14)
6.6.1 Parallel TS stream (14)
6.6.2 Serial TS stream (14)
6.7 LED (14)
7、 Registers Description (15)
7.1 TS Control (16)
7.2 GPIO Interface (18)
7.3 PID index (19)
7.4 Odd/Even Secret Key Select (19)
7.5 HOST Interface (19)
7.6 PCI Interface (20)
7.7 CW (23)
7.8 PID (23)
7.9 IR Remote Control (24)
7.10 PROM (27)
8、 DC ELECTRICAL CHARACTERISTICS (28)
9、 APPLICATIONS (29)
9.1 Simulcrypt System (29)
9.2 Multicrypt System (29)
10、 PACKAGE OUTLINES (30)
1、 FEATURES
Supporting 188 /204 Byte transport stream reception.
Optional parallel or serial input mode; Optional input level.
Supporting 8 bit or 16 bit data input.
Receiving the 8/16 bit YUV digital video signal compliant with CCIR656 standard.
Compliant with bus PCI V2.1.
Supporting PCI bus master-slave mode.
Supporting host interface. Achieving PCMCIA interface through connecting with CI Module.
Supporting I2C interface.
Supporting Remote Controller function.
Embedded DVB descramble module.
Supporting 32 PIDs descramble simultaneously.
Protecting software patent rights by connecting with the encryption chip of DM2016.
PQFP128 Package.
2、 BLOCK DIAGRAM
DM1105 block diagram
3、 SUMMARY
DM1105is a chip to receive DVB transport stream with PCI interface. It can be used to receive Satellite, cable, and terrestrial digital TV singal, IP data, and the YUV video signal of 8/16 bits compliant with CCIR656 standard. Integrated with DVB standard descramble arithmetic, DM1105 can descramble 32 PIDs simultaneously. Remote Controller function is available. DM1105can interface with two PCMCIA connectors through the extension.
DM1105 can be applied in the fields of encrypted and free digital TV reception and IP data broadcast such as distant education, distant medical treatment,stock information,electronic government affairs,and so on.
4、 PIN CONNECTIONS
PCI_AD0103104105106107108109110111112113114115116117118119120121122123124125126127128
234567819101112131415161718192021222324252627282930313233343536373839
4041424344454647484950515253545556575859606162636465
66676869
70
7172737475767778798081828384858687888890919293949596979899100101102PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6
PCI_AD7PCI_CBE0#PCI_AD8PCI_AD9PCI_AD10PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_CBE1#PCI_PAR PCI_SERR#PCI_PERR#PCI_STOP#PCI_DEVSEL#PCI_TRDY#PCI_IRDY#PCI_FRAME#PCI_CBE2#PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_IDSEL PCI_CBE3#PCI_AD24PCI_AD25
PCI_AD26PCI_AD27
PCI_AD28PCI_AD29PCI_AD30PCI_AD31PCI_REQ#
PCI_INTA#PCI_RST#PCI_GNT#PCI_CLK IR LED_DATA
GPIO0/A0GPIO1/A1GPIO2/A2GPIO3/A3GPIO4/A4
GPIO5/A5GPIO6/A6GPIO7/A7GPIO12/A12G P I O 14/A 14G P I O 13/A 13G P I O 8/A 8G P I O 9/A 9G P I O 11/A 11G P I O 10/A 10T S _D 15/D 7T S _D 14/D 6T S _D 13/D 5T S _D 12/D 4T S _D 11/D 3T S _D 10/D 2T S _D 9/D 1T S _D 8/D 0I N T /T E S T _S 2W R #/S C A N _O U T R D #_T E S T _D O N E C S #/F A I L _H T S _D 1T S _D 0T S _D 2T S _D 3T S _D 4T S _D 5T S _D 6T S _D 7T S _V A L T S _S T R T T S _C L K S D A S C L G P I O 15GPIO16GPIO17SE/TEST_S0SI/TEST_S1SO
FB_APLL GND_APLL VCC_APLL CLK_APLL TRST TDI TCK TMS TDO GND VDD
GND GND
GND GND VDD
VDD VDD VDD VDD VDD V D D V D D V D D G N D G N D G N D GND GND GND DM1105
PQFP 128 Pin Configuration
5、 PINOUTS DESCRIPTION
5.1 PCI Interface （50 pins ）
Pin Number
Signal Name I/O Type Function
116 PCI_CLK I PCI
PCI clock 117 PCI_GNT# I PCI PCI grant indicate 118
PCI_RST#
I
PCI
PCI reset signal
119 PCI_INTA# O PCI OD PCI interrupt request signal
120 PCI_REQ# O PCI TS PCI request signal
122 PCI_AD31 B PCI PCI address data bit 31
123 PCI_AD30 B PCI PCI address data bit 30
124 PCI_AD29 B PCI PCI address data bit 29
125 PCI_AD28 B PCI PCI address data bit 28
126 PCI_AD27 B PCI PCI address data bit 27
128 PCI_AD26 B PCI PCI address data bit 26
1 PCI_AD25 B PCI PCI address data bit 25
2 PCI_AD24 B PCI PCI address data bit 24
3 PCI_CBE3# B PCI PCI valid byte indication, active low
configuration operation indication
PCI
4 PCI_IDSEL
I PCI
6 PCI_AD23 B PCI PCI address data bit 23
7 PCI_AD22 B PCI PCI address data bit 22
8 PCI_AD21 B PCI PCI address data bit 21
9 PCI_AD20 B PCI PCI address data bit 20
10 PCI_AD19 B PCI PCI address data bit 19
12 PCI_AD18 B PCI PCI address data bit 18
13 PCI_AD17 B PCI PCI address data bit 17
14 PCI_AD16 B PCI PCI address data bit 16
15 PCI_CBE2# B PCI PCI valid byte indication, active low
16 PCI_FRAME# B PCI PCI frame start
18 PCI_IRDY# B PCI PCI master device ready
19 PCI_TRDY# B PCI PCI slave device ready
20 PCI_DEVSEL# B PCI PCI slave device response signal
21 PCI_STOP# B PCI PCI transport stop
22 PCI_PERR# B PCI PCI non-Special Cycle data parity error 24 PCI_SERR# B PCI OD PCI address and Special Cycle data
parity error
25 PCI_PAR B PCI PCI even parity bit
B PCI PCI valid byte indication，active low
26 PCI_CBE1#
27 PCI_AD15 B PCI PCI address data bit 15
28 PCI_AD14 B PCI PCI address data bit 14
30 PCI_AD13 B PCI PCI address data bit 13
31 PCI_AD12 B PCI PCI address data bit 12
32 PCI_AD11 B PCI PCI address data bit 11
33 PCI_AD10 B PCI PCI address data bit 10
34 PCI_AD9 B PCI PCI address data bit 9
36 PCI_AD8 B PCI PCI address data bit 8
37 PCI_CBE0# B PCI PCI valid byte indication, active low
38 PCI_AD7 B PCI PCI address data bit 7
39 PCI_AD6 B PCI PCI address data bit 6
40 PCI_AD5 B PCI PCI address data bit 5
42 PCI_AD4 B PCI PCI address data bit 4
43 PCI_AD3 B PCI PCI address data bit 3
44 PCI_AD2 B PCI PCI address data bit 2
45 PCI_AD1 B PCI PCI address data bit 1
46 PCI_AD0 B PCI PCI address data bit 0
5.2 TS stream（19 pins）
Pin Number Signal Name I/O Type Function
69 TS_CLK I CMOS 5 TS clock
70 TS_STRT I CMOS 5D TS stream packet start
71 TS_VAL I CMOS 5D Valid data indication
72 TS_D7 I CMOS 5D Data input bit 7
73 TS_D6 I CMOS 5D Data input bit 6
74 TS_D5 I CMOS 5D Data input bit 5
75 TS_D4 I CMOS 5D Data input bit 4
76 TS_D3 I CMOS 5D Data input bit 3
77 TS_D2 I CMOS 5D Data input bit 2
79 TS_D1 I CMOS 5D Data input bit 1
80 TS_D0 I CMOS 5D Data input bit 0
5M Data input bit 8（16 bit mode）or HOST
CMOS
86 TS_D8/D0
B
data bit 0（HOST mode）
87 TS_D9/D1
CMOS
5M Data input bit 9（16 bit mode）or HOST
B
data bit 1（HOST mode）
5M Data input bit 10（16 bit mode）or
CMOS
88 TS_D10/D2
B
HOST data bit 2（HOST mode）
5M Data input bit 11（16 bit mode）or HOST
CMOS
89 TS_D11/D3
B
data bit 3（HOST mode）
91 TS_D12/D4
CMOS
5M Data input bit 12（16 bit mode）or
B
HOST data bit 4（HOST mode）
CMOS
5M Data input bit 13（16 bit mode）or
B
92 TS_D13/D5
HOST data bit 5（HOST mode）
CMOS
5M Data input bit 14（16 bit mode）or
93 TS_D14/D6
B
HOST data bit 6（HOST mode）
5M Data input bit 15（16 bit mode）or
CMOS
94 TS_D15/D7
B
HOST data bit 7（HOST mode）
5.3 GPIO（18 pins）
Pin Number Signal Name I/O Type Function
63 GPIO17 B CMOS 5M GPIO port 17
64 GPIO16 B CMOS 5M GPIO port 16
65 GPIO15 B CMOS 5M GPIO port 15
95 GPIO10/A10 B CMOS 5M GPIO or HOST address bit 10
97 GPIO11/A11 B CMOS 5M GPIO or HOST address bit 11
98 GPIO9/A9 B CMOS 5M GPIO or HOST address bit 9
99 GPIO8/A8 B CMOS 5M GPIO or HOST address bit 8
100 GPIO13/A13 B CMOS 5M GPIO or HOST address bit 13
101 GPIO14/A14 B CMOS 5M GPIO or HOST address bit 14
103 GPIO12/A12 B CMOS 5M GPIO or HOST address bit 12
104 GPIO7/A7 B CMOS 5M GPIO or HOST address bit 7
105 GPIO6/A6 B CMOS 5M GPIO or HOST address bit 6
106 GPIO5/A5 B CMOS 5M GPIO or HOST address bit 5
107 GPIO4/A4 B CMOS 5M GPIO or HOST address bit 4
109 GPIO3/A3 B CMOS 5M GPIO or HOST address bit 3
110 GPIO2/A2 B CMOS 5M GPIO or HOST address bit 2
111 GPIO1/A1 B CMOS 5M GPIO or HOST address bit 1
112 GPIO0/A0 B CMOS 5M GPIO or HOST address bit 1 5.4 I2C Signal（2 pins）
Pin Number Signal Name I/O Type Function
66 SCL O CMOS M OD I2C clock
67 SDA
CMOS
5M I2C data
B
5.5 IR Input（1 pin）
Pin Number Signal Name I/O Type Function 114 IR I CMOS 5 Trig IR signal input
5.6 HOST Control（4 pins）
Pin Number Signal Name I/O Type Function
81 CS#/FAIL_H O CMOS M HOST chip select or FAIL_H in
test mode
82 RD#/TEST_DONE O CMOS M HOST read or TEST_DONE in
test mode
83 WR#/SCAN_OUT O CMOS M HOST write or SCAN_OUT in test
mode
85 INT/TEST_S2 I CMOS 5 Trig HOST interrupt input or TEST_S2
in test mode
5.7 Valid Data Indication Signal（1 pin）
Pin Number Signal Name I/O Type Function 113 LED_DATA O CMOS M Data transfer indication
5.8 JTAG Signal（5 pins）
Pin Number Signal Name I/O Type Function
48 TDO O CMOS TS M JTAG data output
49 TCK I CMOS 5D JTAG clock
50 TMS I CMOS 5D JTAG mode select
51 TDI I CMOS 5D JTAG data input
52 TRST I CMOS 5D JTAG reset
5.9 Modules Test（4 pins）
Pin Number Signal Name I/O Type Function
59 SI/TEST_S1 I CMOS 5D SCAN test input or TEST_S1 test
mode
60 SO O CMOS M SCAN output
61 SE/TEST_S0 I CMOS 5D SCAN enable orTEST_S0 in test
mode
57 FB_APLL O CMOS M APLL based frequency output
5.10 Descrambling Clock（1 pin）
Pin Number Signal Name I/O Type Function
54 CLK_APLL I CMOS 5 Analog Phase Lock Loop clock
input
5.11 Power Supply（23 pins）
Pin Number Signal Name Function
Supply 11,23,35,47,62,78,90,102,115,127 VDD Power
5,17,29,41,53,58,68,84,96,108,121 GND Ground
55 VCC_APLL Analog Phase Lock Loop power
56 GND_APLL Analog Phase Lock Loop ground
Remarks：CMOS CMOS
LEVEL
5 5V Tolerant
Trig Schmitt Trigger
D Inernal Pull_down
Drain
OD Open
M 4mA Output current
output
TS Tri_state
6、 FUNCTIONAL DESCRIPTION
6.1 PCI Bus
DM1105 is a chip to receive DVB transport stream with PCI interface. DM1105 is compliant with PCI2.1 bus. PCI target and PCI master device is achieved.
Control registers are mapped to PCI IO Space. I2C control, HOST interface, GPIO control and descrambling control can be operated by PCI IO ports.
When DM1105 acts as master device to apply PCI bus and starts PCI DMA transfer data to designated memory. data length of every DMA is 128*4 bytes. User may set register INTCNT (@44H) to control how many times DMA transfer generate an interrupt. DMA data buffer structure is cycle buffer structure. The start address (STADR: 38H ) of data buffer and length ( RLEN: 3CH ) may be set. After interrupting every time, software may know transfer data length by read pointer(WRP: 40H ) and write pointer of last interrupt. Because of cycle buffer structure, the capacity need enough big and data length of DMA interrupt twice at least. Thus DMA data won’t cover unsettled data.
User may customize PCI configuration information, such as Verdor ID, Device ID, Subsystem Vendor ID, Subsystem ID, Min_Gnt, Max_Lat, Class Code, Revision ID and so on. User may store these configuration information in EEPROM memory with I2C interface (24C01 ). When power on, DM1105 can read out these information as PCI configuration information automatically.
6.2 I2C Control
DM1105 can use as I2C master device and can’t use as I2C slave device, not supporting multi-matster mode. DM1105 assign 64 byte PCI IO space to I2C control. The 64 byte can only be operated as byte device.
Distribution of 64 bytes show as below:
80H 81H 82H 83H
BFH
Bit7
Bit6REV REV
OK
BUSY
ST ……DATA
LEN[5:0]Bit5---Bit0
I 2C IO Space Assignment
6.2.1 I 2C write
If want to write I 2C device, Firstly, inquire I 2C status register (@81H). Write operation won’t be active until BUSY=’0’. Then write I 2C device address to 82H, register address to 83H and other data. Finally, write I 2C operation length (LEN[5:0]=length of data+2) and ST=1 to control register (@80H) to start I 2C operation. Inquire I 2C status register (@81H). If BUSY=’0’ and OK=’1’, transmit end and transmit data right. If BUSY=’0’ and OK=’0’, transmit stop and transmit data is error. If BUSY =’1’, transmit don’t stop.
6.2.2 I 2C read
I 2C read operation includes two steps.
First, set I 2C register address by writing I 2C. Inquire I 2C status register (@81H) and don’t start read operation until BUSY=”0”. Then write I 2C device address to 81H and register address to 83H. Finally, write I 2C operation length (LEN[5:0]=2) and ST=’1’ to control register (@80H) to start write I 2C operation.
Second, read I 2C operation. Inquire I 2C status register (@81H) and don’t read operation until BUSY=’1’. Then write I 2C device address to 82H and data address to 83H. Finally, write I 2C operation length (LEN[5:0]=2) and ST=1 to control register (@80H) to start read I 2C operation. The data read out stores in internal memory. The first data stores in 83H of IO space. Inquiry I 2C status register (@81H), if BUSY=’0’ and OK=”1”, data may be read out.
6.3 IR Receiving
IR reveiving module of DM1105, achieves hardware decoding function, and supports IR encoded mode, including NEC code and RC5 code. Encoded mode may select by mode register ( @68H ).
IR receiving module supports systematic code compare function. If the systematic code of receiving key code is different from the systematic code set, give up this key code.
IR receiving module supports inquiry and interrupt operation mode. Enable IR interrupt is interrupt operation mode, otherwise it is inquiry mode.
Use IR function: Firstly set IR mode ( RC5 code or NEC code ), then set systematic code, IR interrupt register, IR control register ( systematic code verify and IR enable ), finnally read/write IR code and clear IR interrupt.
6.4 GPIO
When using GPIO ports, firstly set the registers (@018H) of GPIO and HOST relating. If HOST enabled, only use 3 GPIO ports. Then set GPIO control registers and set input/output. Finally write or read out data from GPIOVAL register.
6.5 HOST Interface Modules
DM1105 achieves a general 8-bit HOST interface and has 15 bit address lines. DM1105 support interrupt input, interrupt trigger mode and interrupt polarity optional. The cycle of HOST read/write operation may configure ( HOST control register address : 18H ).
In order to save IO pins, HOST interface and other modules share IO ports:
HOST data bit share with MSB 8 bit of 16 bit data extended.
HOST address of 15 bit share with GPIO0-GPIO14 address.
So, when HOST interface enabled, DM1105 doesn’t support 16 bit data input, only support 3 GPIO ports.
HOST interface read cycle timing is as Figure below, The cycle of HOST read operation In Figure below is eight PCI clocks.
S1 S2 S3.. S7 S8 S9 S10
HOST read timing
HOST interface write cycle timing is as Figure below The cycle of HOST write operation in Figure below is eight PCI clocks.
S0 S1 S2… S7 S8 S9 S10.
HOST read timing
HOST write operation flow: Software start PCI IO write operation and hardware transfer PCI IO write operation to HOST write timing.
HOST read operation flow: Software start PCI IO write operation and hardware transfer PCI IO write operation to HOST read timing. Then start read operation in HOST bus. Hardware stores the data read out in registers and software start PCI IO read operation and read back the data.
When using HOST read/write operation, firstly set HOST control register and HOST interrupt register, then start HOST read/write transfer, finally clear HOST interrupt after transfer stop.
6.6 Input Data Select
DM1105 supports parallel TS stream input, serial TS stream input, packet synchronous mode, data valid mode, CCIR656 8/16 data mode. The polarity of Synchronous signal and valid data signal is optional.
6.6.1 Parallel TS stream
Parallel TS stream includes 8/16 bit TS stream and sequential/non-sequential TS stream. The polarity of Synchronous signal and valid data signal is optional. The value of settings may be modified in registers.
6.6.2 Serial TS stream
Serial TS stream includes 8/16 bit TS stream and sequential/non-sequential TS stream. The polarity of Synchronous signal and valid data signal is optional. The value of settings may be modified in registers.
6.7 LED
When data is tranferred, pin LED_DATA generates continuous pulse. The pulse can drive LED to flash.
7、 Registers Description
The following is internal register of DM1105, not including PCI configuration register.
Address Name R/W Description
TS Control
00H TSCTR R/W input TS pattern and control
04H DTALENTH R/W the length of input data
GPIO Interface
08H GPIOVAL R/W the value of GPIO
0CH GPIOCTR R/W GPIO control
PID serial number
10H PIDN R/W indes of PID and CW set currently
Odd-even secret key select
14H CWSEL R/W provide odd-even secret key select
HOST Command Interface
18H HOST_CTR R/W HOST interface control register
1CH HOST_AD R/W HOST interface address and data register
PCI Interface
30H CR R/W command register
34H RST W reset register ( reset chip )
38H STADR R/W receiving data memory start/stop address 3CH RLEN R/W DMA buffer length
40H WRP R DMA write pointer
44H INTCNT R/W DMA counter per interrupt
48H INTMAK R/W interrupt mask register
4CH INTSTS R interrupt status register
CW Value
50-57H ODD R/W 64 bit odd secret key
58-5FH EVEN R/W 64 bit even secret key
PID Value
value，descrambling control
PID
60H PID R/W
IR Control
64H IRCTR R/W IR control register
68H IRMODE R/W IR mode select register
System
code
6CH SYSTEMCODE R/W
code
70H IRCODE R IR
I2C Interface
I2C control, including start flag and length 80H I2C CTR R/W
I2C status
81H I2C STS R
I2C data
82H I2C DAT R/W
……………………
I2C data
BFH I2C DAT R/W
7.1 TS Control
TSCTR:00H
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TS_STRTP TS_VALP R R R R R MSBFIRST Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WIDTH_EXT Path_sel Ts_mode SI ALPAS CPRPID TSPES FEPAK TS_STRTP TS_STRT palority select.
=’1’ active high
=’0’ active low. The default is ’1’.
TS_VALP TS_VAL palority select.
=’1’ active high.
=’0’ active low. The default is ’1’.
MSBFIRST MSB first or LSB first select during serial mode.
=’1’ MSB first.
=’0’ LSB first. The default is’1’.
WIDTH_EXT Bit extension enable flag.
=’1’ 16-bit data receiving mode.
= ’0’ 8-bit data receiving mode. The default is ’0’.
Path_sel
=’1’ data path is 16 bit operation.
=’0’ data path is TS processing module. The default is’0’.
Ts_mode
=’1’ packet synchronous mode input.
=‘0’ valid data mode input. The default is’1’.
SI
=’1’ serial data input.
=’0’ parallel data input. The default is ‘0’.
ALPAS all pass flag.
=’0’ Whatever CPRPID value is, it is necessary to compare PID value.
If PID value is equal, data scramble and descrambling control bit is ‘1’, and start
descrambling. If no scrambling, receive data directly.
=’1’ receiving all data. If CPRPID=’0’, it isn’t necessary to compare PID .
If CPRPID=’1’, compare PID value. When the value is equal, start descrambling. If
no equal, receive data directly. The default is’0’.
CPRPID relevant to ALPAS The default is ’0’.
TSPES TS/PES select.
=’1’ descrambling in TS layer.
=’0’ descrambling in PES layer. The default is ’1’.
FEPAK filter empty packet flag.
=’1’ filter TS stream empty packet.
=’0’ don’t filter empty packet. The default is’0’.
DATLENTH: 04H
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
B7 B6 B5 B4 B3 B2 B1 B0
DATLENTH: The length of data package, in unit BYTE, For ts, you can set it to 188/204.
7.2 GPIO Interface
GPIOVAL:08H
Bit31 Bit30 Bit29 Bit28 Bit27 Bit26 Bit25 Bit24
Bit17 Bit16
B16
B17
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
B15 B14 B13 B12 B11 B10 B9 B8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
B7 B6 B5 B4 B3 B2 B1 B0
B[14:0] B[14:0] is used as HOST address H_A[14:0] if enable HOST interface mode. B[14:0] is used as GPIO[14:0] if disable HOST interface mode. And each vallue has corresponding value in
GPIO ports.
B[17:15] B[17:15] is used as GPIO[17:15].
GPIOCTR:0CH
Bit31 Bit30 Bit29 Bit28 Bit27 Bit26 Bit25 Bit24
Bit23 Bit22 Bit21 Bit20 Bit19 Bit18 Bit17 Bit16
B16
B17
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
B15 B14 B13 B12 B11 B10 B9 B8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
B7 B6 B5 B4 B3 B2 B1 B0
B[14:0]: If disable host interface, =’1’, direction of GPIO[14:0] is input; =’0’, direction of GPIO[14:0] is output. If enable host interface, B[14:0] are unuseful.the default of each bit of B[14:0] is ‘1’.
B[17:15] =’1’, direction of GPIO[17:15] is input.
=’0’, direction of GPIO[17:15] is output.
7.3 PID index
PIDN:10H
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIDN0 PIDN4
PIDN1
PIDN3
PIDN2
PID index
7.4 Odd/Even Secret Key Select
CWSEL:14H
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ODDK1
EVENK1
EVENK0
ODDK0
ODDK [1:0] control flag of odd secret key.
EVENK [1:0] control flag of even secret key.
When TS stream scrambling flag equal to the value of ODDK [1:0]，secret key switch to odd secret key; When TS stream scrambling flag equal to the value of EVENK [1:0]，secret key switch to even secret key.
7.5 HOST Interface
HOST_CTR:18H
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Cyc_b4 Cyc_b3 Cyc_b2 Cyc_b1 Cyc_b0
HOST_en Int_lev_sel
Event_level
HOST_en =’1’, HOST enabled.
=’0’, HOST prohibitted. The default is ‘0’.